2020-12-04 07:53:41 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Linaro Ltd
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/interconnect-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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2021-10-21 13:24:42 +00:00
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#include <linux/pm_domain.h>
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2021-09-03 23:24:14 +00:00
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#include <linux/regmap.h>
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2020-12-04 07:53:41 +00:00
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#include <linux/slab.h>
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#include "smd-rpm.h"
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2022-07-12 01:59:27 +00:00
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#include "icc-common.h"
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2020-12-04 07:53:41 +00:00
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#include "icc-rpm.h"
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2021-12-15 00:23:21 +00:00
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/* QNOC QoS */
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#define QNOC_QOS_MCTL_LOWn_ADDR(n) (0x8 + (n * 0x1000))
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#define QNOC_QOS_MCTL_DFLT_PRIO_MASK 0x70
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#define QNOC_QOS_MCTL_DFLT_PRIO_SHIFT 4
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#define QNOC_QOS_MCTL_URGFWD_EN_MASK 0x8
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#define QNOC_QOS_MCTL_URGFWD_EN_SHIFT 3
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2021-09-03 23:24:14 +00:00
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/* BIMC QoS */
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#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n))
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#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n))
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#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i))
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#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000
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#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300
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#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3
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#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8
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#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f
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#define M_BKE_EN_EN_BMASK 0x1
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/* NoC QoS */
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#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000))
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#define NOC_QOS_PRIORITY_P1_MASK 0xc
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#define NOC_QOS_PRIORITY_P0_MASK 0x3
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#define NOC_QOS_PRIORITY_P1_SHIFT 0x2
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#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
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#define NOC_QOS_MODEn_MASK 0x3
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2021-12-15 00:23:21 +00:00
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static int qcom_icc_set_qnoc_qos(struct icc_node *src, u64 max_bw)
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{
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struct icc_provider *provider = src->provider;
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struct qcom_icc_provider *qp = to_qcom_provider(provider);
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struct qcom_icc_node *qn = src->data;
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struct qcom_icc_qos *qos = &qn->qos;
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int rc;
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rc = regmap_update_bits(qp->regmap,
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qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
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QNOC_QOS_MCTL_DFLT_PRIO_MASK,
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qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT);
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if (rc)
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return rc;
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return regmap_update_bits(qp->regmap,
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qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
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QNOC_QOS_MCTL_URGFWD_EN_MASK,
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!!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT);
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}
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2021-09-03 23:24:15 +00:00
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static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp,
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2021-09-03 23:24:14 +00:00
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struct qcom_icc_qos *qos,
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int regnum)
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{
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u32 val;
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u32 mask;
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val = qos->prio_level;
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mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK;
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val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT;
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mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK;
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/* LIMITCMDS is not present on M_BKE_HEALTH_3 */
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if (regnum != 3) {
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val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT;
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mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK;
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}
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2021-09-03 23:24:15 +00:00
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return regmap_update_bits(qp->regmap,
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qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
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2021-09-03 23:24:14 +00:00
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mask, val);
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}
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static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw)
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2020-12-04 07:53:41 +00:00
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{
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struct qcom_icc_provider *qp;
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struct qcom_icc_node *qn;
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struct icc_provider *provider;
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2021-09-03 23:24:14 +00:00
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u32 mode = NOC_QOS_MODE_BYPASS;
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u32 val = 0;
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int i, rc = 0;
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2020-12-04 07:53:41 +00:00
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qn = src->data;
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provider = src->provider;
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qp = to_qcom_provider(provider);
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2021-12-06 07:58:03 +00:00
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if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID)
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2021-09-03 23:24:14 +00:00
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mode = qn->qos.qos_mode;
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2020-12-04 07:53:41 +00:00
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2021-09-03 23:24:14 +00:00
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/* QoS Priority: The QoS Health parameters are getting considered
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* only if we are NOT in Bypass Mode.
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*/
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if (mode != NOC_QOS_MODE_BYPASS) {
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for (i = 3; i >= 0; i--) {
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2021-09-03 23:24:15 +00:00
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rc = qcom_icc_bimc_set_qos_health(qp,
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2021-09-03 23:24:14 +00:00
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&qn->qos, i);
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if (rc)
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return rc;
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}
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/* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */
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val = 1;
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}
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2021-09-03 23:24:15 +00:00
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return regmap_update_bits(qp->regmap,
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qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port),
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2021-09-03 23:24:14 +00:00
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M_BKE_EN_EN_BMASK, val);
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}
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2021-09-03 23:24:15 +00:00
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static int qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp,
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2021-09-03 23:24:14 +00:00
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struct qcom_icc_qos *qos)
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{
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u32 val;
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int rc;
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/* Must be updated one at a time, P1 first, P0 last */
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val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
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2021-09-03 23:24:15 +00:00
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rc = regmap_update_bits(qp->regmap,
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qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
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2021-09-03 23:24:14 +00:00
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NOC_QOS_PRIORITY_P1_MASK, val);
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if (rc)
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return rc;
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2021-09-03 23:24:15 +00:00
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return regmap_update_bits(qp->regmap,
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qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
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2021-09-03 23:24:14 +00:00
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NOC_QOS_PRIORITY_P0_MASK, qos->prio_level);
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}
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static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
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{
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struct qcom_icc_provider *qp;
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struct qcom_icc_node *qn;
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struct icc_provider *provider;
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u32 mode = NOC_QOS_MODE_BYPASS;
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int rc = 0;
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qn = src->data;
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provider = src->provider;
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qp = to_qcom_provider(provider);
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if (qn->qos.qos_port < 0) {
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dev_dbg(src->provider->dev,
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"NoC QoS: Skipping %s: vote aggregated on parent.\n",
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qn->name);
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return 0;
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}
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2021-12-06 07:58:03 +00:00
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if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID)
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2021-09-03 23:24:14 +00:00
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mode = qn->qos.qos_mode;
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if (mode == NOC_QOS_MODE_FIXED) {
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dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n",
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qn->name);
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2021-09-03 23:24:15 +00:00
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rc = qcom_icc_noc_set_qos_priority(qp, &qn->qos);
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2021-09-03 23:24:14 +00:00
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if (rc)
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return rc;
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} else if (mode == NOC_QOS_MODE_BYPASS) {
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dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n",
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qn->name);
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}
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2020-12-04 07:53:41 +00:00
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2021-09-03 23:24:14 +00:00
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return regmap_update_bits(qp->regmap,
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2021-09-03 23:24:15 +00:00
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qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
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2021-09-03 23:24:14 +00:00
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NOC_QOS_MODEn_MASK, mode);
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}
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static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
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{
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struct qcom_icc_provider *qp = to_qcom_provider(node->provider);
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struct qcom_icc_node *qn = node->data;
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dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name);
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2021-12-15 00:23:21 +00:00
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switch (qp->type) {
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case QCOM_ICC_BIMC:
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2021-09-03 23:24:14 +00:00
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return qcom_icc_set_bimc_qos(node, sum_bw);
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2021-12-15 00:23:21 +00:00
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case QCOM_ICC_QNOC:
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return qcom_icc_set_qnoc_qos(node, sum_bw);
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default:
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return qcom_icc_set_noc_qos(node, sum_bw);
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}
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2021-09-03 23:24:14 +00:00
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}
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static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
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{
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int ret = 0;
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if (mas_rpm_id != -1) {
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2020-12-04 07:53:41 +00:00
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ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
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RPM_BUS_MASTER_REQ,
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2021-09-03 23:24:14 +00:00
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mas_rpm_id,
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2020-12-04 07:53:41 +00:00
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sum_bw);
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if (ret) {
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pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
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2021-09-03 23:24:14 +00:00
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mas_rpm_id, ret);
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2020-12-04 07:53:41 +00:00
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return ret;
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}
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}
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2021-09-03 23:24:14 +00:00
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if (slv_rpm_id != -1) {
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2020-12-04 07:53:41 +00:00
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ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
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RPM_BUS_SLAVE_REQ,
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2021-09-03 23:24:14 +00:00
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slv_rpm_id,
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2020-12-04 07:53:41 +00:00
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sum_bw);
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if (ret) {
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2021-03-08 13:13:40 +00:00
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pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
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2021-09-03 23:24:14 +00:00
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slv_rpm_id, ret);
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2020-12-04 07:53:41 +00:00
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return ret;
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}
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}
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2021-09-03 23:24:14 +00:00
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return ret;
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}
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2022-07-07 09:38:23 +00:00
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static int __qcom_icc_set(struct icc_node *n, struct qcom_icc_node *qn,
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u64 sum_bw)
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{
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int ret;
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if (!qn->qos.ap_owned) {
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/* send bandwidth request message to the RPM processor */
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ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw);
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if (ret)
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return ret;
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} else if (qn->qos.qos_mode != -1) {
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/* set bandwidth directly from the AP */
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ret = qcom_icc_qos_set(n, sum_bw);
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if (ret)
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return ret;
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}
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return 0;
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}
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2022-07-12 01:59:28 +00:00
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/**
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* qcom_icc_pre_bw_aggregate - cleans up values before re-aggregate requests
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* @node: icc node to operate on
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*/
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static void qcom_icc_pre_bw_aggregate(struct icc_node *node)
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{
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struct qcom_icc_node *qn;
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size_t i;
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qn = node->data;
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for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
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qn->sum_avg[i] = 0;
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qn->max_peak[i] = 0;
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}
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}
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/**
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* qcom_icc_bw_aggregate - aggregate bw for buckets indicated by tag
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* @node: node to aggregate
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* @tag: tag to indicate which buckets to aggregate
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* @avg_bw: new bw to sum aggregate
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* @peak_bw: new bw to max aggregate
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* @agg_avg: existing aggregate avg bw val
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* @agg_peak: existing aggregate peak bw val
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*/
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static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
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u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
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{
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size_t i;
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struct qcom_icc_node *qn;
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qn = node->data;
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if (!tag)
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tag = QCOM_ICC_TAG_ALWAYS;
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for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
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if (tag & BIT(i)) {
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qn->sum_avg[i] += avg_bw;
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qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw);
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}
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}
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*agg_avg += avg_bw;
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*agg_peak = max_t(u32, *agg_peak, peak_bw);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-07-12 01:59:29 +00:00
|
|
|
/**
|
|
|
|
* qcom_icc_bus_aggregate - aggregate bandwidth by traversing all nodes
|
|
|
|
* @provider: generic interconnect provider
|
|
|
|
* @agg_avg: an array for aggregated average bandwidth of buckets
|
|
|
|
* @agg_peak: an array for aggregated peak bandwidth of buckets
|
|
|
|
* @max_agg_avg: pointer to max value of aggregated average bandwidth
|
|
|
|
*/
|
|
|
|
static void qcom_icc_bus_aggregate(struct icc_provider *provider,
|
|
|
|
u64 *agg_avg, u64 *agg_peak,
|
|
|
|
u64 *max_agg_avg)
|
|
|
|
{
|
|
|
|
struct icc_node *node;
|
|
|
|
struct qcom_icc_node *qn;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Initialise aggregate values */
|
|
|
|
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
|
|
|
|
agg_avg[i] = 0;
|
|
|
|
agg_peak[i] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
*max_agg_avg = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Iterate nodes on the interconnect and aggregate bandwidth
|
|
|
|
* requests for every bucket.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(node, &provider->nodes, node_list) {
|
|
|
|
qn = node->data;
|
|
|
|
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
|
|
|
|
agg_avg[i] += qn->sum_avg[i];
|
|
|
|
agg_peak[i] = max_t(u64, agg_peak[i], qn->max_peak[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Find maximum values across all buckets */
|
|
|
|
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++)
|
|
|
|
*max_agg_avg = max_t(u64, *max_agg_avg, agg_avg[i]);
|
|
|
|
}
|
|
|
|
|
2021-09-03 23:24:14 +00:00
|
|
|
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
|
|
|
{
|
|
|
|
struct qcom_icc_provider *qp;
|
2022-07-07 09:38:23 +00:00
|
|
|
struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL;
|
2021-09-03 23:24:14 +00:00
|
|
|
struct icc_provider *provider;
|
|
|
|
u64 sum_bw;
|
|
|
|
u64 rate;
|
2022-07-12 01:59:29 +00:00
|
|
|
u64 agg_avg[QCOM_ICC_NUM_BUCKETS], agg_peak[QCOM_ICC_NUM_BUCKETS];
|
|
|
|
u64 max_agg_avg;
|
2021-09-03 23:24:14 +00:00
|
|
|
int ret, i;
|
2022-07-12 01:59:29 +00:00
|
|
|
int bucket;
|
2021-09-03 23:24:14 +00:00
|
|
|
|
2022-07-07 09:38:23 +00:00
|
|
|
src_qn = src->data;
|
|
|
|
if (dst)
|
|
|
|
dst_qn = dst->data;
|
2021-09-03 23:24:14 +00:00
|
|
|
provider = src->provider;
|
|
|
|
qp = to_qcom_provider(provider);
|
|
|
|
|
2022-07-12 01:59:29 +00:00
|
|
|
qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg);
|
2021-09-03 23:24:14 +00:00
|
|
|
|
2022-07-12 01:59:29 +00:00
|
|
|
sum_bw = icc_units_to_bps(max_agg_avg);
|
2021-09-03 23:24:14 +00:00
|
|
|
|
2022-07-07 09:38:23 +00:00
|
|
|
ret = __qcom_icc_set(src, src_qn, sum_bw);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
if (dst_qn) {
|
|
|
|
ret = __qcom_icc_set(dst, dst_qn, sum_bw);
|
2021-09-03 23:24:14 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-12-04 07:53:41 +00:00
|
|
|
for (i = 0; i < qp->num_clks; i++) {
|
2022-07-12 01:59:29 +00:00
|
|
|
/*
|
|
|
|
* Use WAKE bucket for active clock, otherwise, use SLEEP bucket
|
|
|
|
* for other clocks. If a platform doesn't set interconnect
|
|
|
|
* path tags, by default use sleep bucket for all clocks.
|
|
|
|
*
|
|
|
|
* Note, AMC bucket is not supported yet.
|
|
|
|
*/
|
|
|
|
if (!strcmp(qp->bus_clks[i].id, "bus_a"))
|
|
|
|
bucket = QCOM_ICC_BUCKET_WAKE;
|
|
|
|
else
|
|
|
|
bucket = QCOM_ICC_BUCKET_SLEEP;
|
|
|
|
|
|
|
|
rate = icc_units_to_bps(max(agg_avg[bucket], agg_peak[bucket]));
|
|
|
|
do_div(rate, src_qn->buswidth);
|
|
|
|
rate = min_t(u64, rate, LONG_MAX);
|
|
|
|
|
2022-05-04 07:46:18 +00:00
|
|
|
if (qp->bus_clk_rate[i] == rate)
|
|
|
|
continue;
|
|
|
|
|
2020-12-04 07:53:41 +00:00
|
|
|
ret = clk_set_rate(qp->bus_clks[i].clk, rate);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("%s clk_set_rate error: %d\n",
|
|
|
|
qp->bus_clks[i].id, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
2022-05-04 07:46:18 +00:00
|
|
|
qp->bus_clk_rate[i] = rate;
|
2020-12-04 07:53:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-09-03 23:24:11 +00:00
|
|
|
static const char * const bus_clocks[] = {
|
|
|
|
"bus", "bus_a",
|
|
|
|
};
|
|
|
|
|
|
|
|
int qnoc_probe(struct platform_device *pdev)
|
2020-12-04 07:53:41 +00:00
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
const struct qcom_icc_desc *desc;
|
|
|
|
struct icc_onecell_data *data;
|
|
|
|
struct icc_provider *provider;
|
2022-04-12 10:26:22 +00:00
|
|
|
struct qcom_icc_node * const *qnodes;
|
2020-12-04 07:53:41 +00:00
|
|
|
struct qcom_icc_provider *qp;
|
|
|
|
struct icc_node *node;
|
|
|
|
size_t num_nodes, i;
|
2021-09-03 23:24:11 +00:00
|
|
|
const char * const *cds;
|
|
|
|
int cd_num;
|
2020-12-04 07:53:41 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* wait for the RPM proxy */
|
|
|
|
if (!qcom_icc_rpm_smd_available())
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
|
|
|
desc = of_device_get_match_data(dev);
|
|
|
|
if (!desc)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
qnodes = desc->nodes;
|
|
|
|
num_nodes = desc->num_nodes;
|
|
|
|
|
2021-09-03 23:24:14 +00:00
|
|
|
if (desc->num_clocks) {
|
|
|
|
cds = desc->clocks;
|
|
|
|
cd_num = desc->num_clocks;
|
|
|
|
} else {
|
|
|
|
cds = bus_clocks;
|
|
|
|
cd_num = ARRAY_SIZE(bus_clocks);
|
|
|
|
}
|
2021-09-03 23:24:11 +00:00
|
|
|
|
|
|
|
qp = devm_kzalloc(dev, struct_size(qp, bus_clks, cd_num), GFP_KERNEL);
|
2020-12-04 07:53:41 +00:00
|
|
|
if (!qp)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2022-05-04 07:46:18 +00:00
|
|
|
qp->bus_clk_rate = devm_kcalloc(dev, cd_num, sizeof(*qp->bus_clk_rate),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!qp->bus_clk_rate)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2020-12-04 07:53:41 +00:00
|
|
|
data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!data)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2021-09-03 23:24:11 +00:00
|
|
|
for (i = 0; i < cd_num; i++)
|
|
|
|
qp->bus_clks[i].id = cds[i];
|
2020-12-04 07:53:41 +00:00
|
|
|
qp->num_clks = cd_num;
|
2021-09-03 23:24:11 +00:00
|
|
|
|
2021-12-15 00:23:20 +00:00
|
|
|
qp->type = desc->type;
|
2021-09-03 23:24:15 +00:00
|
|
|
qp->qos_offset = desc->qos_offset;
|
2021-09-03 23:24:14 +00:00
|
|
|
|
|
|
|
if (desc->regmap_cfg) {
|
|
|
|
struct resource *res;
|
|
|
|
void __iomem *mmio;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2021-12-15 00:23:22 +00:00
|
|
|
if (!res) {
|
|
|
|
/* Try parent's regmap */
|
|
|
|
qp->regmap = dev_get_regmap(dev->parent, NULL);
|
|
|
|
if (qp->regmap)
|
|
|
|
goto regmap_done;
|
2021-09-03 23:24:14 +00:00
|
|
|
return -ENODEV;
|
2021-12-15 00:23:22 +00:00
|
|
|
}
|
2021-09-03 23:24:14 +00:00
|
|
|
|
|
|
|
mmio = devm_ioremap_resource(dev, res);
|
2022-09-24 01:50:43 +00:00
|
|
|
if (IS_ERR(mmio))
|
2021-09-03 23:24:14 +00:00
|
|
|
return PTR_ERR(mmio);
|
|
|
|
|
|
|
|
qp->regmap = devm_regmap_init_mmio(dev, mmio, desc->regmap_cfg);
|
|
|
|
if (IS_ERR(qp->regmap)) {
|
|
|
|
dev_err(dev, "Cannot regmap interconnect bus resource\n");
|
|
|
|
return PTR_ERR(qp->regmap);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-15 00:23:22 +00:00
|
|
|
regmap_done:
|
2020-12-04 07:53:41 +00:00
|
|
|
ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-10-21 13:24:42 +00:00
|
|
|
if (desc->has_bus_pd) {
|
|
|
|
ret = dev_pm_domain_attach(dev, true);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-12-04 07:53:41 +00:00
|
|
|
provider = &qp->provider;
|
|
|
|
INIT_LIST_HEAD(&provider->nodes);
|
|
|
|
provider->dev = dev;
|
|
|
|
provider->set = qcom_icc_set;
|
2022-07-12 01:59:28 +00:00
|
|
|
provider->pre_aggregate = qcom_icc_pre_bw_aggregate;
|
|
|
|
provider->aggregate = qcom_icc_bw_aggregate;
|
2022-07-12 01:59:27 +00:00
|
|
|
provider->xlate_extended = qcom_icc_xlate_extended;
|
2020-12-04 07:53:41 +00:00
|
|
|
provider->data = data;
|
|
|
|
|
|
|
|
ret = icc_provider_add(provider);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "error adding interconnect provider: %d\n", ret);
|
|
|
|
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < num_nodes; i++) {
|
|
|
|
size_t j;
|
|
|
|
|
|
|
|
node = icc_node_create(qnodes[i]->id);
|
|
|
|
if (IS_ERR(node)) {
|
|
|
|
ret = PTR_ERR(node);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
node->name = qnodes[i]->name;
|
|
|
|
node->data = qnodes[i];
|
|
|
|
icc_node_add(node, provider);
|
|
|
|
|
|
|
|
for (j = 0; j < qnodes[i]->num_links; j++)
|
|
|
|
icc_link_create(node, qnodes[i]->links[j]);
|
|
|
|
|
|
|
|
data->nodes[i] = node;
|
|
|
|
}
|
|
|
|
data->num_nodes = num_nodes;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, qp);
|
|
|
|
|
2021-12-15 00:23:22 +00:00
|
|
|
/* Populate child NoC devices if any */
|
|
|
|
if (of_get_child_count(dev->of_node) > 0)
|
|
|
|
return of_platform_populate(dev->of_node, NULL, NULL, dev);
|
|
|
|
|
2020-12-04 07:53:41 +00:00
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
icc_nodes_remove(provider);
|
|
|
|
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
|
|
|
icc_provider_del(provider);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(qnoc_probe);
|
|
|
|
|
|
|
|
int qnoc_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
icc_nodes_remove(&qp->provider);
|
|
|
|
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
|
2022-07-18 12:14:03 +00:00
|
|
|
icc_provider_del(&qp->provider);
|
|
|
|
|
|
|
|
return 0;
|
2020-12-04 07:53:41 +00:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(qnoc_remove);
|