2019-05-19 12:07:45 +00:00
|
|
|
# SPDX-License-Identifier: GPL-2.0-only
|
2015-09-09 13:29:22 +00:00
|
|
|
if ARCH_TEGRA
|
|
|
|
|
|
|
|
# 32-bit ARM SoCs
|
|
|
|
if ARM
|
|
|
|
|
|
|
|
config ARCH_TEGRA_2x_SOC
|
|
|
|
bool "Enable support for Tegra20 family"
|
|
|
|
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
|
|
|
|
select ARM_ERRATA_720789
|
|
|
|
select ARM_ERRATA_754327 if SMP
|
|
|
|
select ARM_ERRATA_764369 if SMP
|
|
|
|
select PINCTRL_TEGRA20
|
|
|
|
select PL310_ERRATA_727915 if CACHE_L2X0
|
|
|
|
select PL310_ERRATA_769419 if CACHE_L2X0
|
2017-03-28 12:42:54 +00:00
|
|
|
select SOC_TEGRA_FLOWCTRL
|
2017-02-23 17:11:57 +00:00
|
|
|
select SOC_TEGRA_PMC
|
2021-07-21 23:26:16 +00:00
|
|
|
select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR
|
2015-09-09 13:29:22 +00:00
|
|
|
select TEGRA_TIMER
|
|
|
|
help
|
|
|
|
Support for NVIDIA Tegra AP20 and T20 processors, based on the
|
|
|
|
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
|
|
|
|
|
|
|
config ARCH_TEGRA_3x_SOC
|
|
|
|
bool "Enable support for Tegra30 family"
|
|
|
|
select ARM_ERRATA_754322
|
|
|
|
select ARM_ERRATA_764369 if SMP
|
|
|
|
select PINCTRL_TEGRA30
|
|
|
|
select PL310_ERRATA_769419 if CACHE_L2X0
|
2017-03-28 12:42:54 +00:00
|
|
|
select SOC_TEGRA_FLOWCTRL
|
2017-02-23 17:11:57 +00:00
|
|
|
select SOC_TEGRA_PMC
|
2021-07-21 23:26:16 +00:00
|
|
|
select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR
|
2015-09-09 13:29:22 +00:00
|
|
|
select TEGRA_TIMER
|
|
|
|
help
|
|
|
|
Support for NVIDIA Tegra T30 processor family, based on the
|
|
|
|
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
|
|
|
|
|
|
|
config ARCH_TEGRA_114_SOC
|
|
|
|
bool "Enable support for Tegra114 family"
|
|
|
|
select ARM_ERRATA_798181 if SMP
|
|
|
|
select HAVE_ARM_ARCH_TIMER
|
|
|
|
select PINCTRL_TEGRA114
|
2017-03-28 12:42:54 +00:00
|
|
|
select SOC_TEGRA_FLOWCTRL
|
2017-02-23 17:11:57 +00:00
|
|
|
select SOC_TEGRA_PMC
|
2015-09-09 13:29:22 +00:00
|
|
|
select TEGRA_TIMER
|
|
|
|
help
|
|
|
|
Support for NVIDIA Tegra T114 processor family, based on the
|
|
|
|
ARM CortexA15MP CPU
|
|
|
|
|
|
|
|
config ARCH_TEGRA_124_SOC
|
|
|
|
bool "Enable support for Tegra124 family"
|
|
|
|
select HAVE_ARM_ARCH_TIMER
|
|
|
|
select PINCTRL_TEGRA124
|
2017-03-28 12:42:54 +00:00
|
|
|
select SOC_TEGRA_FLOWCTRL
|
2017-02-23 17:11:57 +00:00
|
|
|
select SOC_TEGRA_PMC
|
2015-09-09 13:29:22 +00:00
|
|
|
select TEGRA_TIMER
|
|
|
|
help
|
|
|
|
Support for NVIDIA Tegra T124 processor family, based on the
|
|
|
|
ARM CortexA15MP CPU
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
# 64-bit ARM SoCs
|
|
|
|
if ARM64
|
|
|
|
|
|
|
|
config ARCH_TEGRA_132_SOC
|
|
|
|
bool "NVIDIA Tegra132 SoC"
|
|
|
|
select PINCTRL_TEGRA124
|
2017-03-28 12:42:58 +00:00
|
|
|
select SOC_TEGRA_FLOWCTRL
|
2017-02-23 17:11:57 +00:00
|
|
|
select SOC_TEGRA_PMC
|
2015-09-09 13:29:22 +00:00
|
|
|
help
|
|
|
|
Enable support for NVIDIA Tegra132 SoC, based on the Denver
|
|
|
|
ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
|
|
|
|
but contains an NVIDIA Denver CPU complex in place of
|
|
|
|
Tegra124's "4+1" Cortex-A15 CPU complex.
|
|
|
|
|
soc/tegra: Add Tegra210 support
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU using the Maxwell architecture with support for DX11, SM4, OpenGL
4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware
accelerated en- and decoding of various video standards including
H.265, H.264 and VP8 at 4K resolutions and up to 60 fps.
Besides the multimedia features it also comes with a variety of I/O
controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.
Add a Kconfig option for Tegra210 to allow SoC-specific support to be
enabled for this new generation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-16 06:15:55 +00:00
|
|
|
config ARCH_TEGRA_210_SOC
|
|
|
|
bool "NVIDIA Tegra210 SoC"
|
|
|
|
select PINCTRL_TEGRA210
|
2017-03-28 12:42:58 +00:00
|
|
|
select SOC_TEGRA_FLOWCTRL
|
2017-02-23 17:11:57 +00:00
|
|
|
select SOC_TEGRA_PMC
|
2019-02-21 07:21:45 +00:00
|
|
|
select TEGRA_TIMER
|
soc/tegra: Add Tegra210 support
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU using the Maxwell architecture with support for DX11, SM4, OpenGL
4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware
accelerated en- and decoding of various video standards including
H.265, H.264 and VP8 at 4K resolutions and up to 60 fps.
Besides the multimedia features it also comes with a variety of I/O
controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.
Add a Kconfig option for Tegra210 to allow SoC-specific support to be
enabled for this new generation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-16 06:15:55 +00:00
|
|
|
help
|
|
|
|
Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
|
|
|
|
the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
|
|
|
|
cores in a switched configuration. It features a GPU of the Maxwell
|
|
|
|
architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
|
|
|
|
and providing 256 CUDA cores. It supports hardware-accelerated en-
|
|
|
|
and decoding of various video standards including H.265, H.264 and
|
|
|
|
VP8 at 4K resolution and up to 60 fps.
|
|
|
|
|
|
|
|
Besides the multimedia features it also comes with a variety of I/O
|
|
|
|
controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
|
|
|
|
name only a few.
|
|
|
|
|
2016-07-05 09:04:27 +00:00
|
|
|
config ARCH_TEGRA_186_SOC
|
|
|
|
bool "NVIDIA Tegra186 SoC"
|
2022-12-15 16:53:21 +00:00
|
|
|
depends on !CPU_BIG_ENDIAN
|
2016-07-05 09:04:27 +00:00
|
|
|
select MAILBOX
|
|
|
|
select TEGRA_BPMP
|
|
|
|
select TEGRA_HSP_MBOX
|
|
|
|
select TEGRA_IVC
|
2017-08-30 10:42:34 +00:00
|
|
|
select SOC_TEGRA_PMC
|
2016-07-05 09:04:27 +00:00
|
|
|
help
|
|
|
|
Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
|
|
|
|
combination of Denver and Cortex-A57 CPU cores and a GPU based on
|
|
|
|
the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
|
|
|
|
used for audio processing, hardware video encoders/decoders with
|
|
|
|
multi-format support, ISP for image capture processing and BPMP for
|
|
|
|
power management.
|
|
|
|
|
2018-02-20 11:58:07 +00:00
|
|
|
config ARCH_TEGRA_194_SOC
|
|
|
|
bool "NVIDIA Tegra194 SoC"
|
2022-12-15 16:53:21 +00:00
|
|
|
depends on !CPU_BIG_ENDIAN
|
2018-02-20 11:58:07 +00:00
|
|
|
select MAILBOX
|
2019-05-16 11:53:14 +00:00
|
|
|
select PINCTRL_TEGRA194
|
2018-02-20 11:58:07 +00:00
|
|
|
select TEGRA_BPMP
|
|
|
|
select TEGRA_HSP_MBOX
|
|
|
|
select TEGRA_IVC
|
|
|
|
select SOC_TEGRA_PMC
|
|
|
|
help
|
|
|
|
Enable support for the NVIDIA Tegra194 SoC.
|
|
|
|
|
2020-09-17 10:07:52 +00:00
|
|
|
config ARCH_TEGRA_234_SOC
|
|
|
|
bool "NVIDIA Tegra234 SoC"
|
2022-12-15 16:53:21 +00:00
|
|
|
depends on !CPU_BIG_ENDIAN
|
2020-09-17 10:07:52 +00:00
|
|
|
select MAILBOX
|
|
|
|
select TEGRA_BPMP
|
|
|
|
select TEGRA_HSP_MBOX
|
|
|
|
select TEGRA_IVC
|
|
|
|
select SOC_TEGRA_PMC
|
|
|
|
help
|
|
|
|
Enable support for the NVIDIA Tegra234 SoC.
|
|
|
|
|
2015-09-09 13:29:22 +00:00
|
|
|
endif
|
|
|
|
endif
|
2017-02-23 17:11:57 +00:00
|
|
|
|
2017-08-17 14:42:17 +00:00
|
|
|
config SOC_TEGRA_FUSE
|
|
|
|
def_bool y
|
|
|
|
depends on ARCH_TEGRA
|
|
|
|
select SOC_BUS
|
|
|
|
|
2017-03-28 12:42:54 +00:00
|
|
|
config SOC_TEGRA_FLOWCTRL
|
|
|
|
bool
|
|
|
|
|
2017-02-23 17:11:57 +00:00
|
|
|
config SOC_TEGRA_PMC
|
|
|
|
bool
|
2020-03-18 15:25:08 +00:00
|
|
|
select GENERIC_PINCONF
|
2022-10-02 17:54:25 +00:00
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
2021-06-01 02:31:17 +00:00
|
|
|
select PM_OPP
|
|
|
|
select PM_GENERIC_DOMAINS
|
2022-05-04 09:08:14 +00:00
|
|
|
select REGMAP
|
2017-02-23 17:11:57 +00:00
|
|
|
|
2017-03-29 16:34:52 +00:00
|
|
|
config SOC_TEGRA_POWERGATE_BPMP
|
|
|
|
def_bool y
|
|
|
|
depends on PM_GENERIC_DOMAINS
|
|
|
|
depends on TEGRA_BPMP
|
2019-07-25 15:18:31 +00:00
|
|
|
|
|
|
|
config SOC_TEGRA20_VOLTAGE_COUPLER
|
|
|
|
bool "Voltage scaling support for Tegra20 SoCs"
|
|
|
|
depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
|
2021-07-21 23:26:16 +00:00
|
|
|
depends on REGULATOR
|
2019-07-25 15:18:32 +00:00
|
|
|
|
|
|
|
config SOC_TEGRA30_VOLTAGE_COUPLER
|
|
|
|
bool "Voltage scaling support for Tegra30 SoCs"
|
|
|
|
depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
|
2021-07-21 23:26:16 +00:00
|
|
|
depends on REGULATOR
|
2022-05-11 20:16:47 +00:00
|
|
|
|
|
|
|
config SOC_TEGRA_CBB
|
|
|
|
tristate "Tegra driver to handle error from CBB"
|
2022-05-11 20:16:50 +00:00
|
|
|
depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
|
2022-05-11 20:16:47 +00:00
|
|
|
default y
|
|
|
|
help
|
|
|
|
Support for handling error from Tegra Control Backbone(CBB).
|
|
|
|
This driver handles the errors from CBB and prints debug
|
|
|
|
information about the failed transactions.
|