2009-06-04 07:34:49 +00:00
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/*
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* Intel Langwell USB Device Controller driver
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* Copyright (C) 2008-2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/usb/langwell_udc.h>
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#include <linux/usb/langwell_otg.h>
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/*-------------------------------------------------------------------------*/
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/* driver data structures and utilities */
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/*
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* dTD: Device Endpoint Transfer Descriptor
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* describe to the device controller the location and quantity of
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* data to be send/received for given transfer
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*/
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struct langwell_dtd {
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u32 dtd_next;
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/* bits 31:5, next transfer element pointer */
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#define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
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#define DTD_NEXT_MASK (0x7ffffff << 5)
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/* terminate */
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#define DTD_TERM BIT(0)
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/* bits 7:0, execution back states */
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u32 dtd_status:8;
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#define DTD_STATUS(d) (((d)>>0)&0xff)
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#define DTD_STS_ACTIVE BIT(7) /* active */
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#define DTD_STS_HALTED BIT(6) /* halted */
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#define DTD_STS_DBE BIT(5) /* data buffer error */
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#define DTD_STS_TRE BIT(3) /* transaction error */
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/* bits 9:8 */
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u32 dtd_res0:2;
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/* bits 11:10, multipier override */
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u32 dtd_multo:2;
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#define DTD_MULTO (BIT(11) | BIT(10))
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/* bits 14:12 */
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u32 dtd_res1:3;
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/* bit 15, interrupt on complete */
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u32 dtd_ioc:1;
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#define DTD_IOC BIT(15)
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/* bits 30:16, total bytes */
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u32 dtd_total:15;
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#define DTD_TOTAL(d) (((d)>>16)&0x7fff)
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#define DTD_MAX_TRANSFER_LENGTH 0x4000
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/* bit 31 */
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u32 dtd_res2:1;
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/* dTD buffer pointer page 0 to 4 */
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u32 dtd_buf[5];
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#define DTD_OFFSET_MASK 0xfff
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/* bits 31:12, buffer pointer */
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#define DTD_BUFFER(d) (((d)>>12)&0x3ff)
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/* bits 11:0, current offset */
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#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
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/* bits 10:0, frame number */
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#define DTD_FRAME(d) (((d)>>0)&0x7ff)
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/* driver-private parts */
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/* dtd dma address */
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dma_addr_t dtd_dma;
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/* next dtd virtual address */
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struct langwell_dtd *next_dtd_virt;
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};
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/*
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* dQH: Device Endpoint Queue Head
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* describe where all transfers are managed
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* 48-byte data structure, aligned on 64-byte boundary
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*
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* These are associated with dTD structure
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*/
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struct langwell_dqh {
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/* endpoint capabilities and characteristics */
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u32 dqh_res0:15; /* bits 14:0 */
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u32 dqh_ios:1; /* bit 15, interrupt on setup */
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#define DQH_IOS BIT(15)
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u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
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#define DQH_MPL (0x7ff << 16)
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u32 dqh_res1:2; /* bits 28:27 */
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u32 dqh_zlt:1; /* bit 29, zero length termination */
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#define DQH_ZLT BIT(29)
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u32 dqh_mult:2; /* bits 31:30 */
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#define DQH_MULT (BIT(30) | BIT(31))
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/* current dTD pointer */
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u32 dqh_current; /* locate the transfer in progress */
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#define DQH_C_DTD(e) \
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(((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
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/* transfer overlay, hardware parts of a struct langwell_dtd */
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u32 dtd_next;
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u32 dtd_status:8; /* bits 7:0, execution back states */
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u32 dtd_res0:2; /* bits 9:8 */
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u32 dtd_multo:2; /* bits 11:10, multipier override */
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u32 dtd_res1:3; /* bits 14:12 */
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u32 dtd_ioc:1; /* bit 15, interrupt on complete */
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u32 dtd_total:15; /* bits 30:16, total bytes */
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u32 dtd_res2:1; /* bit 31 */
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u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
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u32 dqh_res2;
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struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
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} __attribute__ ((aligned(64)));
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/* endpoint data structure */
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struct langwell_ep {
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struct usb_ep ep;
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dma_addr_t dma;
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struct langwell_udc *dev;
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unsigned long irqs;
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struct list_head queue;
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struct langwell_dqh *dqh;
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const struct usb_endpoint_descriptor *desc;
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char name[14];
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unsigned stopped:1,
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ep_type:2,
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ep_num:8;
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};
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/* request data structure */
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struct langwell_request {
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struct usb_request req;
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struct langwell_dtd *dtd, *head, *tail;
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struct langwell_ep *ep;
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dma_addr_t dtd_dma;
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struct list_head queue;
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unsigned dtd_count;
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unsigned mapped:1;
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};
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/* ep0 transfer state */
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enum ep0_state {
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WAIT_FOR_SETUP,
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DATA_STATE_XMIT,
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DATA_STATE_NEED_ZLP,
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WAIT_FOR_OUT_STATUS,
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DATA_STATE_RECV,
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};
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/* device suspend state */
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enum lpm_state {
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LPM_L0, /* on */
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LPM_L1, /* LPM L1 sleep */
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LPM_L2, /* suspend */
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LPM_L3, /* off */
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};
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/* device data structure */
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struct langwell_udc {
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/* each pci device provides one gadget, several endpoints */
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struct usb_gadget gadget;
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spinlock_t lock; /* device lock */
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struct langwell_ep *ep;
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struct usb_gadget_driver *driver;
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struct otg_transceiver *transceiver;
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u8 dev_addr;
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u32 usb_state;
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u32 resume_state;
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u32 bus_reset;
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enum lpm_state lpm_state;
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enum ep0_state ep0_state;
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u32 ep0_dir;
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u16 dciversion;
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unsigned ep_max;
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unsigned devcap:1,
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enabled:1,
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region:1,
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got_irq:1,
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powered:1,
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remote_wakeup:1,
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rate:1,
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is_reset:1,
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softconnected:1,
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vbus_active:1,
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suspended:1,
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stopped:1,
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2010-08-05 13:18:29 +00:00
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lpm:1, /* LPM capability */
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has_sram:1, /* SRAM caching */
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got_sram:1;
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2009-06-04 07:34:49 +00:00
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/* pci state used to access those endpoints */
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struct pci_dev *pdev;
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/* Langwell otg transceiver */
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struct langwell_otg *lotg;
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/* control registers */
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struct langwell_cap_regs __iomem *cap_regs;
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struct langwell_op_regs __iomem *op_regs;
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struct usb_ctrlrequest local_setup_buff;
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struct langwell_dqh *ep_dqh;
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size_t ep_dqh_size;
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dma_addr_t ep_dqh_dma;
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/* ep0 status request */
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struct langwell_request *status_req;
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/* dma pool */
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struct dma_pool *dtd_pool;
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/* make sure release() is done */
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struct completion *done;
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2010-08-05 13:18:21 +00:00
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2010-08-05 13:18:29 +00:00
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/* for private SRAM caching */
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unsigned int sram_addr;
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unsigned int sram_size;
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2010-08-05 13:18:21 +00:00
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/* device status data for get_status request */
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u16 dev_status;
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2009-06-04 07:34:49 +00:00
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};
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