2006-03-08 07:53:24 +00:00
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/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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2013-01-22 10:26:32 +00:00
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* Copyright (C) 2013, Intel Corporation
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2006-03-08 07:53:24 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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2013-04-08 10:19:33 +00:00
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#include <linux/err.h>
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2006-03-08 07:53:24 +00:00
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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2010-11-23 01:12:15 +00:00
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#include <linux/spi/pxa2xx_spi.h>
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2006-03-08 07:53:24 +00:00
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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2009-04-07 02:00:54 +00:00
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#include <linux/gpio.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2013-01-22 10:26:27 +00:00
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#include <linux/clk.h>
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2013-01-22 10:26:30 +00:00
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#include <linux/pm_runtime.h>
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2013-01-22 10:26:33 +00:00
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#include <linux/acpi.h>
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2006-03-08 07:53:24 +00:00
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/delay.h>
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2013-01-22 10:26:28 +00:00
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#include "spi-pxa2xx.h"
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2006-03-08 07:53:24 +00:00
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MODULE_AUTHOR("Stephen Street");
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2007-12-10 23:49:25 +00:00
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MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
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2006-03-08 07:53:24 +00:00
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MODULE_LICENSE("GPL");
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2008-04-11 04:29:20 +00:00
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MODULE_ALIAS("platform:pxa2xx-spi");
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2006-03-08 07:53:24 +00:00
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#define MAX_BUSES 3
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2008-10-16 05:02:43 +00:00
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#define TIMOUT_DFLT 1000
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2008-02-23 23:23:40 +00:00
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/*
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* for testing SSCR1 changes that require SSP restart, basically
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* everything except the service and interrupt enables, the pxa270 developer
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* manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
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* list, but the PXA255 dev man says all bits without really meaning the
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* service and interrupt enables
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*/
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#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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2006-12-10 10:18:54 +00:00
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| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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2008-02-23 23:23:40 +00:00
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| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
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| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
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| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
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| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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2006-12-10 10:18:54 +00:00
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2013-01-22 10:26:32 +00:00
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#define LPSS_RX_THRESH_DFLT 64
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#define LPSS_TX_LOTHRESH_DFLT 160
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#define LPSS_TX_HITHRESH_DFLT 224
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/* Offset from drv_data->lpss_base */
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2013-07-03 10:25:06 +00:00
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#define GENERAL_REG 0x08
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#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
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2013-03-05 10:05:17 +00:00
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#define SSP_REG 0x0c
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2013-01-22 10:26:32 +00:00
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#define SPI_CS_CONTROL 0x18
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#define SPI_CS_CONTROL_SW_MODE BIT(0)
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#define SPI_CS_CONTROL_CS_HIGH BIT(1)
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static bool is_lpss_ssp(const struct driver_data *drv_data)
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{
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return drv_data->ssp_type == LPSS_SSP;
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}
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/*
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* Read and write LPSS SSP private registers. Caller must first check that
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* is_lpss_ssp() returns true before these can be called.
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*/
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static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
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{
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WARN_ON(!drv_data->lpss_base);
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return readl(drv_data->lpss_base + offset);
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}
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static void __lpss_ssp_write_priv(struct driver_data *drv_data,
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unsigned offset, u32 value)
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{
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WARN_ON(!drv_data->lpss_base);
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writel(value, drv_data->lpss_base + offset);
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}
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/*
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* lpss_ssp_setup - perform LPSS SSP specific setup
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* @drv_data: pointer to the driver private data
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*
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* Perform LPSS SSP specific setup. This function must be called first if
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* one is going to use LPSS SSP private registers.
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*/
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static void lpss_ssp_setup(struct driver_data *drv_data)
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{
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unsigned offset = 0x400;
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u32 value, orig;
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if (!is_lpss_ssp(drv_data))
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return;
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/*
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* Perform auto-detection of the LPSS SSP private registers. They
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* can be either at 1k or 2k offset from the base address.
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*/
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orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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2014-06-13 15:57:25 +00:00
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/* Test SPI_CS_CONTROL_SW_MODE bit enabling */
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2013-01-22 10:26:32 +00:00
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value = orig | SPI_CS_CONTROL_SW_MODE;
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writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
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value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
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offset = 0x800;
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goto detection_done;
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}
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2014-06-13 15:57:25 +00:00
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orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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/* Test SPI_CS_CONTROL_SW_MODE bit disabling */
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value = orig & ~SPI_CS_CONTROL_SW_MODE;
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2013-01-22 10:26:32 +00:00
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writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
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value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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2014-06-13 15:57:25 +00:00
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if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {
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2013-01-22 10:26:32 +00:00
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offset = 0x800;
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goto detection_done;
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}
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detection_done:
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/* Now set the LPSS base */
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drv_data->lpss_base = drv_data->ioaddr + offset;
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/* Enable software chip select control */
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value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
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__lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
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2013-03-05 10:05:17 +00:00
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/* Enable multiblock DMA transfers */
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2013-07-03 10:25:06 +00:00
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if (drv_data->master_info->enable_dma) {
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2013-03-05 10:05:17 +00:00
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__lpss_ssp_write_priv(drv_data, SSP_REG, 1);
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2013-07-03 10:25:06 +00:00
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value = __lpss_ssp_read_priv(drv_data, GENERAL_REG);
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value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
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__lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
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}
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2013-01-22 10:26:32 +00:00
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}
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static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
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{
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u32 value;
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if (!is_lpss_ssp(drv_data))
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return;
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value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
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if (enable)
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value &= ~SPI_CS_CONTROL_CS_HIGH;
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else
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value |= SPI_CS_CONTROL_CS_HIGH;
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__lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
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}
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2009-04-07 02:00:54 +00:00
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static void cs_assert(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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2010-11-23 01:12:17 +00:00
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if (drv_data->ssp_type == CE4100_SSP) {
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write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
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return;
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}
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2009-04-07 02:00:54 +00:00
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if (chip->cs_control) {
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chip->cs_control(PXA2XX_CS_ASSERT);
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return;
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}
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2013-01-22 10:26:32 +00:00
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if (gpio_is_valid(chip->gpio_cs)) {
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2009-04-07 02:00:54 +00:00
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gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
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2013-01-22 10:26:32 +00:00
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return;
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}
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lpss_ssp_cs_control(drv_data, true);
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2009-04-07 02:00:54 +00:00
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}
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static void cs_deassert(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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2010-11-23 01:12:17 +00:00
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if (drv_data->ssp_type == CE4100_SSP)
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return;
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2009-04-07 02:00:54 +00:00
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if (chip->cs_control) {
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2009-04-09 01:48:03 +00:00
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chip->cs_control(PXA2XX_CS_DEASSERT);
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2009-04-07 02:00:54 +00:00
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return;
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}
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2013-01-22 10:26:32 +00:00
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if (gpio_is_valid(chip->gpio_cs)) {
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2009-04-07 02:00:54 +00:00
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gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
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2013-01-22 10:26:32 +00:00
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return;
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}
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lpss_ssp_cs_control(drv_data, false);
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2009-04-07 02:00:54 +00:00
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}
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2013-01-22 10:26:28 +00:00
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int pxa2xx_spi_flush(struct driver_data *drv_data)
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2006-03-08 07:53:24 +00:00
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{
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unsigned long limit = loops_per_jiffy << 1;
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2008-04-28 09:14:17 +00:00
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void __iomem *reg = drv_data->ioaddr;
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2006-03-08 07:53:24 +00:00
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do {
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while (read_SSSR(reg) & SSSR_RNE) {
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read_SSDR(reg);
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}
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2009-04-21 19:24:46 +00:00
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} while ((read_SSSR(reg) & SSSR_BSY) && --limit);
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2010-11-23 01:12:17 +00:00
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write_SSSR_CS(drv_data, SSSR_ROR);
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2006-03-08 07:53:24 +00:00
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return limit;
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}
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2006-12-10 10:18:54 +00:00
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static int null_writer(struct driver_data *drv_data)
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2006-03-08 07:53:24 +00:00
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{
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2008-04-28 09:14:17 +00:00
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void __iomem *reg = drv_data->ioaddr;
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2006-03-28 22:05:23 +00:00
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u8 n_bytes = drv_data->n_bytes;
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2006-03-08 07:53:24 +00:00
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2010-11-23 01:12:15 +00:00
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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2006-12-10 10:18:54 +00:00
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|| (drv_data->tx == drv_data->tx_end))
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return 0;
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write_SSDR(0, reg);
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drv_data->tx += n_bytes;
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return 1;
|
2006-03-08 07:53:24 +00:00
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}
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2006-12-10 10:18:54 +00:00
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static int null_reader(struct driver_data *drv_data)
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2006-03-08 07:53:24 +00:00
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{
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2008-04-28 09:14:17 +00:00
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void __iomem *reg = drv_data->ioaddr;
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2006-03-28 22:05:23 +00:00
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u8 n_bytes = drv_data->n_bytes;
|
2006-03-08 07:53:24 +00:00
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while ((read_SSSR(reg) & SSSR_RNE)
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2006-12-10 10:18:54 +00:00
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&& (drv_data->rx < drv_data->rx_end)) {
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2006-03-08 07:53:24 +00:00
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read_SSDR(reg);
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drv_data->rx += n_bytes;
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}
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2006-12-10 10:18:54 +00:00
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|
|
|
return drv_data->rx == drv_data->rx_end;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static int u8_writer(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2010-11-23 01:12:15 +00:00
|
|
|
if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
|
2006-12-10 10:18:54 +00:00
|
|
|
|| (drv_data->tx == drv_data->tx_end))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
write_SSDR(*(u8 *)(drv_data->tx), reg);
|
|
|
|
++drv_data->tx;
|
|
|
|
|
|
|
|
return 1;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static int u8_reader(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
while ((read_SSSR(reg) & SSSR_RNE)
|
2006-12-10 10:18:54 +00:00
|
|
|
&& (drv_data->rx < drv_data->rx_end)) {
|
2006-03-08 07:53:24 +00:00
|
|
|
*(u8 *)(drv_data->rx) = read_SSDR(reg);
|
|
|
|
++drv_data->rx;
|
|
|
|
}
|
2006-12-10 10:18:54 +00:00
|
|
|
|
|
|
|
return drv_data->rx == drv_data->rx_end;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static int u16_writer(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2010-11-23 01:12:15 +00:00
|
|
|
if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
|
2006-12-10 10:18:54 +00:00
|
|
|
|| (drv_data->tx == drv_data->tx_end))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
write_SSDR(*(u16 *)(drv_data->tx), reg);
|
|
|
|
drv_data->tx += 2;
|
|
|
|
|
|
|
|
return 1;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static int u16_reader(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
while ((read_SSSR(reg) & SSSR_RNE)
|
2006-12-10 10:18:54 +00:00
|
|
|
&& (drv_data->rx < drv_data->rx_end)) {
|
2006-03-08 07:53:24 +00:00
|
|
|
*(u16 *)(drv_data->rx) = read_SSDR(reg);
|
|
|
|
drv_data->rx += 2;
|
|
|
|
}
|
2006-12-10 10:18:54 +00:00
|
|
|
|
|
|
|
return drv_data->rx == drv_data->rx_end;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
2006-12-10 10:18:54 +00:00
|
|
|
|
|
|
|
static int u32_writer(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2010-11-23 01:12:15 +00:00
|
|
|
if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
|
2006-12-10 10:18:54 +00:00
|
|
|
|| (drv_data->tx == drv_data->tx_end))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
write_SSDR(*(u32 *)(drv_data->tx), reg);
|
|
|
|
drv_data->tx += 4;
|
|
|
|
|
|
|
|
return 1;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static int u32_reader(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
while ((read_SSSR(reg) & SSSR_RNE)
|
2006-12-10 10:18:54 +00:00
|
|
|
&& (drv_data->rx < drv_data->rx_end)) {
|
2006-03-08 07:53:24 +00:00
|
|
|
*(u32 *)(drv_data->rx) = read_SSDR(reg);
|
|
|
|
drv_data->rx += 4;
|
|
|
|
}
|
2006-12-10 10:18:54 +00:00
|
|
|
|
|
|
|
return drv_data->rx == drv_data->rx_end;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2013-01-22 10:26:28 +00:00
|
|
|
void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
|
|
|
struct spi_message *msg = drv_data->cur_msg;
|
|
|
|
struct spi_transfer *trans = drv_data->cur_transfer;
|
|
|
|
|
|
|
|
/* Move to next transfer */
|
|
|
|
if (trans->transfer_list.next != &msg->transfers) {
|
|
|
|
drv_data->cur_transfer =
|
|
|
|
list_entry(trans->transfer_list.next,
|
|
|
|
struct spi_transfer,
|
|
|
|
transfer_list);
|
|
|
|
return RUNNING_STATE;
|
|
|
|
} else
|
|
|
|
return DONE_STATE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* caller already set message->status; dma and pio irqs are blocked */
|
2006-05-20 22:00:19 +00:00
|
|
|
static void giveback(struct driver_data *drv_data)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
|
|
|
struct spi_transfer* last_transfer;
|
2006-05-20 22:00:19 +00:00
|
|
|
struct spi_message *msg;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-05-20 22:00:19 +00:00
|
|
|
msg = drv_data->cur_msg;
|
|
|
|
drv_data->cur_msg = NULL;
|
|
|
|
drv_data->cur_transfer = NULL;
|
|
|
|
|
2014-02-12 14:13:27 +00:00
|
|
|
last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
|
2006-03-08 07:53:24 +00:00
|
|
|
transfer_list);
|
|
|
|
|
2008-09-13 09:33:17 +00:00
|
|
|
/* Delay if requested before any change in chip select */
|
|
|
|
if (last_transfer->delay_usecs)
|
|
|
|
udelay(last_transfer->delay_usecs);
|
|
|
|
|
|
|
|
/* Drop chip select UNLESS cs_change is true or we are returning
|
|
|
|
* a message with an error, or next message is for another chip
|
|
|
|
*/
|
2006-03-08 07:53:24 +00:00
|
|
|
if (!last_transfer->cs_change)
|
2009-04-07 02:00:54 +00:00
|
|
|
cs_deassert(drv_data);
|
2008-09-13 09:33:17 +00:00
|
|
|
else {
|
|
|
|
struct spi_message *next_msg;
|
|
|
|
|
|
|
|
/* Holding of cs was hinted, but we need to make sure
|
|
|
|
* the next message is for the same chip. Don't waste
|
|
|
|
* time with the following tests unless this was hinted.
|
|
|
|
*
|
|
|
|
* We cannot postpone this until pump_messages, because
|
|
|
|
* after calling msg->complete (below) the driver that
|
|
|
|
* sent the current message could be unloaded, which
|
|
|
|
* could invalidate the cs_control() callback...
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* get a pointer to the next message, if any */
|
2013-01-22 10:26:26 +00:00
|
|
|
next_msg = spi_get_next_queued_message(drv_data->master);
|
2008-09-13 09:33:17 +00:00
|
|
|
|
|
|
|
/* see if the next and current messages point
|
|
|
|
* to the same chip
|
|
|
|
*/
|
|
|
|
if (next_msg && next_msg->spi != msg->spi)
|
|
|
|
next_msg = NULL;
|
|
|
|
if (!next_msg || msg->state == ERROR_STATE)
|
2009-04-07 02:00:54 +00:00
|
|
|
cs_deassert(drv_data);
|
2008-09-13 09:33:17 +00:00
|
|
|
}
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2013-01-22 10:26:26 +00:00
|
|
|
spi_finalize_current_message(drv_data->master);
|
2009-04-07 02:00:54 +00:00
|
|
|
drv_data->cur_chip = NULL;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2010-11-23 01:12:17 +00:00
|
|
|
static void reset_sccr1(struct driver_data *drv_data)
|
|
|
|
{
|
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
|
|
|
struct chip_data *chip = drv_data->cur_chip;
|
|
|
|
u32 sccr1_reg;
|
|
|
|
|
|
|
|
sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
|
|
|
|
sccr1_reg &= ~SSCR1_RFT;
|
|
|
|
sccr1_reg |= chip->threshold;
|
|
|
|
write_SSCR1(sccr1_reg, reg);
|
|
|
|
}
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static void int_error_stop(struct driver_data *drv_data, const char* msg)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* Stop and reset SSP */
|
2010-11-23 01:12:17 +00:00
|
|
|
write_SSSR_CS(drv_data, drv_data->clear_sr);
|
2010-11-23 01:12:17 +00:00
|
|
|
reset_sccr1(drv_data);
|
2010-11-23 01:12:17 +00:00
|
|
|
if (!pxa25x_ssp_comp(drv_data))
|
2006-12-10 10:18:54 +00:00
|
|
|
write_SSTO(0, reg);
|
2013-01-22 10:26:28 +00:00
|
|
|
pxa2xx_spi_flush(drv_data);
|
2006-12-10 10:18:54 +00:00
|
|
|
write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
dev_err(&drv_data->pdev->dev, "%s\n", msg);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
drv_data->cur_msg->state = ERROR_STATE;
|
|
|
|
tasklet_schedule(&drv_data->pump_transfers);
|
|
|
|
}
|
2006-05-20 22:00:19 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static void int_transfer_complete(struct driver_data *drv_data)
|
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* Stop SSP */
|
2010-11-23 01:12:17 +00:00
|
|
|
write_SSSR_CS(drv_data, drv_data->clear_sr);
|
2010-11-23 01:12:17 +00:00
|
|
|
reset_sccr1(drv_data);
|
2010-11-23 01:12:17 +00:00
|
|
|
if (!pxa25x_ssp_comp(drv_data))
|
2006-12-10 10:18:54 +00:00
|
|
|
write_SSTO(0, reg);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2011-03-31 01:57:33 +00:00
|
|
|
/* Update total byte transferred return count actual bytes read */
|
2006-12-10 10:18:54 +00:00
|
|
|
drv_data->cur_msg->actual_length += drv_data->len -
|
|
|
|
(drv_data->rx_end - drv_data->rx);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2008-09-13 09:33:17 +00:00
|
|
|
/* Transfer delays and chip select release are
|
|
|
|
* handled in pump_transfers or giveback
|
|
|
|
*/
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* Move to next transfer */
|
2013-01-22 10:26:28 +00:00
|
|
|
drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* Schedule transfer tasklet */
|
|
|
|
tasklet_schedule(&drv_data->pump_transfers);
|
|
|
|
}
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
|
|
|
|
{
|
2008-04-28 09:14:17 +00:00
|
|
|
void __iomem *reg = drv_data->ioaddr;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
|
|
|
|
drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
u32 irq_status = read_SSSR(reg) & irq_mask;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
if (irq_status & SSSR_ROR) {
|
|
|
|
int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
if (irq_status & SSSR_TINT) {
|
|
|
|
write_SSSR(SSSR_TINT, reg);
|
|
|
|
if (drv_data->read(drv_data)) {
|
|
|
|
int_transfer_complete(drv_data);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* Drain rx fifo, Fill tx fifo and prevent overruns */
|
|
|
|
do {
|
|
|
|
if (drv_data->read(drv_data)) {
|
|
|
|
int_transfer_complete(drv_data);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
} while (drv_data->write(drv_data));
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
if (drv_data->read(drv_data)) {
|
|
|
|
int_transfer_complete(drv_data);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
if (drv_data->tx == drv_data->tx_end) {
|
2010-11-23 01:12:17 +00:00
|
|
|
u32 bytes_left;
|
|
|
|
u32 sccr1_reg;
|
|
|
|
|
|
|
|
sccr1_reg = read_SSCR1(reg);
|
|
|
|
sccr1_reg &= ~SSCR1_TIE;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PXA25x_SSP has no timeout, set up rx threshould for the
|
2011-03-31 01:57:33 +00:00
|
|
|
* remaining RX bytes.
|
2010-11-23 01:12:17 +00:00
|
|
|
*/
|
2010-11-23 01:12:17 +00:00
|
|
|
if (pxa25x_ssp_comp(drv_data)) {
|
2010-11-23 01:12:17 +00:00
|
|
|
|
|
|
|
sccr1_reg &= ~SSCR1_RFT;
|
|
|
|
|
|
|
|
bytes_left = drv_data->rx_end - drv_data->rx;
|
|
|
|
switch (drv_data->n_bytes) {
|
|
|
|
case 4:
|
|
|
|
bytes_left >>= 1;
|
|
|
|
case 2:
|
|
|
|
bytes_left >>= 1;
|
2006-12-10 10:18:54 +00:00
|
|
|
}
|
2010-11-23 01:12:17 +00:00
|
|
|
|
|
|
|
if (bytes_left > RX_THRESH_DFLT)
|
|
|
|
bytes_left = RX_THRESH_DFLT;
|
|
|
|
|
|
|
|
sccr1_reg |= SSCR1_RxTresh(bytes_left);
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
2010-11-23 01:12:17 +00:00
|
|
|
write_SSCR1(sccr1_reg, reg);
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2006-05-20 22:00:19 +00:00
|
|
|
/* We did something */
|
|
|
|
return IRQ_HANDLED;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 13:55:46 +00:00
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static irqreturn_t ssp_int(int irq, void *dev_id)
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2006-03-08 07:53:24 +00:00
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{
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2006-10-06 19:00:58 +00:00
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struct driver_data *drv_data = dev_id;
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2008-04-28 09:14:17 +00:00
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void __iomem *reg = drv_data->ioaddr;
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2013-01-22 10:26:30 +00:00
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u32 sccr1_reg;
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2010-11-23 01:12:14 +00:00
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u32 mask = drv_data->mask_sr;
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u32 status;
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2013-01-22 10:26:30 +00:00
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/*
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* The IRQ might be shared with other peripherals so we must first
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* check that are we RPM suspended or not. If we are we assume that
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* the IRQ was not for us (we shouldn't be RPM suspended when the
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* interrupt is enabled).
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*/
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if (pm_runtime_suspended(&drv_data->pdev->dev))
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return IRQ_NONE;
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2013-09-04 10:37:43 +00:00
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/*
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* If the device is not yet in RPM suspended state and we get an
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* interrupt that is meant for another device, check if status bits
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* are all set to one. That means that the device is already
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* powered off.
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*/
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2010-11-23 01:12:14 +00:00
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status = read_SSSR(reg);
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2013-09-04 10:37:43 +00:00
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if (status == ~0)
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return IRQ_NONE;
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sccr1_reg = read_SSCR1(reg);
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2010-11-23 01:12:14 +00:00
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/* Ignore possible writes if we don't need to write */
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if (!(sccr1_reg & SSCR1_TIE))
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mask &= ~SSSR_TFS;
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if (!(status & mask))
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return IRQ_NONE;
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2006-03-08 07:53:24 +00:00
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if (!drv_data->cur_msg) {
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2006-05-20 22:00:19 +00:00
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
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2010-11-23 01:12:17 +00:00
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if (!pxa25x_ssp_comp(drv_data))
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2006-05-20 22:00:19 +00:00
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write_SSTO(0, reg);
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2010-11-23 01:12:17 +00:00
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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2006-05-20 22:00:19 +00:00
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2013-10-11 10:54:00 +00:00
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dev_err(&drv_data->pdev->dev,
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"bad message state in interrupt handler\n");
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2006-05-20 22:00:19 +00:00
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2006-03-08 07:53:24 +00:00
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/* Never fail */
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return IRQ_HANDLED;
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}
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return drv_data->transfer_handler(drv_data);
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}
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2013-01-22 10:26:27 +00:00
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static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
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2007-11-21 10:50:53 +00:00
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{
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2013-01-22 10:26:27 +00:00
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unsigned long ssp_clk = drv_data->max_clk_rate;
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const struct ssp_device *ssp = drv_data->ssp;
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rate = min_t(int, ssp_clk, rate);
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2007-11-21 10:50:53 +00:00
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2010-11-23 01:12:17 +00:00
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if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
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2007-11-21 10:50:53 +00:00
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return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
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else
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return ((ssp_clk / rate - 1) & 0xfff) << 8;
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}
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2006-03-08 07:53:24 +00:00
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static void pump_transfers(unsigned long data)
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{
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struct driver_data *drv_data = (struct driver_data *)data;
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struct spi_message *message = NULL;
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struct spi_transfer *transfer = NULL;
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struct spi_transfer *previous = NULL;
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struct chip_data *chip = NULL;
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2008-04-28 09:14:17 +00:00
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void __iomem *reg = drv_data->ioaddr;
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2006-03-28 22:05:23 +00:00
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u32 clk_div = 0;
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u8 bits = 0;
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u32 speed = 0;
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u32 cr0;
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2006-12-10 10:18:54 +00:00
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u32 cr1;
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u32 dma_thresh = drv_data->cur_chip->dma_threshold;
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u32 dma_burst = drv_data->cur_chip->dma_burst_size;
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2006-03-08 07:53:24 +00:00
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/* Get current state information */
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message = drv_data->cur_msg;
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transfer = drv_data->cur_transfer;
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chip = drv_data->cur_chip;
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/* Handle for abort */
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if (message->state == ERROR_STATE) {
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message->status = -EIO;
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2006-05-20 22:00:19 +00:00
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giveback(drv_data);
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2006-03-08 07:53:24 +00:00
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return;
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}
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/* Handle end of message */
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if (message->state == DONE_STATE) {
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message->status = 0;
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2006-05-20 22:00:19 +00:00
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giveback(drv_data);
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2006-03-08 07:53:24 +00:00
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return;
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}
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2008-09-13 09:33:17 +00:00
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/* Delay if requested at end of transfer before CS change */
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2006-03-08 07:53:24 +00:00
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if (message->state == RUNNING_STATE) {
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previous = list_entry(transfer->transfer_list.prev,
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struct spi_transfer,
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transfer_list);
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if (previous->delay_usecs)
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udelay(previous->delay_usecs);
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2008-09-13 09:33:17 +00:00
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/* Drop chip select only if cs_change is requested */
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if (previous->cs_change)
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2009-04-07 02:00:54 +00:00
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cs_deassert(drv_data);
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2006-03-08 07:53:24 +00:00
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}
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2013-01-22 10:26:28 +00:00
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/* Check if we can DMA this transfer */
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if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
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2008-09-13 09:33:18 +00:00
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/* reject already-mapped transfers; PIO won't always work */
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if (message->is_dma_mapped
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|| transfer->rx_dma || transfer->tx_dma) {
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dev_err(&drv_data->pdev->dev,
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2013-10-11 10:54:00 +00:00
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"pump_transfers: mapped transfer length of "
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"%u is greater than %d\n",
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2008-09-13 09:33:18 +00:00
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transfer->len, MAX_DMA_LEN);
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message->status = -EINVAL;
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giveback(drv_data);
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return;
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}
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/* warn ... we force this to PIO mode */
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2013-10-11 10:54:00 +00:00
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dev_warn_ratelimited(&message->spi->dev,
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"pump_transfers: DMA disabled for transfer length %ld "
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"greater than %d\n",
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(long)drv_data->len, MAX_DMA_LEN);
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2006-12-10 10:18:54 +00:00
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}
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2006-03-08 07:53:24 +00:00
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/* Setup the transfer state based on the type of transfer */
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2013-01-22 10:26:28 +00:00
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if (pxa2xx_spi_flush(drv_data) == 0) {
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2006-03-08 07:53:24 +00:00
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dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
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message->status = -EIO;
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2006-05-20 22:00:19 +00:00
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giveback(drv_data);
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2006-03-08 07:53:24 +00:00
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return;
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}
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2006-03-28 22:05:23 +00:00
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drv_data->n_bytes = chip->n_bytes;
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2006-03-08 07:53:24 +00:00
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drv_data->tx = (void *)transfer->tx_buf;
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drv_data->tx_end = drv_data->tx + transfer->len;
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drv_data->rx = transfer->rx_buf;
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drv_data->rx_end = drv_data->rx + transfer->len;
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drv_data->rx_dma = transfer->rx_dma;
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drv_data->tx_dma = transfer->tx_dma;
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2013-01-22 10:26:28 +00:00
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drv_data->len = transfer->len;
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2006-03-08 07:53:24 +00:00
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drv_data->write = drv_data->tx ? chip->write : null_writer;
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drv_data->read = drv_data->rx ? chip->read : null_reader;
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2006-03-28 22:05:23 +00:00
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/* Change speed and bit per word on a per transfer */
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2006-12-10 10:18:54 +00:00
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cr0 = chip->cr0;
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2006-03-28 22:05:23 +00:00
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if (transfer->speed_hz || transfer->bits_per_word) {
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bits = chip->bits_per_word;
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speed = chip->speed_hz;
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if (transfer->speed_hz)
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speed = transfer->speed_hz;
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if (transfer->bits_per_word)
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bits = transfer->bits_per_word;
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2013-01-22 10:26:27 +00:00
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clk_div = ssp_get_clk_div(drv_data, speed);
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2006-03-28 22:05:23 +00:00
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if (bits <= 8) {
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drv_data->n_bytes = 1;
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drv_data->read = drv_data->read != null_reader ?
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u8_reader : null_reader;
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drv_data->write = drv_data->write != null_writer ?
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u8_writer : null_writer;
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} else if (bits <= 16) {
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drv_data->n_bytes = 2;
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drv_data->read = drv_data->read != null_reader ?
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u16_reader : null_reader;
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drv_data->write = drv_data->write != null_writer ?
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u16_writer : null_writer;
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} else if (bits <= 32) {
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drv_data->n_bytes = 4;
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drv_data->read = drv_data->read != null_reader ?
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u32_reader : null_reader;
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drv_data->write = drv_data->write != null_writer ?
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u32_writer : null_writer;
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}
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2006-12-10 10:18:54 +00:00
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/* if bits/word is changed in dma mode, then must check the
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* thresholds and burst also */
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if (chip->enable_dma) {
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2013-01-22 10:26:28 +00:00
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if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
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message->spi,
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2006-12-10 10:18:54 +00:00
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bits, &dma_burst,
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&dma_thresh))
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2013-10-11 10:54:00 +00:00
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dev_warn_ratelimited(&message->spi->dev,
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"pump_transfers: DMA burst size reduced to match bits_per_word\n");
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2006-12-10 10:18:54 +00:00
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}
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2006-03-28 22:05:23 +00:00
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cr0 = clk_div
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| SSCR0_Motorola
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2006-05-20 22:00:19 +00:00
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| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
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2006-03-28 22:05:23 +00:00
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| SSCR0_SSE
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| (bits > 16 ? SSCR0_EDSS : 0);
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}
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2006-03-08 07:53:24 +00:00
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message->state = RUNNING_STATE;
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2008-09-13 09:33:18 +00:00
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drv_data->dma_mapped = 0;
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2013-01-22 10:26:28 +00:00
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if (pxa2xx_spi_dma_is_possible(drv_data->len))
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drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
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2008-09-13 09:33:18 +00:00
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if (drv_data->dma_mapped) {
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2006-03-08 07:53:24 +00:00
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/* Ensure we have the correct interrupt handler */
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2013-01-22 10:26:28 +00:00
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drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
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pxa2xx_spi_dma_prepare(drv_data, dma_burst);
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2006-03-08 07:53:24 +00:00
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2006-12-10 10:18:54 +00:00
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/* Clear status and start DMA engine */
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cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
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2006-03-08 07:53:24 +00:00
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write_SSSR(drv_data->clear_sr, reg);
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2013-01-22 10:26:28 +00:00
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pxa2xx_spi_dma_start(drv_data);
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2006-03-08 07:53:24 +00:00
|
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} else {
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/* Ensure we have the correct interrupt handler */
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drv_data->transfer_handler = interrupt_transfer;
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2006-12-10 10:18:54 +00:00
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/* Clear status */
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|
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cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
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2010-11-23 01:12:17 +00:00
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write_SSSR_CS(drv_data, drv_data->clear_sr);
|
2006-12-10 10:18:54 +00:00
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}
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2013-01-22 10:26:32 +00:00
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if (is_lpss_ssp(drv_data)) {
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|
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if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
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write_SSIRF(chip->lpss_rx_threshold, reg);
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|
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if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
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write_SSITF(chip->lpss_tx_threshold, reg);
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}
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|
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|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* see if we need to reload the config registers */
|
|
|
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if ((read_SSCR0(reg) != cr0)
|
|
|
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|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
|
|
|
|
(cr1 & SSCR1_CHANGE_MASK)) {
|
|
|
|
|
2008-02-23 23:23:40 +00:00
|
|
|
/* stop the SSP, and update the other bits */
|
2006-12-10 10:18:54 +00:00
|
|
|
write_SSCR0(cr0 & ~SSCR0_SSE, reg);
|
2010-11-23 01:12:17 +00:00
|
|
|
if (!pxa25x_ssp_comp(drv_data))
|
2006-03-08 07:53:24 +00:00
|
|
|
write_SSTO(chip->timeout, reg);
|
2008-02-23 23:23:40 +00:00
|
|
|
/* first set CR1 without interrupt and service enables */
|
|
|
|
write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
|
|
|
|
/* restart the SSP */
|
2006-12-10 10:18:54 +00:00
|
|
|
write_SSCR0(cr0, reg);
|
2008-02-23 23:23:40 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
} else {
|
2010-11-23 01:12:17 +00:00
|
|
|
if (!pxa25x_ssp_comp(drv_data))
|
2006-12-10 10:18:54 +00:00
|
|
|
write_SSTO(chip->timeout, reg);
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
2008-02-23 23:23:40 +00:00
|
|
|
|
2009-04-07 02:00:54 +00:00
|
|
|
cs_assert(drv_data);
|
2008-02-23 23:23:40 +00:00
|
|
|
|
|
|
|
/* after chip select, release the data by enabling service
|
|
|
|
* requests and interrupts, without changing any mode bits */
|
|
|
|
write_SSCR1(cr1, reg);
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2013-01-22 10:26:26 +00:00
|
|
|
static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
|
|
|
|
struct spi_message *msg)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2013-01-22 10:26:26 +00:00
|
|
|
struct driver_data *drv_data = spi_master_get_devdata(master);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2013-01-22 10:26:26 +00:00
|
|
|
drv_data->cur_msg = msg;
|
2006-03-08 07:53:24 +00:00
|
|
|
/* Initial message state*/
|
|
|
|
drv_data->cur_msg->state = START_STATE;
|
|
|
|
drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
|
|
|
|
struct spi_transfer,
|
|
|
|
transfer_list);
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* prepare to setup the SSP, in pump_transfers, using the per
|
|
|
|
* chip configuration */
|
2006-03-08 07:53:24 +00:00
|
|
|
drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
|
|
|
|
|
|
|
|
/* Mark as busy and launch transfers */
|
|
|
|
tasklet_schedule(&drv_data->pump_transfers);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-01-22 10:26:30 +00:00
|
|
|
static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
|
|
|
|
{
|
|
|
|
struct driver_data *drv_data = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
/* Disable the SSP now */
|
|
|
|
write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
|
|
|
|
drv_data->ioaddr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-07 02:00:54 +00:00
|
|
|
static int setup_cs(struct spi_device *spi, struct chip_data *chip,
|
|
|
|
struct pxa2xx_spi_chip *chip_info)
|
|
|
|
{
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (chip == NULL || chip_info == NULL)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* NOTE: setup() can be called multiple times, possibly with
|
|
|
|
* different chip_info, release previously requested GPIO
|
|
|
|
*/
|
|
|
|
if (gpio_is_valid(chip->gpio_cs))
|
|
|
|
gpio_free(chip->gpio_cs);
|
|
|
|
|
|
|
|
/* If (*cs_control) is provided, ignore GPIO chip select */
|
|
|
|
if (chip_info->cs_control) {
|
|
|
|
chip->cs_control = chip_info->cs_control;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (gpio_is_valid(chip_info->gpio_cs)) {
|
|
|
|
err = gpio_request(chip_info->gpio_cs, "SPI_CS");
|
|
|
|
if (err) {
|
2013-10-11 10:54:00 +00:00
|
|
|
dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
|
|
|
|
chip_info->gpio_cs);
|
2009-04-07 02:00:54 +00:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
chip->gpio_cs = chip_info->gpio_cs;
|
|
|
|
chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
|
|
|
|
|
|
|
|
err = gpio_direction_output(chip->gpio_cs,
|
|
|
|
!chip->gpio_cs_inverted);
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
static int setup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct pxa2xx_spi_chip *chip_info = NULL;
|
|
|
|
struct chip_data *chip;
|
|
|
|
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
|
|
|
|
unsigned int clk_div;
|
2013-01-22 10:26:32 +00:00
|
|
|
uint tx_thres, tx_hi_thres, rx_thres;
|
|
|
|
|
|
|
|
if (is_lpss_ssp(drv_data)) {
|
|
|
|
tx_thres = LPSS_TX_LOTHRESH_DFLT;
|
|
|
|
tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
|
|
|
|
rx_thres = LPSS_RX_THRESH_DFLT;
|
|
|
|
} else {
|
|
|
|
tx_thres = TX_THRESH_DFLT;
|
|
|
|
tx_hi_thres = 0;
|
|
|
|
rx_thres = RX_THRESH_DFLT;
|
|
|
|
}
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* Only alloc on first setup */
|
2006-03-08 07:53:24 +00:00
|
|
|
chip = spi_get_ctldata(spi);
|
2006-12-10 10:18:54 +00:00
|
|
|
if (!chip) {
|
2006-03-08 07:53:24 +00:00
|
|
|
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
2014-04-29 08:19:38 +00:00
|
|
|
if (!chip)
|
2006-03-08 07:53:24 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-11-23 01:12:17 +00:00
|
|
|
if (drv_data->ssp_type == CE4100_SSP) {
|
|
|
|
if (spi->chip_select > 4) {
|
2013-10-11 10:54:00 +00:00
|
|
|
dev_err(&spi->dev,
|
|
|
|
"failed setup: cs number must not be > 4.\n");
|
2010-11-23 01:12:17 +00:00
|
|
|
kfree(chip);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
chip->frm = spi->chip_select;
|
|
|
|
} else
|
|
|
|
chip->gpio_cs = -1;
|
2006-03-08 07:53:24 +00:00
|
|
|
chip->enable_dma = 0;
|
2008-10-16 05:02:43 +00:00
|
|
|
chip->timeout = TIMOUT_DFLT;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* protocol drivers may change the chip settings, so...
|
|
|
|
* if chip_info exists, use it */
|
|
|
|
chip_info = spi->controller_data;
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
/* chip_info isn't always needed */
|
2006-12-10 10:18:54 +00:00
|
|
|
chip->cr1 = 0;
|
2006-03-08 07:53:24 +00:00
|
|
|
if (chip_info) {
|
2008-10-16 05:02:43 +00:00
|
|
|
if (chip_info->timeout)
|
|
|
|
chip->timeout = chip_info->timeout;
|
|
|
|
if (chip_info->tx_threshold)
|
|
|
|
tx_thres = chip_info->tx_threshold;
|
2013-01-22 10:26:32 +00:00
|
|
|
if (chip_info->tx_hi_threshold)
|
|
|
|
tx_hi_thres = chip_info->tx_hi_threshold;
|
2008-10-16 05:02:43 +00:00
|
|
|
if (chip_info->rx_threshold)
|
|
|
|
rx_thres = chip_info->rx_threshold;
|
|
|
|
chip->enable_dma = drv_data->master_info->enable_dma;
|
2006-03-08 07:53:24 +00:00
|
|
|
chip->dma_threshold = 0;
|
|
|
|
if (chip_info->enable_loopback)
|
|
|
|
chip->cr1 = SSCR1_LBM;
|
2013-01-22 10:26:33 +00:00
|
|
|
} else if (ACPI_HANDLE(&spi->dev)) {
|
|
|
|
/*
|
|
|
|
* Slave devices enumerated from ACPI namespace don't
|
|
|
|
* usually have chip_info but we still might want to use
|
|
|
|
* DMA with them.
|
|
|
|
*/
|
|
|
|
chip->enable_dma = drv_data->master_info->enable_dma;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2008-10-16 05:02:43 +00:00
|
|
|
chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
|
|
|
|
(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
|
|
|
|
|
2013-01-22 10:26:32 +00:00
|
|
|
chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
|
|
|
|
chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
|
|
|
|
| SSITF_TxHiThresh(tx_hi_thres);
|
|
|
|
|
2006-12-10 10:18:54 +00:00
|
|
|
/* set dma burst and threshold outside of chip_info path so that if
|
|
|
|
* chip_info goes away after setting chip->enable_dma, the
|
|
|
|
* burst and threshold can still respond to changes in bits_per_word */
|
|
|
|
if (chip->enable_dma) {
|
|
|
|
/* set up legal burst and threshold for dma */
|
2013-01-22 10:26:28 +00:00
|
|
|
if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
|
|
|
|
spi->bits_per_word,
|
2006-12-10 10:18:54 +00:00
|
|
|
&chip->dma_burst_size,
|
|
|
|
&chip->dma_threshold)) {
|
2013-10-11 10:54:00 +00:00
|
|
|
dev_warn(&spi->dev,
|
|
|
|
"in setup: DMA burst size reduced to match bits_per_word\n");
|
2006-12-10 10:18:54 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-22 10:26:27 +00:00
|
|
|
clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
|
2006-03-28 22:05:23 +00:00
|
|
|
chip->speed_hz = spi->max_speed_hz;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
chip->cr0 = clk_div
|
|
|
|
| SSCR0_Motorola
|
2006-05-20 22:00:19 +00:00
|
|
|
| SSCR0_DataSize(spi->bits_per_word > 16 ?
|
|
|
|
spi->bits_per_word - 16 : spi->bits_per_word)
|
2006-03-08 07:53:24 +00:00
|
|
|
| SSCR0_SSE
|
|
|
|
| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
|
2007-01-26 08:56:44 +00:00
|
|
|
chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
|
|
|
|
chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
|
|
|
|
| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2013-01-22 10:26:31 +00:00
|
|
|
if (spi->mode & SPI_LOOP)
|
|
|
|
chip->cr1 |= SSCR1_LBM;
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
/* NOTE: PXA25x_SSP _could_ use external clocking ... */
|
2010-11-23 01:12:17 +00:00
|
|
|
if (!pxa25x_ssp_comp(drv_data))
|
2009-06-17 23:26:03 +00:00
|
|
|
dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
|
2013-01-22 10:26:27 +00:00
|
|
|
drv_data->max_clk_rate
|
2010-03-16 08:48:01 +00:00
|
|
|
/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
|
|
|
|
chip->enable_dma ? "DMA" : "PIO");
|
2006-03-08 07:53:24 +00:00
|
|
|
else
|
2009-06-17 23:26:03 +00:00
|
|
|
dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
|
2013-01-22 10:26:27 +00:00
|
|
|
drv_data->max_clk_rate / 2
|
2010-03-16 08:48:01 +00:00
|
|
|
/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
|
|
|
|
chip->enable_dma ? "DMA" : "PIO");
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
if (spi->bits_per_word <= 8) {
|
|
|
|
chip->n_bytes = 1;
|
|
|
|
chip->read = u8_reader;
|
|
|
|
chip->write = u8_writer;
|
|
|
|
} else if (spi->bits_per_word <= 16) {
|
|
|
|
chip->n_bytes = 2;
|
|
|
|
chip->read = u16_reader;
|
|
|
|
chip->write = u16_writer;
|
|
|
|
} else if (spi->bits_per_word <= 32) {
|
|
|
|
chip->cr0 |= SSCR0_EDSS;
|
|
|
|
chip->n_bytes = 4;
|
|
|
|
chip->read = u32_reader;
|
|
|
|
chip->write = u32_writer;
|
|
|
|
}
|
2006-03-28 22:05:23 +00:00
|
|
|
chip->bits_per_word = spi->bits_per_word;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
spi_set_ctldata(spi, chip);
|
|
|
|
|
2010-11-23 01:12:17 +00:00
|
|
|
if (drv_data->ssp_type == CE4100_SSP)
|
|
|
|
return 0;
|
|
|
|
|
2009-04-07 02:00:54 +00:00
|
|
|
return setup_cs(spi, chip, chip_info);
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
2007-02-12 08:52:45 +00:00
|
|
|
static void cleanup(struct spi_device *spi)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2007-02-12 08:52:45 +00:00
|
|
|
struct chip_data *chip = spi_get_ctldata(spi);
|
2010-11-23 01:12:17 +00:00
|
|
|
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2009-05-12 20:19:36 +00:00
|
|
|
if (!chip)
|
|
|
|
return;
|
|
|
|
|
2010-11-23 01:12:17 +00:00
|
|
|
if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
|
2009-04-07 02:00:54 +00:00
|
|
|
gpio_free(chip->gpio_cs);
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
kfree(chip);
|
|
|
|
}
|
|
|
|
|
2013-01-22 10:26:33 +00:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
static struct pxa2xx_spi_master *
|
|
|
|
pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct pxa2xx_spi_master *pdata;
|
|
|
|
struct acpi_device *adev;
|
|
|
|
struct ssp_device *ssp;
|
|
|
|
struct resource *res;
|
|
|
|
int devid;
|
|
|
|
|
|
|
|
if (!ACPI_HANDLE(&pdev->dev) ||
|
|
|
|
acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
|
|
|
|
return NULL;
|
|
|
|
|
2013-06-20 14:44:22 +00:00
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
2014-04-29 08:19:38 +00:00
|
|
|
if (!pdata)
|
2013-01-22 10:26:33 +00:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
ssp = &pdata->ssp;
|
|
|
|
|
|
|
|
ssp->phys_base = res->start;
|
2013-04-08 10:19:33 +00:00
|
|
|
ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(ssp->mmio_base))
|
2013-05-13 10:45:09 +00:00
|
|
|
return NULL;
|
2013-01-22 10:26:33 +00:00
|
|
|
|
|
|
|
ssp->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
ssp->irq = platform_get_irq(pdev, 0);
|
|
|
|
ssp->type = LPSS_SSP;
|
|
|
|
ssp->pdev = pdev;
|
|
|
|
|
|
|
|
ssp->port_id = -1;
|
|
|
|
if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
|
|
|
|
ssp->port_id = devid;
|
|
|
|
|
|
|
|
pdata->num_chipselect = 1;
|
2013-05-13 10:45:10 +00:00
|
|
|
pdata->enable_dma = true;
|
2013-01-22 10:26:33 +00:00
|
|
|
|
|
|
|
return pdata;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
|
|
|
|
{ "INT33C0", 0 },
|
|
|
|
{ "INT33C1", 0 },
|
2013-11-12 10:06:21 +00:00
|
|
|
{ "INT3430", 0 },
|
|
|
|
{ "INT3431", 0 },
|
2013-05-13 10:45:11 +00:00
|
|
|
{ "80860F0E", 0 },
|
2014-08-20 10:57:26 +00:00
|
|
|
{ "8086228E", 0 },
|
2013-01-22 10:26:33 +00:00
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
|
|
|
|
#else
|
|
|
|
static inline struct pxa2xx_spi_master *
|
|
|
|
pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-12-07 16:57:14 +00:00
|
|
|
static int pxa2xx_spi_probe(struct platform_device *pdev)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct pxa2xx_spi_master *platform_info;
|
|
|
|
struct spi_master *master;
|
2008-10-16 05:02:42 +00:00
|
|
|
struct driver_data *drv_data;
|
2007-11-21 10:50:53 +00:00
|
|
|
struct ssp_device *ssp;
|
2008-10-16 05:02:42 +00:00
|
|
|
int status;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2013-01-07 10:44:33 +00:00
|
|
|
platform_info = dev_get_platdata(dev);
|
|
|
|
if (!platform_info) {
|
2013-01-22 10:26:33 +00:00
|
|
|
platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
|
|
|
|
if (!platform_info) {
|
|
|
|
dev_err(&pdev->dev, "missing platform data\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2013-01-07 10:44:33 +00:00
|
|
|
}
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2010-05-05 14:11:15 +00:00
|
|
|
ssp = pxa_ssp_request(pdev->id, pdev->name);
|
2013-01-07 10:44:33 +00:00
|
|
|
if (!ssp)
|
|
|
|
ssp = &platform_info->ssp;
|
|
|
|
|
|
|
|
if (!ssp->mmio_base) {
|
|
|
|
dev_err(&pdev->dev, "failed to get ssp\n");
|
2006-03-08 07:53:24 +00:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate master with space for drv_data and null dma buffer */
|
|
|
|
master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
|
|
|
|
if (!master) {
|
2008-10-16 05:02:42 +00:00
|
|
|
dev_err(&pdev->dev, "cannot alloc spi_master\n");
|
2010-05-05 14:11:15 +00:00
|
|
|
pxa_ssp_free(ssp);
|
2006-03-08 07:53:24 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
drv_data = spi_master_get_devdata(master);
|
|
|
|
drv_data->master = master;
|
|
|
|
drv_data->master_info = platform_info;
|
|
|
|
drv_data->pdev = pdev;
|
2007-11-21 10:50:53 +00:00
|
|
|
drv_data->ssp = ssp;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2010-10-08 16:11:19 +00:00
|
|
|
master->dev.parent = &pdev->dev;
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
2009-06-17 23:26:04 +00:00
|
|
|
/* the spi->mode bits understood by this driver: */
|
2013-01-22 10:26:31 +00:00
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
|
2009-06-17 23:26:04 +00:00
|
|
|
|
2013-01-07 10:44:33 +00:00
|
|
|
master->bus_num = ssp->port_id;
|
2006-03-08 07:53:24 +00:00
|
|
|
master->num_chipselect = platform_info->num_chipselect;
|
2009-04-07 02:00:57 +00:00
|
|
|
master->dma_alignment = DMA_ALIGNMENT;
|
2006-03-08 07:53:24 +00:00
|
|
|
master->cleanup = cleanup;
|
|
|
|
master->setup = setup;
|
2013-01-22 10:26:26 +00:00
|
|
|
master->transfer_one_message = pxa2xx_spi_transfer_one_message;
|
2013-01-22 10:26:30 +00:00
|
|
|
master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
|
2013-07-28 14:35:21 +00:00
|
|
|
master->auto_runtime_pm = true;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2007-11-21 10:50:53 +00:00
|
|
|
drv_data->ssp_type = ssp->type;
|
2013-01-22 10:26:25 +00:00
|
|
|
drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2007-11-21 10:50:53 +00:00
|
|
|
drv_data->ioaddr = ssp->mmio_base;
|
|
|
|
drv_data->ssdr_physical = ssp->phys_base + SSDR;
|
2010-11-23 01:12:17 +00:00
|
|
|
if (pxa25x_ssp_comp(drv_data)) {
|
2013-05-22 02:36:35 +00:00
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
2006-03-08 07:53:24 +00:00
|
|
|
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
|
|
|
|
drv_data->dma_cr1 = 0;
|
|
|
|
drv_data->clear_sr = SSSR_ROR;
|
|
|
|
drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
|
|
|
|
} else {
|
2013-05-22 02:36:35 +00:00
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
2006-03-08 07:53:24 +00:00
|
|
|
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
|
2013-01-22 10:26:29 +00:00
|
|
|
drv_data->dma_cr1 = DEFAULT_DMA_CR1;
|
2006-03-08 07:53:24 +00:00
|
|
|
drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
|
|
|
|
drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
|
|
|
|
}
|
|
|
|
|
2010-11-23 01:12:14 +00:00
|
|
|
status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
|
|
|
|
drv_data);
|
2006-03-08 07:53:24 +00:00
|
|
|
if (status < 0) {
|
2008-10-16 05:02:42 +00:00
|
|
|
dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
|
2006-03-08 07:53:24 +00:00
|
|
|
goto out_error_master_alloc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup DMA if requested */
|
|
|
|
drv_data->tx_channel = -1;
|
|
|
|
drv_data->rx_channel = -1;
|
|
|
|
if (platform_info->enable_dma) {
|
2013-01-22 10:26:28 +00:00
|
|
|
status = pxa2xx_spi_dma_setup(drv_data);
|
|
|
|
if (status) {
|
2013-05-13 10:45:10 +00:00
|
|
|
dev_dbg(dev, "no DMA channels available, using PIO\n");
|
2013-01-22 10:26:28 +00:00
|
|
|
platform_info->enable_dma = false;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable SOC clock */
|
2013-01-22 10:26:27 +00:00
|
|
|
clk_prepare_enable(ssp->clk);
|
|
|
|
|
|
|
|
drv_data->max_clk_rate = clk_get_rate(ssp->clk);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
/* Load default SSP configuration */
|
|
|
|
write_SSCR0(0, drv_data->ioaddr);
|
2008-10-16 05:02:43 +00:00
|
|
|
write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
|
|
|
|
SSCR1_TxTresh(TX_THRESH_DFLT),
|
|
|
|
drv_data->ioaddr);
|
2010-03-16 08:48:01 +00:00
|
|
|
write_SSCR0(SSCR0_SCR(2)
|
2006-03-08 07:53:24 +00:00
|
|
|
| SSCR0_Motorola
|
|
|
|
| SSCR0_DataSize(8),
|
|
|
|
drv_data->ioaddr);
|
2010-11-23 01:12:17 +00:00
|
|
|
if (!pxa25x_ssp_comp(drv_data))
|
2006-03-08 07:53:24 +00:00
|
|
|
write_SSTO(0, drv_data->ioaddr);
|
|
|
|
write_SSPSP(0, drv_data->ioaddr);
|
|
|
|
|
2013-01-22 10:26:32 +00:00
|
|
|
lpss_ssp_setup(drv_data);
|
|
|
|
|
2013-01-22 10:26:26 +00:00
|
|
|
tasklet_init(&drv_data->pump_transfers, pump_transfers,
|
|
|
|
(unsigned long)drv_data);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2014-05-30 16:18:09 +00:00
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
/* Register with the SPI framework */
|
|
|
|
platform_set_drvdata(pdev, drv_data);
|
2013-09-24 04:46:55 +00:00
|
|
|
status = devm_spi_register_master(&pdev->dev, master);
|
2006-03-08 07:53:24 +00:00
|
|
|
if (status != 0) {
|
|
|
|
dev_err(&pdev->dev, "problem registering spi master\n");
|
2013-01-22 10:26:26 +00:00
|
|
|
goto out_error_clock_enabled;
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return status;
|
|
|
|
|
|
|
|
out_error_clock_enabled:
|
2013-01-22 10:26:27 +00:00
|
|
|
clk_disable_unprepare(ssp->clk);
|
2013-01-22 10:26:28 +00:00
|
|
|
pxa2xx_spi_dma_release(drv_data);
|
2007-11-21 10:50:53 +00:00
|
|
|
free_irq(ssp->irq, drv_data);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
out_error_master_alloc:
|
|
|
|
spi_master_put(master);
|
2010-05-05 14:11:15 +00:00
|
|
|
pxa_ssp_free(ssp);
|
2006-03-08 07:53:24 +00:00
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pxa2xx_spi_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct driver_data *drv_data = platform_get_drvdata(pdev);
|
2009-01-06 22:41:45 +00:00
|
|
|
struct ssp_device *ssp;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
if (!drv_data)
|
|
|
|
return 0;
|
2009-01-06 22:41:45 +00:00
|
|
|
ssp = drv_data->ssp;
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2013-01-22 10:26:30 +00:00
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
/* Disable the SSP at the peripheral and SOC level */
|
|
|
|
write_SSCR0(0, drv_data->ioaddr);
|
2013-01-22 10:26:27 +00:00
|
|
|
clk_disable_unprepare(ssp->clk);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
/* Release DMA */
|
2013-01-22 10:26:28 +00:00
|
|
|
if (drv_data->master_info->enable_dma)
|
|
|
|
pxa2xx_spi_dma_release(drv_data);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2013-01-22 10:26:30 +00:00
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
/* Release IRQ */
|
2007-11-21 10:50:53 +00:00
|
|
|
free_irq(ssp->irq, drv_data);
|
|
|
|
|
|
|
|
/* Release SSP */
|
2010-05-05 14:11:15 +00:00
|
|
|
pxa_ssp_free(ssp);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pxa2xx_spi_shutdown(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
int status = 0;
|
|
|
|
|
|
|
|
if ((status = pxa2xx_spi_remove(pdev)) != 0)
|
|
|
|
dev_err(&pdev->dev, "shutdown failed with %d\n", status);
|
|
|
|
}
|
|
|
|
|
2014-01-16 12:50:55 +00:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2009-07-21 14:50:16 +00:00
|
|
|
static int pxa2xx_spi_suspend(struct device *dev)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2009-07-21 14:50:16 +00:00
|
|
|
struct driver_data *drv_data = dev_get_drvdata(dev);
|
2007-11-21 10:50:53 +00:00
|
|
|
struct ssp_device *ssp = drv_data->ssp;
|
2006-03-08 07:53:24 +00:00
|
|
|
int status = 0;
|
|
|
|
|
2013-01-22 10:26:26 +00:00
|
|
|
status = spi_master_suspend(drv_data->master);
|
2006-03-08 07:53:24 +00:00
|
|
|
if (status != 0)
|
|
|
|
return status;
|
|
|
|
write_SSCR0(0, drv_data->ioaddr);
|
2014-11-06 11:08:29 +00:00
|
|
|
|
|
|
|
if (!pm_runtime_suspended(dev))
|
|
|
|
clk_disable_unprepare(ssp->clk);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-07-21 14:50:16 +00:00
|
|
|
static int pxa2xx_spi_resume(struct device *dev)
|
2006-03-08 07:53:24 +00:00
|
|
|
{
|
2009-07-21 14:50:16 +00:00
|
|
|
struct driver_data *drv_data = dev_get_drvdata(dev);
|
2007-11-21 10:50:53 +00:00
|
|
|
struct ssp_device *ssp = drv_data->ssp;
|
2006-03-08 07:53:24 +00:00
|
|
|
int status = 0;
|
|
|
|
|
2013-01-22 10:26:28 +00:00
|
|
|
pxa2xx_spi_dma_resume(drv_data);
|
2009-04-21 19:24:43 +00:00
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
/* Enable the SSP clock */
|
2014-11-06 11:08:29 +00:00
|
|
|
if (!pm_runtime_suspended(dev))
|
|
|
|
clk_prepare_enable(ssp->clk);
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2013-11-28 18:13:11 +00:00
|
|
|
/* Restore LPSS private register bits */
|
|
|
|
lpss_ssp_setup(drv_data);
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
/* Start the queue running */
|
2013-01-22 10:26:26 +00:00
|
|
|
status = spi_master_resume(drv_data->master);
|
2006-03-08 07:53:24 +00:00
|
|
|
if (status != 0) {
|
2009-07-21 14:50:16 +00:00
|
|
|
dev_err(dev, "problem starting queue (%d)\n", status);
|
2006-03-08 07:53:24 +00:00
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2013-01-22 10:26:30 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
|
|
static int pxa2xx_spi_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct driver_data *drv_data = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
clk_disable_unprepare(drv_data->ssp->clk);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pxa2xx_spi_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct driver_data *drv_data = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
clk_prepare_enable(drv_data->ssp->clk);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
2009-07-21 14:50:16 +00:00
|
|
|
|
2009-12-15 02:00:08 +00:00
|
|
|
static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
|
2013-01-22 10:26:30 +00:00
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
|
|
|
|
SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
|
|
|
|
pxa2xx_spi_runtime_resume, NULL)
|
2009-07-21 14:50:16 +00:00
|
|
|
};
|
2006-03-08 07:53:24 +00:00
|
|
|
|
|
|
|
static struct platform_driver driver = {
|
|
|
|
.driver = {
|
2009-07-21 14:50:16 +00:00
|
|
|
.name = "pxa2xx-spi",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.pm = &pxa2xx_spi_pm_ops,
|
2013-01-22 10:26:33 +00:00
|
|
|
.acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
|
2006-03-08 07:53:24 +00:00
|
|
|
},
|
2010-11-19 17:00:11 +00:00
|
|
|
.probe = pxa2xx_spi_probe,
|
2007-10-16 08:27:46 +00:00
|
|
|
.remove = pxa2xx_spi_remove,
|
2006-03-08 07:53:24 +00:00
|
|
|
.shutdown = pxa2xx_spi_shutdown,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init pxa2xx_spi_init(void)
|
|
|
|
{
|
2010-11-19 17:00:11 +00:00
|
|
|
return platform_driver_register(&driver);
|
2006-03-08 07:53:24 +00:00
|
|
|
}
|
2009-09-22 23:46:10 +00:00
|
|
|
subsys_initcall(pxa2xx_spi_init);
|
2006-03-08 07:53:24 +00:00
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static void __exit pxa2xx_spi_exit(void)
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{
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platform_driver_unregister(&driver);
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}
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module_exit(pxa2xx_spi_exit);
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