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52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
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/*
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* Intel Core SoC Power Management Controller Header File
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*
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* Copyright (c) 2016, Intel Corporation.
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* All Rights Reserved.
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*
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* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
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* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef PMC_CORE_H
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#define PMC_CORE_H
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/* Sunrise Point Power Management Controller PCI Device ID */
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#define SPT_PMC_PCI_DEVICE_ID 0x9d21
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#define SPT_PMC_BASE_ADDR_OFFSET 0x48
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#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
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#define SPT_PMC_MMIO_REG_LEN 0x100
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#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64
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/**
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* struct pmc_dev - pmc device structure
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* @base_addr: comtains pmc base address
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* @regbase: pointer to io-remapped memory location
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* @dbgfs_dir: path to debug fs interface
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* @feature_available: flag to indicate whether
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* the feature is available
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* on a particular platform or not.
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*
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* pmc_dev contains info about power management controller device.
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*/
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struct pmc_dev {
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u32 base_addr;
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void __iomem *regbase;
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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struct dentry *dbgfs_dir;
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#endif /* CONFIG_DEBUG_FS */
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bool has_slp_s0_res;
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};
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#endif /* PMC_CORE_H */
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