2022-06-07 14:11:13 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-02-02 23:43:57 +00:00
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/*
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* Motorola CPCAP PMIC regulator driver
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*
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* Based on cpcap-regulator.c from Motorola Linux kernel tree
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* Copyright (C) 2009-2011 Motorola, Inc.
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*
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* Rewritten for mainline kernel to use device tree and regmap
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* Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/of_regulator.h>
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#include <linux/mfd/motorola-cpcap.h>
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/*
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* Resource assignment register bits. These seem to control the state
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* idle modes adn are used at least for omap4.
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*/
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/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
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#define CPCAP_BIT_VSDIO_SEL BIT(15)
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#define CPCAP_BIT_VDIG_SEL BIT(14)
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#define CPCAP_BIT_VCAM_SEL BIT(13)
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#define CPCAP_BIT_SW6_SEL BIT(12)
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#define CPCAP_BIT_SW5_SEL BIT(11)
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#define CPCAP_BIT_SW4_SEL BIT(10)
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#define CPCAP_BIT_SW3_SEL BIT(9)
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#define CPCAP_BIT_SW2_SEL BIT(8)
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#define CPCAP_BIT_SW1_SEL BIT(7)
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/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
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#define CPCAP_BIT_VUSBINT2_SEL BIT(15)
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#define CPCAP_BIT_VUSBINT1_SEL BIT(14)
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#define CPCAP_BIT_VVIB_SEL BIT(13)
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#define CPCAP_BIT_VWLAN1_SEL BIT(12)
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#define CPCAP_BIT_VRF1_SEL BIT(11)
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#define CPCAP_BIT_VHVIO_SEL BIT(10)
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#define CPCAP_BIT_VDAC_SEL BIT(9)
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#define CPCAP_BIT_VUSB_SEL BIT(8)
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#define CPCAP_BIT_VSIM_SEL BIT(7)
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#define CPCAP_BIT_VRFREF_SEL BIT(6)
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#define CPCAP_BIT_VPLL_SEL BIT(5)
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#define CPCAP_BIT_VFUSE_SEL BIT(4)
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#define CPCAP_BIT_VCSI_SEL BIT(3)
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#define CPCAP_BIT_SPARE_14_2 BIT(2)
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#define CPCAP_BIT_VWLAN2_SEL BIT(1)
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#define CPCAP_BIT_VRF2_SEL BIT(0)
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/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
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#define CPCAP_BIT_VAUDIO_SEL BIT(0)
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/*
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* Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic,
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* and not limited to audio regulator. Let's use the Motorola kernel
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* naming for now until we have a better understanding of the other
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* enable register bits. No idea why BIT(3) is not defined.
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*/
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#define CPCAP_BIT_AUDIO_LOW_PWR BIT(6)
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#define CPCAP_BIT_AUD_LOWPWR_SPEED BIT(5)
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#define CPCAP_BIT_VAUDIOPRISTBY BIT(4)
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#define CPCAP_BIT_VAUDIO_MODE1 BIT(2)
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#define CPCAP_BIT_VAUDIO_MODE0 BIT(1)
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#define CPCAP_BIT_V_AUDIO_EN BIT(0)
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2017-07-10 14:33:39 +00:00
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#define CPCAP_BIT_AUDIO_NORMAL_MODE 0x00
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2017-02-02 23:43:57 +00:00
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/*
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* Off mode configuration bit. Used currently only by SW5 on omap4. There's
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* the following comment in Motorola Linux kernel tree for it:
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*
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* When set in the regulator mode, the regulator assignment will be changed
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* to secondary when the regulator is disabled. The mode will be set back to
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* primary when the regulator is turned on.
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*/
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#define CPCAP_REG_OFF_MODE_SEC BIT(15)
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2020-06-25 16:36:12 +00:00
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/*
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2019-06-07 11:26:40 +00:00
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* SoC specific configuration for CPCAP regulator. There are at least three
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2017-02-02 23:43:57 +00:00
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* different SoCs each with their own parameters: omap3, omap4 and tegra2.
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*
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* The assign_reg and assign_mask seem to allow toggling between primary
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* and secondary mode that at least omap4 uses for off mode.
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*/
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struct cpcap_regulator {
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struct regulator_desc rdesc;
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const u16 assign_reg;
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const u16 assign_mask;
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};
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#define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl, \
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2019-02-26 05:52:29 +00:00
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mode_mask, volt_mask, mode_val, off_val, \
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volt_trans_time) { \
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2017-02-02 23:43:57 +00:00
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.rdesc = { \
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.name = #_ID, \
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.of_match = of_match_ptr(#_ID), \
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.ops = &cpcap_regulator_ops, \
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.regulators_node = of_match_ptr("regulators"), \
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.type = REGULATOR_VOLTAGE, \
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.id = CPCAP_##_ID, \
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.owner = THIS_MODULE, \
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.n_voltages = ARRAY_SIZE(val_tbl), \
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.volt_table = (val_tbl), \
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.vsel_reg = (reg), \
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.vsel_mask = (volt_mask), \
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.enable_reg = (reg), \
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.enable_mask = (mode_mask), \
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.enable_val = (mode_val), \
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.disable_val = (off_val), \
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.ramp_delay = (volt_trans_time), \
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2017-07-10 14:33:40 +00:00
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.of_map_mode = cpcap_map_mode, \
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2017-02-02 23:43:57 +00:00
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}, \
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.assign_reg = (assignment_reg), \
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.assign_mask = (assignment_mask), \
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}
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struct cpcap_ddata {
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struct regmap *reg;
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struct device *dev;
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const struct cpcap_regulator *soc;
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};
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enum cpcap_regulator_id {
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CPCAP_SW1,
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CPCAP_SW2,
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CPCAP_SW3,
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CPCAP_SW4,
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CPCAP_SW5,
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CPCAP_SW6,
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CPCAP_VCAM,
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CPCAP_VCSI,
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CPCAP_VDAC,
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CPCAP_VDIG,
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CPCAP_VFUSE,
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CPCAP_VHVIO,
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CPCAP_VSDIO,
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CPCAP_VPLL,
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CPCAP_VRF1,
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CPCAP_VRF2,
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CPCAP_VRFREF,
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CPCAP_VWLAN1,
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CPCAP_VWLAN2,
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CPCAP_VSIM,
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CPCAP_VSIMCARD,
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CPCAP_VVIB,
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CPCAP_VUSB,
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CPCAP_VAUDIO,
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CPCAP_NR_REGULATORS,
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};
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/*
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* We need to also configure regulator idle mode for SoC off mode if
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* CPCAP_REG_OFF_MODE_SEC is set.
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*/
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static int cpcap_regulator_enable(struct regulator_dev *rdev)
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{
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struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
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2020-06-25 16:36:11 +00:00
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int error;
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2017-02-02 23:43:57 +00:00
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error = regulator_enable_regmap(rdev);
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if (error)
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return error;
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if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
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error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
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regulator->assign_mask,
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regulator->assign_mask);
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if (error)
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2020-06-25 16:36:11 +00:00
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regulator_disable_regmap(rdev);
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2017-02-02 23:43:57 +00:00
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}
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return error;
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}
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/*
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* We need to also configure regulator idle mode for SoC off mode if
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* CPCAP_REG_OFF_MODE_SEC is set.
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*/
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static int cpcap_regulator_disable(struct regulator_dev *rdev)
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{
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struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
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2020-06-25 16:36:11 +00:00
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int error;
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2017-02-02 23:43:57 +00:00
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if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
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error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
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regulator->assign_mask, 0);
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if (error)
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return error;
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}
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error = regulator_disable_regmap(rdev);
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if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) {
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2020-06-25 16:36:11 +00:00
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regmap_update_bits(rdev->regmap, regulator->assign_reg,
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regulator->assign_mask,
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regulator->assign_mask);
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2017-02-02 23:43:57 +00:00
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}
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return error;
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}
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2017-07-10 14:33:40 +00:00
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static unsigned int cpcap_map_mode(unsigned int mode)
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{
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switch (mode) {
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case CPCAP_BIT_AUDIO_NORMAL_MODE:
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return REGULATOR_MODE_NORMAL;
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case CPCAP_BIT_AUDIO_LOW_PWR:
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return REGULATOR_MODE_STANDBY;
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default:
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2018-04-18 15:54:18 +00:00
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return REGULATOR_MODE_INVALID;
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2017-07-10 14:33:40 +00:00
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}
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}
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2017-02-02 23:43:57 +00:00
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static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev)
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{
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int value;
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regmap_read(rdev->regmap, rdev->desc->enable_reg, &value);
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2017-07-10 14:33:39 +00:00
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if (value & CPCAP_BIT_AUDIO_LOW_PWR)
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2017-02-02 23:43:57 +00:00
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return REGULATOR_MODE_STANDBY;
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return REGULATOR_MODE_NORMAL;
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}
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static int cpcap_regulator_set_mode(struct regulator_dev *rdev,
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unsigned int mode)
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{
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int value;
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switch (mode) {
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case REGULATOR_MODE_NORMAL:
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2017-07-10 14:33:39 +00:00
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value = CPCAP_BIT_AUDIO_NORMAL_MODE;
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2017-02-02 23:43:57 +00:00
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break;
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case REGULATOR_MODE_STANDBY:
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2017-07-10 14:33:39 +00:00
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value = CPCAP_BIT_AUDIO_LOW_PWR;
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2017-02-02 23:43:57 +00:00
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break;
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default:
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return -EINVAL;
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}
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return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
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CPCAP_BIT_AUDIO_LOW_PWR, value);
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}
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2020-06-17 22:32:44 +00:00
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static const struct regulator_ops cpcap_regulator_ops = {
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2017-02-02 23:43:57 +00:00
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.enable = cpcap_regulator_enable,
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.disable = cpcap_regulator_disable,
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.is_enabled = regulator_is_enabled_regmap,
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.list_voltage = regulator_list_voltage_table,
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.map_voltage = regulator_map_voltage_iterate,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_mode = cpcap_regulator_get_mode,
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.set_mode = cpcap_regulator_set_mode,
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};
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static const unsigned int unknown_val_tbl[] = { 0, };
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2018-07-24 13:25:40 +00:00
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static const unsigned int sw2_sw4_val_tbl[] = { 612500, 625000, 637500,
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650000, 662500, 675000,
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687500, 700000, 712500,
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725000, 737500, 750000,
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762500, 775000, 787500,
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800000, 812500, 825000,
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837500, 850000, 862500,
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875000, 887500, 900000,
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912500, 925000, 937500,
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950000, 962500, 975000,
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987500, 1000000, 1012500,
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1025000, 1037500, 1050000,
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1062500, 1075000, 1087500,
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1100000, 1112500, 1125000,
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1137500, 1150000, 1162500,
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1175000, 1187500, 1200000,
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1212500, 1225000, 1237500,
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1250000, 1262500, 1275000,
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1287500, 1300000, 1312500,
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1325000, 1337500, 1350000,
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1362500, 1375000, 1387500,
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1400000, 1412500, 1425000,
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1437500, 1450000, 1462500, };
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2017-02-02 23:43:57 +00:00
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static const unsigned int sw5_val_tbl[] = { 0, 5050000, };
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static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000,
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2900000, };
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static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, };
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static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000,
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2500000,};
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static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000,
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1875000, };
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static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000,
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1800000, 1900000, 2000000,
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2100000, 2200000, 2300000,
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2400000, 2500000, 2600000,
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2700000, 3150000, };
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static const unsigned int vhvio_val_tbl[] = { 2775000, };
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static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000,
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2600000, 2700000, 2800000,
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2900000, 3000000, };
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static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000,
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1800000, };
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/* Quirk: 2775000 is before 2500000 for vrf1 regulator */
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static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, };
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static const unsigned int vrf2_val_tbl[] = { 0, 2775000, };
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static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, };
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static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, };
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static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000,
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3300000, };
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static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, };
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static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, };
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static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000,
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3000000, };
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static const unsigned int vusb_val_tbl[] = { 0, 3300000, };
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static const unsigned int vaudio_val_tbl[] = { 0, 2775000, };
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2020-06-25 16:36:12 +00:00
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/*
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2017-02-02 23:43:57 +00:00
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* SoC specific configuration for omap4. The data below is comes from Motorola
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* Linux kernel tree. It's basically the values of cpcap_regltr_data,
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* cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see
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* CPCAP_REG macro above.
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*
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* SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and
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* VSIMCARD have a shared resource assignment bit.
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*/
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2019-02-26 05:52:30 +00:00
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static const struct cpcap_regulator omap4_regulators[] = {
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW1_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW2_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW3_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW4_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW5_SEL, sw5_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x28, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW6_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x87, 0x30, 0x3, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x47, 0x10, 0x43, 0x41, 350),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x87, 0x30, 0x3, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x87, 0x30, 0x82, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x80, 0xf, 0x80, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x17, 0, 0, 0x12, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x87, 0x38, 0x82, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x43, 0x18, 0x2, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
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2019-02-26 05:52:29 +00:00
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0xac, 0x2, 0x4, 0, 10),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x23, 0x8, 0, 0, 10),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x23, 0x8, 0, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x47, 0x10, 0, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x20c, 0xc0, 0x20c, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
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0xffff, vsim_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x23, 0x8, 0x3, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
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0xffff, vsimcard_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x1e80, 0x8, 0x1e00, 0, 420),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x1, 0xc, 0x1, 0, 500),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x11c, 0x40, 0xc, 0, 0),
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2017-02-02 23:43:57 +00:00
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CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
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CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x16, 0x1, 0x4, 0, 0),
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2017-02-02 23:43:57 +00:00
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{ /* sentinel */ },
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};
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2019-02-26 05:52:30 +00:00
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static const struct cpcap_regulator xoom_regulators[] = {
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW1_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW2_SEL, sw2_sw4_val_tbl,
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2019-02-26 05:52:29 +00:00
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0xf00, 0x7f, 0x800, 0, 120),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW3_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW4_SEL, sw2_sw4_val_tbl,
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2019-02-26 05:52:29 +00:00
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0xf00, 0x7f, 0x900, 0, 100),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW5_SEL, sw5_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x2a, 0, 0x22, 0, 0),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_SW6_SEL, unknown_val_tbl,
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2019-02-26 05:52:29 +00:00
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0, 0, 0, 0, 0),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x87, 0x30, 0x7, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
|
2019-02-26 05:52:29 +00:00
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0x47, 0x10, 0x7, 0, 350),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
|
2019-02-26 05:52:29 +00:00
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0x87, 0x30, 0x3, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
|
2019-02-26 05:52:29 +00:00
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0x87, 0x30, 0x5, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x80, 0xf, 0x80, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x17, 0, 0x2, 0, 0),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
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CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x87, 0x38, 0x2, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x43, 0x18, 0x1, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
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2019-02-26 05:52:29 +00:00
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0xac, 0x2, 0xc, 0, 10),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x23, 0x8, 0x3, 0, 10),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
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2019-02-26 05:52:29 +00:00
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0x23, 0x8, 0x3, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
|
2019-02-26 05:52:29 +00:00
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0x47, 0x10, 0x5, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
|
2019-02-26 05:52:29 +00:00
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0x20c, 0xc0, 0x8, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
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0xffff, vsim_val_tbl,
|
2019-02-26 05:52:29 +00:00
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0x23, 0x8, 0x3, 0, 420),
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2018-07-24 13:25:41 +00:00
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CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
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0xffff, vsimcard_val_tbl,
|
2019-02-26 05:52:29 +00:00
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0x1e80, 0x8, 0x1e00, 0, 420),
|
2018-07-24 13:25:41 +00:00
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CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
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CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
|
2019-02-26 05:52:29 +00:00
|
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0x1, 0xc, 0, 0x1, 500),
|
2018-07-24 13:25:41 +00:00
|
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CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
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|
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CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
|
2019-02-26 05:52:29 +00:00
|
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0x11c, 0x40, 0xc, 0, 0),
|
2018-07-24 13:25:41 +00:00
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CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
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CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
|
2019-02-26 05:52:29 +00:00
|
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0x16, 0x1, 0x4, 0, 0),
|
2018-07-24 13:25:41 +00:00
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{ /* sentinel */ },
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};
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|
2017-02-02 23:43:57 +00:00
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static const struct of_device_id cpcap_regulator_id_table[] = {
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{
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.compatible = "motorola,cpcap-regulator",
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},
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{
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.compatible = "motorola,mapphone-cpcap-regulator",
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.data = omap4_regulators,
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},
|
2018-07-24 13:25:41 +00:00
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{
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.compatible = "motorola,xoom-cpcap-regulator",
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.data = xoom_regulators,
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},
|
2017-02-02 23:43:57 +00:00
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{},
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};
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MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table);
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static int cpcap_regulator_probe(struct platform_device *pdev)
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{
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struct cpcap_ddata *ddata;
|
2019-03-16 14:35:58 +00:00
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const struct cpcap_regulator *match_data;
|
2017-02-02 23:43:57 +00:00
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struct regulator_config config;
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int i;
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|
2019-03-16 14:35:58 +00:00
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match_data = of_device_get_match_data(&pdev->dev);
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if (!match_data) {
|
2017-02-02 23:43:57 +00:00
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dev_err(&pdev->dev, "no configuration data found\n");
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return -ENODEV;
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}
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ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
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if (!ddata->reg)
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|
return -ENODEV;
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ddata->dev = &pdev->dev;
|
2019-03-16 14:35:58 +00:00
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ddata->soc = match_data;
|
2017-02-02 23:43:57 +00:00
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|
platform_set_drvdata(pdev, ddata);
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memset(&config, 0, sizeof(config));
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config.dev = &pdev->dev;
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config.regmap = ddata->reg;
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|
|
for (i = 0; i < CPCAP_NR_REGULATORS; i++) {
|
|
|
|
const struct cpcap_regulator *regulator = &ddata->soc[i];
|
|
|
|
struct regulator_dev *rdev;
|
|
|
|
|
|
|
|
if (!regulator->rdesc.name)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (regulator->rdesc.volt_table == unknown_val_tbl)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
config.driver_data = (void *)regulator;
|
|
|
|
rdev = devm_regulator_register(&pdev->dev,
|
|
|
|
®ulator->rdesc,
|
|
|
|
&config);
|
|
|
|
if (IS_ERR(rdev)) {
|
|
|
|
dev_err(&pdev->dev, "failed to register regulator %s\n",
|
|
|
|
regulator->rdesc.name);
|
|
|
|
|
|
|
|
return PTR_ERR(rdev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver cpcap_regulator_driver = {
|
|
|
|
.probe = cpcap_regulator_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "cpcap-regulator",
|
regulator: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in 4.14
Probing of regulators can be a slow operation and can contribute to
slower boot times. This is especially true if a regulator is turned on
at probe time (with regulator-boot-on or regulator-always-on) and the
regulator requires delays (off-on-time, ramp time, etc).
While the overall kernel is not ready to switch to async probe by
default, as per the discussion on the mailing lists [1] it is believed
that the regulator subsystem is in good shape and we can move
regulator drivers over wholesale. There is no way to just magically
opt in all regulators (regulators are just normal drivers like
platform_driver), so we set PROBE_PREFER_ASYNCHRONOUS for all
regulators found in 'drivers/regulator' individually.
Given the number of drivers touched and the impossibility to test this
ahead of time, it wouldn't be shocking at all if this caused a
regression for someone. If there is a regression caused by this patch,
it's likely to be one of the cases talked about in [1]. As a "quick
fix", drivers involved in the regression could be fixed by changing
them to PROBE_FORCE_SYNCHRONOUS. That being said, the correct fix
would be to directly fix the problem that caused the issue with async
probe.
The approach here follows a similar approach that was used for the mmc
subsystem several years ago [2]. In fact, I ran nearly the same python
script to auto-generate the changes. The only thing I changed was to
search for "i2c_driver", "spmi_driver", and "spi_driver" in addition
to "platform_driver".
[1] https://lore.kernel.org/r/06db017f-e985-4434-8d1d-02ca2100cca0@sirena.org.uk
[2] https://lore.kernel.org/r/20200903232441.2694866-1-dianders@chromium.org/
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20230316125351.1.I2a4677392a38db5758dee0788b2cea5872562a82@changeid
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-16 19:54:38 +00:00
|
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
2017-02-02 23:43:57 +00:00
|
|
|
.of_match_table = of_match_ptr(cpcap_regulator_id_table),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(cpcap_regulator_driver);
|
|
|
|
|
|
|
|
MODULE_ALIAS("platform:cpcap-regulator");
|
|
|
|
MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
|
|
|
|
MODULE_DESCRIPTION("CPCAP regulator driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|