2020-11-30 11:23:29 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 NXP
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* Copyright (C) 2019 Boundary Devices
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* Copyright (C) 2020 Amarula Solutions(India)
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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/* registers */
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#define PF8X00_DEVICEID 0x00
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#define PF8X00_REVID 0x01
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#define PF8X00_EMREV 0x02
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#define PF8X00_PROGID 0x03
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#define PF8X00_IMS_INT 0x04
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#define PF8X00_IMS_THERM 0x07
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#define PF8X00_SW_MODE_INT 0x0a
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#define PF8X00_SW_MODE_MASK 0x0b
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#define PF8X00_IMS_SW_ILIM 0x12
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#define PF8X00_IMS_LDO_ILIM 0x15
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#define PF8X00_IMS_SW_UV 0x18
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#define PF8X00_IMS_SW_OV 0x1b
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#define PF8X00_IMS_LDO_UV 0x1e
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#define PF8X00_IMS_LDO_OV 0x21
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#define PF8X00_IMS_PWRON 0x24
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#define PF8X00_SYS_INT 0x27
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#define PF8X00_HARD_FAULT 0x29
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#define PF8X00_FSOB_FLAGS 0x2a
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#define PF8X00_FSOB_SELECT 0x2b
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#define PF8X00_ABIST_OV1 0x2c
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#define PF8X00_ABIST_OV2 0x2d
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#define PF8X00_ABIST_UV1 0x2e
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#define PF8X00_ABIST_UV2 0x2f
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#define PF8X00_TEST_FLAGS 0x30
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#define PF8X00_ABIST_RUN 0x31
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#define PF8X00_RANDOM_GEN 0x33
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#define PF8X00_RANDOM_CHK 0x34
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#define PF8X00_VMONEN1 0x35
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#define PF8X00_VMONEN2 0x36
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#define PF8X00_CTRL1 0x37
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#define PF8X00_CTRL2 0x38
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#define PF8X00_CTRL3 0x39
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#define PF8X00_PWRUP_CTRL 0x3a
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#define PF8X00_RESETBMCU 0x3c
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#define PF8X00_PGOOD 0x3d
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#define PF8X00_PWRDN_DLY1 0x3e
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#define PF8X00_PWRDN_DLY2 0x3f
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#define PF8X00_FREQ_CTRL 0x40
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#define PF8X00_COINCELL_CTRL 0x41
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#define PF8X00_PWRON 0x42
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#define PF8X00_WD_CONFIG 0x43
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#define PF8X00_WD_CLEAR 0x44
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#define PF8X00_WD_EXPIRE 0x45
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#define PF8X00_WD_COUNTER 0x46
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#define PF8X00_FAULT_COUNTER 0x47
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#define PF8X00_FSAFE_COUNTER 0x48
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#define PF8X00_FAULT_TIMER 0x49
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#define PF8X00_AMUX 0x4a
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#define PF8X00_SW1_CONFIG1 0x4d
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#define PF8X00_LDO1_CONFIG1 0x85
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#define PF8X00_VSNVS_CONFIG1 0x9d
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#define PF8X00_PAGE_SELECT 0x9f
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/* regulators */
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enum pf8x00_regulators {
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PF8X00_LDO1,
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PF8X00_LDO2,
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PF8X00_LDO3,
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PF8X00_LDO4,
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PF8X00_BUCK1,
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PF8X00_BUCK2,
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PF8X00_BUCK3,
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PF8X00_BUCK4,
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PF8X00_BUCK5,
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PF8X00_BUCK6,
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PF8X00_BUCK7,
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PF8X00_VSNVS,
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PF8X00_MAX_REGULATORS,
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};
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enum pf8x00_buck_states {
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SW_CONFIG1,
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SW_CONFIG2,
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SW_PWRUP,
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SW_MODE1,
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SW_RUN_VOLT,
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SW_STBY_VOLT,
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};
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#define PF8X00_SW_BASE(i) (8 * (i - PF8X00_BUCK1) + PF8X00_SW1_CONFIG1)
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enum pf8x00_ldo_states {
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LDO_CONFIG1,
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LDO_CONFIG2,
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LDO_PWRUP,
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LDO_RUN_VOLT,
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LDO_STBY_VOLT,
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};
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#define PF8X00_LDO_BASE(i) (6 * (i - PF8X00_LDO1) + PF8X00_LDO1_CONFIG1)
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enum swxilim_bits {
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SWXILIM_2100_MA,
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SWXILIM_2600_MA,
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SWXILIM_3000_MA,
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SWXILIM_4500_MA,
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};
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#define PF8X00_SWXILIM_SHIFT 3
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#define PF8X00_SWXILIM_MASK GENMASK(4, 3)
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#define PF8X00_SWXPHASE_MASK GENMASK(2, 0)
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#define PF8X00_SWXPHASE_SHIFT 7
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enum pf8x00_devid {
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PF8100 = 0x0,
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PF8121A = BIT(1),
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PF8200 = BIT(3),
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};
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#define PF8X00_FAM BIT(6)
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#define PF8X00_DEVICE_FAM_MASK GENMASK(7, 4)
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#define PF8X00_DEVICE_ID_MASK GENMASK(3, 0)
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2021-01-17 20:49:17 +00:00
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struct pf8x00_regulator_data {
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2020-11-30 11:23:29 +00:00
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struct regulator_desc desc;
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2021-01-17 20:49:17 +00:00
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unsigned int suspend_enable_reg;
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unsigned int suspend_enable_mask;
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unsigned int suspend_voltage_reg;
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unsigned int suspend_voltage_cache;
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2020-11-30 11:23:29 +00:00
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};
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struct pf8x00_chip {
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struct regmap *regmap;
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struct device *dev;
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};
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static const struct regmap_config pf8x00_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = PF8X00_PAGE_SELECT,
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.cache_type = REGCACHE_RBTREE,
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};
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/* VLDOx output: 1.5V to 5.0V */
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static const int pf8x00_ldo_voltages[] = {
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1500000, 1600000, 1800000, 1850000, 2150000, 2500000, 2800000, 3000000,
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3100000, 3150000, 3200000, 3300000, 3350000, 1650000, 1700000, 5000000,
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};
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2021-01-14 17:47:12 +00:00
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/* Output: 2.1A to 4.5A */
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static const unsigned int pf8x00_sw_current_table[] = {
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2100000, 2600000, 3000000, 4500000,
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};
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2020-11-30 11:23:29 +00:00
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/* Output: 0.4V to 1.8V */
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2021-01-14 17:47:13 +00:00
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#define PF8XOO_SW1_6_VOLTAGE_NUM 0xB2
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static const struct linear_range pf8x00_sw1_to_6_voltages[] = {
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REGULATOR_LINEAR_RANGE(400000, 0x00, 0xB0, 6250),
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REGULATOR_LINEAR_RANGE(1800000, 0xB1, 0xB1, 0),
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2020-11-30 11:23:29 +00:00
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};
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/* Output: 1.0V to 4.1V */
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static const int pf8x00_sw7_voltages[] = {
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1000000, 1100000, 1200000, 1250000, 1300000, 1350000, 1500000, 1600000,
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1800000, 1850000, 2000000, 2100000, 2150000, 2250000, 2300000, 2400000,
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2500000, 2800000, 3150000, 3200000, 3250000, 3300000, 3350000, 3400000,
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3500000, 3800000, 4000000, 4100000, 4100000, 4100000, 4100000, 4100000,
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};
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/* Output: 1.8V, 3.0V, or 3.3V */
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static const int pf8x00_vsnvs_voltages[] = {
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0, 1800000, 3000000, 3300000,
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};
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2021-01-14 17:47:12 +00:00
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static void swxilim_select(struct pf8x00_chip *chip, int id, int ilim)
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2020-11-30 11:23:29 +00:00
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{
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u8 ilim_sel;
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2021-01-14 17:47:12 +00:00
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u8 reg = PF8X00_SW_BASE(id) + SW_CONFIG2;
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2020-11-30 11:23:29 +00:00
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switch (ilim) {
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case 2100:
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ilim_sel = SWXILIM_2100_MA;
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break;
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case 2600:
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ilim_sel = SWXILIM_2600_MA;
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break;
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case 3000:
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ilim_sel = SWXILIM_3000_MA;
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break;
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case 4500:
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ilim_sel = SWXILIM_4500_MA;
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break;
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default:
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ilim_sel = SWXILIM_2100_MA;
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break;
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}
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2021-01-14 17:47:12 +00:00
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regmap_update_bits(chip->regmap, reg,
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PF8X00_SWXILIM_MASK,
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ilim_sel << PF8X00_SWXILIM_SHIFT);
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2020-11-30 11:23:29 +00:00
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}
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2021-01-14 17:47:12 +00:00
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static void handle_ilim_property(struct device_node *np,
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2020-11-30 11:23:29 +00:00
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const struct regulator_desc *desc,
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struct regulator_config *config)
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{
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struct pf8x00_chip *chip = config->driver_data;
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2021-01-14 17:47:12 +00:00
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int ret;
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int val;
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if ((desc->id >= PF8X00_BUCK1) && (desc->id <= PF8X00_BUCK7)) {
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ret = of_property_read_u32(np, "nxp,ilim-ma", &val);
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if (ret) {
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dev_dbg(chip->dev, "unspecified ilim for BUCK%d, use value stored in OTP\n",
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desc->id - PF8X00_LDO4);
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return;
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}
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dev_warn(chip->dev, "nxp,ilim-ma is deprecated, please use regulator-max-microamp\n");
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swxilim_select(chip, desc->id, val);
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} else
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dev_warn(chip->dev, "nxp,ilim-ma used with incorrect regulator (%d)\n", desc->id);
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2020-11-30 11:23:29 +00:00
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}
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2021-01-14 17:47:14 +00:00
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static void handle_shift_property(struct device_node *np,
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2020-11-30 11:23:29 +00:00
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const struct regulator_desc *desc,
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struct regulator_config *config)
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{
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2021-01-14 17:47:14 +00:00
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unsigned char id = desc->id - PF8X00_LDO4;
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unsigned char reg = PF8X00_SW_BASE(id) + SW_CONFIG2;
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2020-11-30 11:23:29 +00:00
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struct pf8x00_chip *chip = config->driver_data;
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2021-01-14 17:47:14 +00:00
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2020-11-30 11:23:29 +00:00
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int phase;
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int val;
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int ret;
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2021-01-14 17:47:14 +00:00
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if ((desc->id >= PF8X00_BUCK1) && (desc->id <= PF8X00_BUCK7)) {
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ret = of_property_read_u32(np, "nxp,phase-shift", &val);
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if (ret) {
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dev_dbg(chip->dev,
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"unspecified phase-shift for BUCK%d, using OTP configuration\n",
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id);
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return;
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}
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2020-11-30 11:23:29 +00:00
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2021-01-14 17:47:14 +00:00
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if (val < 0 || val > 315 || val % 45 != 0) {
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dev_warn(config->dev,
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"invalid phase_shift %d for BUCK%d, using OTP configuration\n",
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val, id);
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return;
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}
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2020-11-30 11:23:29 +00:00
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2021-01-14 17:47:14 +00:00
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phase = val / 45;
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2020-11-30 11:23:29 +00:00
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2021-01-14 17:47:14 +00:00
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if (phase >= 1)
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phase -= 1;
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else
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phase = PF8X00_SWXPHASE_SHIFT;
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regmap_update_bits(chip->regmap, reg,
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PF8X00_SWXPHASE_MASK,
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phase);
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} else
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dev_warn(chip->dev, "nxp,phase-shift used with incorrect regulator (%d)\n", id);
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}
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static int pf8x00_of_parse_cb(struct device_node *np,
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const struct regulator_desc *desc,
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struct regulator_config *config)
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{
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2020-11-30 11:23:29 +00:00
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2021-01-14 17:47:14 +00:00
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handle_ilim_property(np, desc, config);
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handle_shift_property(np, desc, config);
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2020-11-30 11:23:29 +00:00
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return 0;
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}
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2021-01-17 20:49:17 +00:00
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static int pf8x00_suspend_enable(struct regulator_dev *rdev)
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{
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struct pf8x00_regulator_data *regl = rdev_get_drvdata(rdev);
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struct regmap *rmap = rdev_get_regmap(rdev);
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return regmap_update_bits(rmap, regl->suspend_enable_reg,
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regl->suspend_enable_mask,
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regl->suspend_enable_mask);
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}
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static int pf8x00_suspend_disable(struct regulator_dev *rdev)
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{
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struct pf8x00_regulator_data *regl = rdev_get_drvdata(rdev);
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struct regmap *rmap = rdev_get_regmap(rdev);
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return regmap_update_bits(rmap, regl->suspend_enable_reg,
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regl->suspend_enable_mask, 0);
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}
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static int pf8x00_set_suspend_voltage(struct regulator_dev *rdev, int uV)
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{
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struct pf8x00_regulator_data *regl = rdev_get_drvdata(rdev);
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int ret;
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if (regl->suspend_voltage_cache == uV)
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return 0;
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ret = regulator_map_voltage_iterate(rdev, uV, uV);
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if (ret < 0) {
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dev_err(rdev_get_dev(rdev), "failed to map %i uV\n", uV);
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return ret;
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2020-11-30 11:23:29 +00:00
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}
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2021-01-17 20:49:17 +00:00
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dev_dbg(rdev_get_dev(rdev), "uV: %i, reg: 0x%x, msk: 0x%x, val: 0x%x\n",
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uV, regl->suspend_voltage_reg, regl->desc.vsel_mask, ret);
|
|
|
|
ret = regmap_update_bits(rdev->regmap, regl->suspend_voltage_reg,
|
|
|
|
regl->desc.vsel_mask, ret);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(rdev_get_dev(rdev), "failed to set %i uV\n", uV);
|
|
|
|
return ret;
|
2020-11-30 11:23:29 +00:00
|
|
|
}
|
|
|
|
|
2021-01-17 20:49:17 +00:00
|
|
|
regl->suspend_voltage_cache = uV;
|
2020-11-30 11:23:29 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct regulator_ops pf8x00_ldo_ops = {
|
|
|
|
.enable = regulator_enable_regmap,
|
|
|
|
.disable = regulator_disable_regmap,
|
|
|
|
.is_enabled = regulator_is_enabled_regmap,
|
|
|
|
.list_voltage = regulator_list_voltage_table,
|
|
|
|
.set_voltage_sel = regulator_set_voltage_sel_regmap,
|
|
|
|
.get_voltage_sel = regulator_get_voltage_sel_regmap,
|
2021-01-17 20:49:17 +00:00
|
|
|
.set_suspend_enable = pf8x00_suspend_enable,
|
|
|
|
.set_suspend_disable = pf8x00_suspend_disable,
|
|
|
|
.set_suspend_voltage = pf8x00_set_suspend_voltage,
|
2020-11-30 11:23:29 +00:00
|
|
|
};
|
|
|
|
|
2021-01-14 17:47:13 +00:00
|
|
|
|
|
|
|
static const struct regulator_ops pf8x00_buck1_6_ops = {
|
|
|
|
.enable = regulator_enable_regmap,
|
|
|
|
.disable = regulator_disable_regmap,
|
|
|
|
.is_enabled = regulator_is_enabled_regmap,
|
|
|
|
.list_voltage = regulator_list_voltage_linear_range,
|
|
|
|
.set_voltage_sel = regulator_set_voltage_sel_regmap,
|
|
|
|
.get_voltage_sel = regulator_get_voltage_sel_regmap,
|
|
|
|
.get_current_limit = regulator_get_current_limit_regmap,
|
|
|
|
.set_current_limit = regulator_set_current_limit_regmap,
|
2021-01-17 20:49:17 +00:00
|
|
|
.set_suspend_enable = pf8x00_suspend_enable,
|
|
|
|
.set_suspend_disable = pf8x00_suspend_disable,
|
|
|
|
.set_suspend_voltage = pf8x00_set_suspend_voltage,
|
2020-11-30 11:23:29 +00:00
|
|
|
};
|
|
|
|
|
2021-01-14 17:47:13 +00:00
|
|
|
static const struct regulator_ops pf8x00_buck7_ops = {
|
2020-11-30 11:23:29 +00:00
|
|
|
.enable = regulator_enable_regmap,
|
|
|
|
.disable = regulator_disable_regmap,
|
|
|
|
.is_enabled = regulator_is_enabled_regmap,
|
|
|
|
.list_voltage = regulator_list_voltage_table,
|
2021-02-16 06:01:28 +00:00
|
|
|
.map_voltage = regulator_map_voltage_ascend,
|
2020-11-30 11:23:29 +00:00
|
|
|
.set_voltage_sel = regulator_set_voltage_sel_regmap,
|
|
|
|
.get_voltage_sel = regulator_get_voltage_sel_regmap,
|
2021-01-14 17:47:12 +00:00
|
|
|
.get_current_limit = regulator_get_current_limit_regmap,
|
|
|
|
.set_current_limit = regulator_set_current_limit_regmap,
|
2021-01-17 20:49:17 +00:00
|
|
|
.set_suspend_enable = pf8x00_suspend_enable,
|
|
|
|
.set_suspend_disable = pf8x00_suspend_disable,
|
2020-11-30 11:23:29 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regulator_ops pf8x00_vsnvs_ops = {
|
|
|
|
.enable = regulator_enable_regmap,
|
|
|
|
.disable = regulator_disable_regmap,
|
|
|
|
.is_enabled = regulator_is_enabled_regmap,
|
|
|
|
.list_voltage = regulator_list_voltage_table,
|
|
|
|
.map_voltage = regulator_map_voltage_ascend,
|
|
|
|
.set_voltage_sel = regulator_set_voltage_sel_regmap,
|
|
|
|
.get_voltage_sel = regulator_get_voltage_sel_regmap,
|
|
|
|
};
|
|
|
|
|
|
|
|
#define PF8X00LDO(_id, _name, base, voltages) \
|
|
|
|
[PF8X00_LDO ## _id] = { \
|
|
|
|
.desc = { \
|
|
|
|
.name = _name, \
|
|
|
|
.of_match = _name, \
|
|
|
|
.regulators_node = "regulators", \
|
|
|
|
.n_voltages = ARRAY_SIZE(voltages), \
|
|
|
|
.ops = &pf8x00_ldo_ops, \
|
|
|
|
.type = REGULATOR_VOLTAGE, \
|
|
|
|
.id = PF8X00_LDO ## _id, \
|
|
|
|
.owner = THIS_MODULE, \
|
|
|
|
.volt_table = voltages, \
|
|
|
|
.vsel_reg = (base) + LDO_RUN_VOLT, \
|
|
|
|
.vsel_mask = 0xff, \
|
|
|
|
.enable_reg = (base) + LDO_CONFIG2, \
|
|
|
|
.enable_val = 0x2, \
|
|
|
|
.disable_val = 0x0, \
|
|
|
|
.enable_mask = 2, \
|
|
|
|
}, \
|
2021-01-17 20:49:17 +00:00
|
|
|
.suspend_enable_reg = (base) + LDO_CONFIG2, \
|
|
|
|
.suspend_enable_mask = 1, \
|
|
|
|
.suspend_voltage_reg = (base) + LDO_STBY_VOLT, \
|
2020-11-30 11:23:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define PF8X00BUCK(_id, _name, base, voltages) \
|
|
|
|
[PF8X00_BUCK ## _id] = { \
|
|
|
|
.desc = { \
|
|
|
|
.name = _name, \
|
|
|
|
.of_match = _name, \
|
|
|
|
.regulators_node = "regulators", \
|
|
|
|
.of_parse_cb = pf8x00_of_parse_cb, \
|
2021-01-14 17:47:13 +00:00
|
|
|
.n_voltages = PF8XOO_SW1_6_VOLTAGE_NUM, \
|
|
|
|
.ops = &pf8x00_buck1_6_ops, \
|
2020-11-30 11:23:29 +00:00
|
|
|
.type = REGULATOR_VOLTAGE, \
|
|
|
|
.id = PF8X00_BUCK ## _id, \
|
|
|
|
.owner = THIS_MODULE, \
|
2021-01-25 16:13:41 +00:00
|
|
|
.ramp_delay = 19000, \
|
2021-01-14 17:47:13 +00:00
|
|
|
.linear_ranges = pf8x00_sw1_to_6_voltages, \
|
|
|
|
.n_linear_ranges = \
|
|
|
|
ARRAY_SIZE(pf8x00_sw1_to_6_voltages), \
|
|
|
|
.vsel_reg = (base) + SW_RUN_VOLT, \
|
|
|
|
.vsel_mask = 0xff, \
|
|
|
|
.curr_table = pf8x00_sw_current_table, \
|
|
|
|
.n_current_limits = \
|
|
|
|
ARRAY_SIZE(pf8x00_sw_current_table), \
|
|
|
|
.csel_reg = (base) + SW_CONFIG2, \
|
|
|
|
.csel_mask = PF8X00_SWXILIM_MASK, \
|
|
|
|
.enable_reg = (base) + SW_MODE1, \
|
|
|
|
.enable_val = 0x3, \
|
|
|
|
.disable_val = 0x0, \
|
|
|
|
.enable_mask = 0x3, \
|
|
|
|
.enable_time = 500, \
|
|
|
|
}, \
|
2021-01-17 20:49:17 +00:00
|
|
|
.suspend_enable_reg = (base) + SW_MODE1, \
|
|
|
|
.suspend_enable_mask = 0xc, \
|
|
|
|
.suspend_voltage_reg = (base) + SW_STBY_VOLT, \
|
2021-01-14 17:47:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define PF8X00BUCK7(_name, base, voltages) \
|
|
|
|
[PF8X00_BUCK7] = { \
|
|
|
|
.desc = { \
|
|
|
|
.name = _name, \
|
|
|
|
.of_match = _name, \
|
|
|
|
.regulators_node = "regulators", \
|
|
|
|
.of_parse_cb = pf8x00_of_parse_cb, \
|
|
|
|
.n_voltages = ARRAY_SIZE(voltages), \
|
|
|
|
.ops = &pf8x00_buck7_ops, \
|
|
|
|
.type = REGULATOR_VOLTAGE, \
|
|
|
|
.id = PF8X00_BUCK7, \
|
|
|
|
.owner = THIS_MODULE, \
|
2021-01-25 16:13:41 +00:00
|
|
|
.ramp_delay = 19000, \
|
2020-11-30 11:23:29 +00:00
|
|
|
.volt_table = voltages, \
|
|
|
|
.vsel_reg = (base) + SW_RUN_VOLT, \
|
|
|
|
.vsel_mask = 0xff, \
|
2021-01-14 17:47:12 +00:00
|
|
|
.curr_table = pf8x00_sw_current_table, \
|
|
|
|
.n_current_limits = \
|
|
|
|
ARRAY_SIZE(pf8x00_sw_current_table), \
|
|
|
|
.csel_reg = (base) + SW_CONFIG2, \
|
|
|
|
.csel_mask = PF8X00_SWXILIM_MASK, \
|
2020-11-30 11:23:29 +00:00
|
|
|
.enable_reg = (base) + SW_MODE1, \
|
|
|
|
.enable_val = 0x3, \
|
|
|
|
.disable_val = 0x0, \
|
|
|
|
.enable_mask = 0x3, \
|
|
|
|
.enable_time = 500, \
|
|
|
|
}, \
|
|
|
|
}
|
|
|
|
|
2021-01-14 17:47:13 +00:00
|
|
|
|
2020-11-30 11:23:29 +00:00
|
|
|
#define PF8X00VSNVS(_name, base, voltages) \
|
|
|
|
[PF8X00_VSNVS] = { \
|
|
|
|
.desc = { \
|
|
|
|
.name = _name, \
|
|
|
|
.of_match = _name, \
|
|
|
|
.regulators_node = "regulators", \
|
|
|
|
.n_voltages = ARRAY_SIZE(voltages), \
|
|
|
|
.ops = &pf8x00_vsnvs_ops, \
|
|
|
|
.type = REGULATOR_VOLTAGE, \
|
|
|
|
.id = PF8X00_VSNVS, \
|
|
|
|
.owner = THIS_MODULE, \
|
|
|
|
.volt_table = voltages, \
|
|
|
|
.vsel_reg = (base), \
|
|
|
|
.vsel_mask = 0x3, \
|
|
|
|
}, \
|
|
|
|
}
|
|
|
|
|
2021-01-17 20:49:17 +00:00
|
|
|
static struct pf8x00_regulator_data pf8x00_regs_data[PF8X00_MAX_REGULATORS] = {
|
2020-11-30 11:23:29 +00:00
|
|
|
PF8X00LDO(1, "ldo1", PF8X00_LDO_BASE(PF8X00_LDO1), pf8x00_ldo_voltages),
|
|
|
|
PF8X00LDO(2, "ldo2", PF8X00_LDO_BASE(PF8X00_LDO2), pf8x00_ldo_voltages),
|
|
|
|
PF8X00LDO(3, "ldo3", PF8X00_LDO_BASE(PF8X00_LDO3), pf8x00_ldo_voltages),
|
|
|
|
PF8X00LDO(4, "ldo4", PF8X00_LDO_BASE(PF8X00_LDO4), pf8x00_ldo_voltages),
|
|
|
|
PF8X00BUCK(1, "buck1", PF8X00_SW_BASE(PF8X00_BUCK1), pf8x00_sw1_to_6_voltages),
|
|
|
|
PF8X00BUCK(2, "buck2", PF8X00_SW_BASE(PF8X00_BUCK2), pf8x00_sw1_to_6_voltages),
|
|
|
|
PF8X00BUCK(3, "buck3", PF8X00_SW_BASE(PF8X00_BUCK3), pf8x00_sw1_to_6_voltages),
|
|
|
|
PF8X00BUCK(4, "buck4", PF8X00_SW_BASE(PF8X00_BUCK4), pf8x00_sw1_to_6_voltages),
|
|
|
|
PF8X00BUCK(5, "buck5", PF8X00_SW_BASE(PF8X00_BUCK5), pf8x00_sw1_to_6_voltages),
|
|
|
|
PF8X00BUCK(6, "buck6", PF8X00_SW_BASE(PF8X00_BUCK6), pf8x00_sw1_to_6_voltages),
|
2021-01-14 17:47:13 +00:00
|
|
|
PF8X00BUCK7("buck7", PF8X00_SW_BASE(PF8X00_BUCK7), pf8x00_sw7_voltages),
|
2020-11-30 11:23:29 +00:00
|
|
|
PF8X00VSNVS("vsnvs", PF8X00_VSNVS_CONFIG1, pf8x00_vsnvs_voltages),
|
|
|
|
};
|
|
|
|
|
|
|
|
static int pf8x00_identify(struct pf8x00_chip *chip)
|
|
|
|
{
|
|
|
|
unsigned int value;
|
|
|
|
u8 dev_fam, dev_id;
|
|
|
|
const char *name = NULL;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = regmap_read(chip->regmap, PF8X00_DEVICEID, &value);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(chip->dev, "failed to read chip family\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_fam = value & PF8X00_DEVICE_FAM_MASK;
|
|
|
|
switch (dev_fam) {
|
|
|
|
case PF8X00_FAM:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(chip->dev,
|
|
|
|
"Chip 0x%x is not from PF8X00 family\n", dev_fam);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_id = value & PF8X00_DEVICE_ID_MASK;
|
|
|
|
switch (dev_id) {
|
|
|
|
case PF8100:
|
|
|
|
name = "PF8100";
|
|
|
|
break;
|
|
|
|
case PF8121A:
|
|
|
|
name = "PF8121A";
|
|
|
|
break;
|
|
|
|
case PF8200:
|
2021-01-28 12:01:51 +00:00
|
|
|
name = "PF8200";
|
2020-11-30 11:23:29 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(chip->dev, "Unknown pf8x00 device id 0x%x\n", dev_id);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_info(chip->dev, "%s PMIC found.\n", name);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pf8x00_i2c_probe(struct i2c_client *client)
|
|
|
|
{
|
|
|
|
struct regulator_config config = { NULL, };
|
|
|
|
struct pf8x00_chip *chip;
|
|
|
|
int id;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
|
|
|
|
if (!chip)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
i2c_set_clientdata(client, chip);
|
|
|
|
chip->dev = &client->dev;
|
|
|
|
|
|
|
|
chip->regmap = devm_regmap_init_i2c(client, &pf8x00_regmap_config);
|
|
|
|
if (IS_ERR(chip->regmap)) {
|
|
|
|
ret = PTR_ERR(chip->regmap);
|
|
|
|
dev_err(&client->dev,
|
|
|
|
"regmap allocation failed with err %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = pf8x00_identify(chip);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-01-17 20:49:17 +00:00
|
|
|
for (id = 0; id < ARRAY_SIZE(pf8x00_regs_data); id++) {
|
|
|
|
struct pf8x00_regulator_data *data = &pf8x00_regs_data[id];
|
2020-11-30 11:23:29 +00:00
|
|
|
struct regulator_dev *rdev;
|
|
|
|
|
|
|
|
config.dev = chip->dev;
|
2021-01-17 20:49:17 +00:00
|
|
|
config.driver_data = data;
|
2020-11-30 11:23:29 +00:00
|
|
|
config.regmap = chip->regmap;
|
|
|
|
|
|
|
|
rdev = devm_regulator_register(&client->dev, &data->desc, &config);
|
|
|
|
if (IS_ERR(rdev)) {
|
|
|
|
dev_err(&client->dev,
|
|
|
|
"failed to register %s regulator\n", data->desc.name);
|
|
|
|
return PTR_ERR(rdev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id pf8x00_dt_ids[] = {
|
2020-12-15 13:20:24 +00:00
|
|
|
{ .compatible = "nxp,pf8100",},
|
|
|
|
{ .compatible = "nxp,pf8121a",},
|
|
|
|
{ .compatible = "nxp,pf8200",},
|
2020-11-30 11:23:29 +00:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, pf8x00_dt_ids);
|
|
|
|
|
|
|
|
static const struct i2c_device_id pf8x00_i2c_id[] = {
|
2020-12-15 13:20:24 +00:00
|
|
|
{ "pf8100", 0 },
|
|
|
|
{ "pf8121a", 0 },
|
|
|
|
{ "pf8200", 0 },
|
2020-11-30 11:23:29 +00:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, pf8x00_i2c_id);
|
|
|
|
|
|
|
|
static struct i2c_driver pf8x00_regulator_driver = {
|
|
|
|
.id_table = pf8x00_i2c_id,
|
|
|
|
.driver = {
|
|
|
|
.name = "pf8x00",
|
2023-03-16 19:54:42 +00:00
|
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
2020-11-30 11:23:29 +00:00
|
|
|
.of_match_table = pf8x00_dt_ids,
|
|
|
|
},
|
2023-05-05 22:02:18 +00:00
|
|
|
.probe = pf8x00_i2c_probe,
|
2020-11-30 11:23:29 +00:00
|
|
|
};
|
|
|
|
module_i2c_driver(pf8x00_regulator_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
|
|
|
|
MODULE_AUTHOR("Troy Kisky <troy.kisky@boundarydevices.com>");
|
|
|
|
MODULE_DESCRIPTION("Regulator Driver for NXP's PF8100/PF8121A/PF8200 PMIC");
|
|
|
|
MODULE_LICENSE("GPL v2");
|