riscv: Introduce alternative mechanism to apply errata solution
Introduce the "alternative" mechanism from ARM64 and x86 to apply the CPU
vendors' errata solution at runtime. The main purpose of this patch is
to provide a framework. Therefore, the implementation is quite basic for
now so that some scenarios could not use this schemei, such as patching
code to a module, relocating the patching code and heterogeneous CPU
topology.
Users could use the macro ALTERNATIVE to apply an errata to the existing
code flow. In the macro ALTERNATIVE, users need to specify the manufacturer
information(vendorid, archid, and impid) for this errata. Therefore, kernel
will know this errata is suitable for which CPU core. During the booting
procedure, kernel will select the errata required by the CPU core and then
patch it. It means that the kernel only applies the errata to the specified
CPU core. In this case, the vendor's errata does not affect each other at
runtime. The above patching procedure only occurs during the booting phase,
so we only take the overhead of the "alternative" mechanism once.
This "alternative" mechanism is enabled by default to ensure that all
required errata will be applied. However, users can disable this feature by
the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE".
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-03-22 14:26:03 +00:00
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menu "CPU errata selection"
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2023-08-18 13:57:19 +00:00
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config ERRATA_ANDES
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bool "Andes AX45MP errata"
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2023-09-01 11:03:20 +00:00
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depends on RISCV_ALTERNATIVE && RISCV_SBI
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2023-08-18 13:57:19 +00:00
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help
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All Andes errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all Andes errata. Please say "Y"
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here if your platform uses Andes CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_ANDES_CMO
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bool "Apply Andes cache management errata"
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2023-09-01 10:58:58 +00:00
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depends on ERRATA_ANDES && ARCH_R9A07G043
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2023-08-18 13:57:19 +00:00
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select RISCV_DMA_NONCOHERENT
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default y
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help
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This will apply the cache management errata to handle the
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non-standard handling on non-coherent operations on Andes cores.
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If you don't know what to do here, say "Y".
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2021-03-22 14:26:04 +00:00
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config ERRATA_SIFIVE
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bool "SiFive errata"
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RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
When moving switch_to's has_fpu() over to using
riscv_has_extension_likely() rather than static branches, the FPU code
gained a dependency on the alternatives framework.
That dependency has now been removed, as riscv_has_extension_ikely() now
contains a fallback path, using __riscv_isa_extension_available(), but
if CONFIG_RISCV_ALTERNATIVE isn't selected when CONFIG_FPU is, has_fpu()
checks will not benefit from the "fast path" that the alternatives
framework provides.
We want to ensure that alternatives are available whenever
riscv_has_extension_[un]likely() is used, rather than silently falling
back to the slow path, but rather than rely on selecting
RISCV_ALTERNATIVE in the myriad of locations that may use
riscv_has_extension_[un]likely(), select it (almost) always instead by
adding it to the main RISCV config entry.
xip kernels cannot make use of the alternatives framework, so it is not
enabled for those configurations, although this is the status quo.
All current sites that select RISCV_ALTERNATIVE are converted to
dependencies on the option instead. The explicit dependencies on
!XIP_KERNEL can be dropped, as RISCV_ALTERNATIVE is not user selectable.
Fixes: 702e64550b12 ("riscv: fpu: switch has_fpu() to riscv_has_extension_likely()")
Link: https://lore.kernel.org/all/ZBruFRwt3rUVngPu@zx2c4.com/
Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Jason A. Donenfeld <Jason@zx2c4.com>
Link: https://lore.kernel.org/r/20230324100538.3514663-3-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-24 10:05:39 +00:00
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depends on RISCV_ALTERNATIVE
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2021-03-22 14:26:04 +00:00
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help
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All SiFive errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all SiFive errata. Please say "Y"
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here if your platform uses SiFive CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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2021-03-22 14:26:05 +00:00
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config ERRATA_SIFIVE_CIP_453
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bool "Apply SiFive errata CIP-453"
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2021-04-29 07:58:36 +00:00
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depends on ERRATA_SIFIVE && 64BIT
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2021-03-22 14:26:05 +00:00
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default y
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help
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This will apply the SiFive CIP-453 errata to add sign extension
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to the $badaddr when exception type is instruction page fault
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and instruction access fault.
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If you don't know what to do here, say "Y".
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2021-03-22 14:26:06 +00:00
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config ERRATA_SIFIVE_CIP_1200
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bool "Apply SiFive errata CIP-1200"
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2021-04-29 07:58:36 +00:00
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depends on ERRATA_SIFIVE && 64BIT
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2021-03-22 14:26:06 +00:00
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default y
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help
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This will apply the SiFive CIP-1200 errata to repalce all
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"sfence.vma addr" with "sfence.vma" to ensure that the addr
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has been flushed from TLB.
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If you don't know what to do here, say "Y".
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2023-11-30 15:19:25 +00:00
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config ERRATA_STARFIVE_JH7100
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bool "StarFive JH7100 support"
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2023-12-15 19:09:09 +00:00
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depends on ARCH_STARFIVE
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depends on !DMA_DIRECT_REMAP
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depends on NONPORTABLE
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2023-11-30 15:19:25 +00:00
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select DMA_GLOBAL_POOL
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select RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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select SIFIVE_CCACHE
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default n
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help
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The StarFive JH7100 was a test chip for the JH7110 and has
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caches that are non-coherent with respect to peripheral DMAs.
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It was designed before the Zicbom extension so needs non-standard
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cache operations through the SiFive cache controller.
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Say "Y" if you want to support the BeagleV Starlight and/or
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StarFive VisionFive V1 boards.
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2022-05-11 19:29:21 +00:00
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config ERRATA_THEAD
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bool "T-HEAD errata"
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RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
When moving switch_to's has_fpu() over to using
riscv_has_extension_likely() rather than static branches, the FPU code
gained a dependency on the alternatives framework.
That dependency has now been removed, as riscv_has_extension_ikely() now
contains a fallback path, using __riscv_isa_extension_available(), but
if CONFIG_RISCV_ALTERNATIVE isn't selected when CONFIG_FPU is, has_fpu()
checks will not benefit from the "fast path" that the alternatives
framework provides.
We want to ensure that alternatives are available whenever
riscv_has_extension_[un]likely() is used, rather than silently falling
back to the slow path, but rather than rely on selecting
RISCV_ALTERNATIVE in the myriad of locations that may use
riscv_has_extension_[un]likely(), select it (almost) always instead by
adding it to the main RISCV config entry.
xip kernels cannot make use of the alternatives framework, so it is not
enabled for those configurations, although this is the status quo.
All current sites that select RISCV_ALTERNATIVE are converted to
dependencies on the option instead. The explicit dependencies on
!XIP_KERNEL can be dropped, as RISCV_ALTERNATIVE is not user selectable.
Fixes: 702e64550b12 ("riscv: fpu: switch has_fpu() to riscv_has_extension_likely()")
Link: https://lore.kernel.org/all/ZBruFRwt3rUVngPu@zx2c4.com/
Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Jason A. Donenfeld <Jason@zx2c4.com>
Link: https://lore.kernel.org/r/20230324100538.3514663-3-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-24 10:05:39 +00:00
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depends on RISCV_ALTERNATIVE
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2022-05-11 19:29:21 +00:00
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help
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All T-HEAD errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all T-HEAD errata. Please say "Y"
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here if your platform uses T-HEAD CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_THEAD_PBMT
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bool "Apply T-Head memory type errata"
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2022-09-07 15:49:32 +00:00
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depends on ERRATA_THEAD && 64BIT && MMU
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2022-05-11 19:29:21 +00:00
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select RISCV_ALTERNATIVE_EARLY
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default y
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help
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This will apply the memory type errata to handle the non-standard
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memory type bits in page-table-entries on T-Head SoCs.
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If you don't know what to do here, say "Y".
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2022-07-06 23:15:36 +00:00
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config ERRATA_THEAD_CMO
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bool "Apply T-Head cache management errata"
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2022-09-07 15:49:32 +00:00
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depends on ERRATA_THEAD && MMU
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2023-10-18 05:26:53 +00:00
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select DMA_DIRECT_REMAP
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2022-07-06 23:15:36 +00:00
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select RISCV_DMA_NONCOHERENT
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2023-11-14 14:33:37 +00:00
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select RISCV_NONSTANDARD_CACHE_OPS
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2022-07-06 23:15:36 +00:00
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default y
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help
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This will apply the cache management errata to handle the
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non-standard handling on non-coherent operations on T-Head SoCs.
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If you don't know what to do here, say "Y".
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2022-10-11 23:18:41 +00:00
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config ERRATA_THEAD_PMU
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bool "Apply T-Head PMU errata"
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depends on ERRATA_THEAD && RISCV_PMU_SBI
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default y
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help
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The T-Head C9xx cores implement a PMU overflow extension very
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similar to the core SSCOFPMF extension.
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This will apply the overflow errata to handle the non-standard
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behaviour via the regular SBI PMU driver and interface.
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If you don't know what to do here, say "Y".
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2022-05-20 12:02:31 +00:00
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endmenu # "CPU errata selection"
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