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230 lines
7.1 KiB
C
230 lines
7.1 KiB
C
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/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "xhci.h"
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#define XHCI_INIT_VALUE 0x0
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/* Add verbose debugging later, just print everything for now */
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void xhci_dbg_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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xhci_dbg(xhci, "// xHCI capability registers at 0x%x:\n",
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(unsigned int) xhci->cap_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
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xhci_dbg(xhci, "// @%x = 0x%x (CAPLENGTH AND HCIVERSION)\n",
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(unsigned int) &xhci->cap_regs->hc_capbase,
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(unsigned int) temp);
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xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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#if 0
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xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
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(unsigned int) HC_VERSION(temp));
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#endif
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xhci_dbg(xhci, "// xHCI operational registers at 0x%x:\n",
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(unsigned int) xhci->op_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "// @%x = 0x%x RTSOFF\n",
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(unsigned int) &xhci->cap_regs->run_regs_off,
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(unsigned int) temp & RTSOFF_MASK);
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xhci_dbg(xhci, "// xHCI runtime registers at 0x%x:\n",
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(unsigned int) xhci->run_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
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xhci_dbg(xhci, "// @%x = 0x%x DBOFF\n",
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(unsigned int) &xhci->cap_regs->db_off, temp);
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}
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void xhci_print_cap_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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xhci_dbg(xhci, "xHCI capability registers at 0x%x:\n",
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(unsigned int) xhci->cap_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
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xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
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(unsigned int) HC_VERSION(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
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xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Max device slots: %u\n",
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(unsigned int) HCS_MAX_SLOTS(temp));
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xhci_dbg(xhci, " Max interrupters: %u\n",
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(unsigned int) HCS_MAX_INTRS(temp));
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xhci_dbg(xhci, " Max ports: %u\n",
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(unsigned int) HCS_MAX_PORTS(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
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xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
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(unsigned int) HCS_IST(temp));
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xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
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(unsigned int) HCS_ERST_MAX(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
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xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
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(unsigned int) HCS_U1_LATENCY(temp));
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xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
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(unsigned int) HCS_U2_LATENCY(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
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xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
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xhci_dbg(xhci, " HC generates %s bit addresses\n",
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HCC_64BIT_ADDR(temp) ? "64" : "32");
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/* FIXME */
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xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
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temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
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}
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void xhci_print_command_reg(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = xhci_readl(xhci, &xhci->op_regs->command);
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xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
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xhci_dbg(xhci, " HC is %s\n",
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(temp & CMD_RUN) ? "running" : "being stopped");
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xhci_dbg(xhci, " HC has %sfinished hard reset\n",
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(temp & CMD_RESET) ? "not " : "");
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xhci_dbg(xhci, " Event Interrupts %s\n",
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(temp & CMD_EIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " Host System Error Interrupts %s\n",
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(temp & CMD_EIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " HC has %sfinished light reset\n",
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(temp & CMD_LRESET) ? "not " : "");
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}
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void xhci_print_status(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
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xhci_dbg(xhci, " Event ring is %sempty\n",
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(temp & STS_EINT) ? "not " : "");
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xhci_dbg(xhci, " %sHost System Error\n",
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(temp & STS_FATAL) ? "WARNING: " : "No ");
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xhci_dbg(xhci, " HC is %s\n",
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(temp & STS_HALT) ? "halted" : "running");
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}
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void xhci_print_op_regs(struct xhci_hcd *xhci)
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{
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xhci_dbg(xhci, "xHCI operational registers at 0x%x:\n",
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(unsigned int) xhci->op_regs);
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xhci_print_command_reg(xhci);
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xhci_print_status(xhci);
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}
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void xhci_print_ir_set(struct xhci_hcd *xhci, struct intr_reg *ir_set, int set_num)
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{
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void *addr;
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u32 temp;
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addr = &ir_set->irq_pending;
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temp = xhci_readl(xhci, addr);
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if (temp == XHCI_INIT_VALUE)
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return;
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xhci_dbg(xhci, " 0x%x: ir_set[%i]\n", (unsigned int) ir_set, set_num);
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xhci_dbg(xhci, " 0x%x: ir_set.pending = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->irq_control;
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.control = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_size;
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_size = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->rsvd;
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temp = xhci_readl(xhci, addr);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: 0x%x: ir_set.rsvd = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_base[0];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_base[0] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_base[1];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_base[1] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_dequeue[0];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[0] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_dequeue[1];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[1] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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}
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void xhci_print_run_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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int i;
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xhci_dbg(xhci, "xHCI runtime registers at 0x%x:\n",
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(unsigned int) xhci->run_regs);
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temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
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xhci_dbg(xhci, " 0x%x: Microframe index = 0x%x\n",
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(unsigned int) &xhci->run_regs->microframe_index,
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(unsigned int) temp);
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for (i = 0; i < 7; ++i) {
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temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: 0x%x: Rsvd[%i] = 0x%x\n",
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(unsigned int) &xhci->run_regs->rsvd[i],
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i, (unsigned int) temp);
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}
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}
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void xhci_print_registers(struct xhci_hcd *xhci)
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{
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xhci_print_cap_regs(xhci);
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xhci_print_op_regs(xhci);
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}
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