2019-05-28 17:10:25 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2008-10-23 05:26:29 +00:00
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#ifndef _ASM_X86_APIC_H
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#define _ASM_X86_APIC_H
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2008-01-30 12:30:15 +00:00
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2009-02-17 12:52:29 +00:00
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#include <linux/cpumask.h>
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x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 18:15:30 +00:00
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#include <asm/alternative.h>
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2009-02-17 12:52:29 +00:00
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#include <asm/cpufeature.h>
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#include <asm/apicdef.h>
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2011-07-26 23:09:06 +00:00
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#include <linux/atomic.h>
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2009-02-17 12:52:29 +00:00
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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2008-07-10 18:16:52 +00:00
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#include <asm/msr.h>
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2018-07-29 11:06:04 +00:00
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#include <asm/hardirq.h>
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2008-01-30 12:30:15 +00:00
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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2015-12-14 10:19:12 +00:00
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/* Macros for apic_extnmi which controls external NMI masking */
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#define APIC_EXTNMI_BSP 0 /* Default */
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#define APIC_EXTNMI_ALL 1
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#define APIC_EXTNMI_NONE 2
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2008-01-30 12:30:15 +00:00
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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2009-02-11 10:27:39 +00:00
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
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2023-08-08 22:04:01 +00:00
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extern void x86_32_probe_apic(void);
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2009-02-11 10:27:39 +00:00
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#else
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2023-08-08 22:04:01 +00:00
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static inline void x86_32_probe_apic(void) { }
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2009-02-11 10:27:39 +00:00
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#endif
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2008-01-30 12:30:15 +00:00
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#ifdef CONFIG_X86_LOCAL_APIC
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x86/apic: Silence -Wtype-limits compiler warnings
There are many compiler warnings like this,
In file included from ./arch/x86/include/asm/smp.h:13,
from ./arch/x86/include/asm/mmzone_64.h:11,
from ./arch/x86/include/asm/mmzone.h:5,
from ./include/linux/mmzone.h:969,
from ./include/linux/gfp.h:6,
from ./include/linux/mm.h:10,
from arch/x86/kernel/apic/io_apic.c:34:
arch/x86/kernel/apic/io_apic.c: In function 'check_timer':
./arch/x86/include/asm/apic.h:37:11: warning: comparison of unsigned
expression >= 0 is always true [-Wtype-limits]
if ((v) <= apic_verbosity) \
^~
arch/x86/kernel/apic/io_apic.c:2160:2: note: in expansion of macro
'apic_printk'
apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
^~~~~~~~~~~
./arch/x86/include/asm/apic.h:37:11: warning: comparison of unsigned
expression >= 0 is always true [-Wtype-limits]
if ((v) <= apic_verbosity) \
^~
arch/x86/kernel/apic/io_apic.c:2207:4: note: in expansion of macro
'apic_printk'
apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
^~~~~~~~~~~
APIC_QUIET is 0, so silence them by making apic_verbosity type int.
Signed-off-by: Qian Cai <cai@lca.pw>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1562621805-24789-1-git-send-email-cai@lca.pw
2019-07-08 21:36:45 +00:00
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extern int apic_verbosity;
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2008-01-30 12:30:15 +00:00
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extern int local_apic_timer_c2_ok;
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2023-08-08 22:03:40 +00:00
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extern bool apic_is_disabled;
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2019-05-09 05:54:16 +00:00
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extern unsigned int lapic_timer_period;
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2009-01-28 16:16:25 +00:00
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2023-05-12 21:07:55 +00:00
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extern int cpuid_to_apicid[];
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2017-09-13 09:12:49 +00:00
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extern enum apic_intr_mode_id apic_intr_mode;
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enum apic_intr_mode_id {
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APIC_PIC,
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APIC_VIRTUAL_WIRE,
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APIC_VIRTUAL_WIRE_NO_CONFIG,
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APIC_SYMMETRIC_IO,
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APIC_SYMMETRIC_IO_NO_ROUTING
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};
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2009-09-15 07:12:30 +00:00
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/*
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* With 82489DX we can't rely on apic feature bit
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* retrieved via cpuid but still have to deal with
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* such an apic chip so we assume that SMP configuration
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* is found from MP table (64bit case uses ACPI mostly
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* which set smp presence flag as well so we are safe
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* to use this helper too).
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*/
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static inline bool apic_from_smp_config(void)
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{
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2023-08-08 22:03:40 +00:00
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return smp_found_config && !apic_is_disabled;
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2009-09-15 07:12:30 +00:00
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}
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2008-01-30 12:30:15 +00:00
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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2007-10-11 09:20:03 +00:00
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#endif
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2008-01-30 12:30:15 +00:00
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2008-07-10 18:16:49 +00:00
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static inline void native_apic_mem_write(u32 reg, u32 v)
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2008-01-30 12:30:15 +00:00
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{
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x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 18:15:30 +00:00
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volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
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2008-01-30 12:30:15 +00:00
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x86/asm: Cleanup prefetch primitives
This is based on a patch originally by hpa.
With the current improvements to the alternatives, we can simply use %P1
as a mem8 operand constraint and rely on the toolchain to generate the
proper instruction sizes. For example, on 32-bit, where we use an empty
old instruction we get:
apply_alternatives: feat: 6*32+8, old: (c104648b, len: 4), repl: (c195566c, len: 4)
c104648b: alt_insn: 90 90 90 90
c195566c: rpl_insn: 0f 0d 4b 5c
...
apply_alternatives: feat: 6*32+8, old: (c18e09b4, len: 3), repl: (c1955948, len: 3)
c18e09b4: alt_insn: 90 90 90
c1955948: rpl_insn: 0f 0d 08
...
apply_alternatives: feat: 6*32+8, old: (c1190cf9, len: 7), repl: (c1955a79, len: 7)
c1190cf9: alt_insn: 90 90 90 90 90 90 90
c1955a79: rpl_insn: 0f 0d 0d a0 d4 85 c1
all with the proper padding done depending on the size of the
replacement instruction the compiler generates.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: H. Peter Anvin <hpa@linux.intel.com>
2015-01-18 16:48:18 +00:00
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alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
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x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 18:15:30 +00:00
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ASM_OUTPUT2("=r" (v), "=m" (*addr)),
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ASM_OUTPUT2("0" (v), "m" (*addr)));
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2008-01-30 12:30:15 +00:00
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}
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2008-07-10 18:16:49 +00:00
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static inline u32 native_apic_mem_read(u32 reg)
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2008-01-30 12:30:15 +00:00
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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2023-08-08 22:04:15 +00:00
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static inline void native_apic_mem_eoi(void)
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{
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native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
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}
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2009-02-17 07:02:14 +00:00
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extern void native_apic_icr_write(u32 low, u32 id);
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extern u64 native_apic_icr_read(void);
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2015-01-15 21:22:09 +00:00
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static inline bool apic_is_x2apic_enabled(void)
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{
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u64 msr;
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if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
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return false;
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return msr & X2APIC_ENABLE;
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}
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2015-09-28 10:26:31 +00:00
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extern void enable_IR_x2apic(void);
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extern int get_physical_broadcast(void);
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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2019-07-24 15:25:52 +00:00
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extern void apic_soft_disable(void);
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2015-09-28 10:26:31 +00:00
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extern void lapic_shutdown(void);
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extern void sync_Arb_IDs(void);
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2017-11-28 14:53:50 +00:00
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extern void init_bsp_APIC(void);
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2020-01-23 11:54:53 +00:00
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extern void apic_intr_mode_select(void);
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2017-09-13 09:12:45 +00:00
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extern void apic_intr_mode_init(void);
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2015-09-28 10:26:31 +00:00
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extern void init_apic_mappings(void);
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void register_lapic_address(unsigned long address);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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2016-07-14 15:22:55 +00:00
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extern void lapic_update_tsc_freq(void);
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2015-09-28 10:26:31 +00:00
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#ifdef CONFIG_X86_64
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2023-08-08 22:03:48 +00:00
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static inline bool apic_force_enable(unsigned long addr)
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2015-09-28 10:26:31 +00:00
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{
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2023-08-08 22:03:48 +00:00
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return false;
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2015-09-28 10:26:31 +00:00
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}
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#else
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2023-08-08 22:03:48 +00:00
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extern bool apic_force_enable(unsigned long addr);
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2015-09-28 10:26:31 +00:00
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#endif
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extern void apic_ap_setup(void);
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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extern int apic_is_clustered_box(void);
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#else
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static inline int apic_is_clustered_box(void)
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{
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return 0;
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}
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#endif
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extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
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2017-09-13 21:29:38 +00:00
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extern void lapic_assign_system_vectors(void);
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extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
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2021-05-25 11:08:41 +00:00
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extern void lapic_update_legacy_vectors(void);
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2017-09-13 21:29:38 +00:00
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extern void lapic_online(void);
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extern void lapic_offline(void);
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2019-06-28 07:23:07 +00:00
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extern bool apic_needs_pit(void);
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2015-09-28 10:26:31 +00:00
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2019-07-22 18:47:23 +00:00
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extern void apic_send_IPI_allbutself(unsigned int vector);
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2015-09-28 10:26:31 +00:00
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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static inline void init_apic_mappings(void) { }
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static inline void disable_local_APIC(void) { }
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# define setup_boot_APIC_clock x86_init_noop
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# define setup_secondary_APIC_clock x86_init_noop
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2016-07-14 15:22:55 +00:00
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static inline void lapic_update_tsc_freq(void) { }
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2018-01-17 07:37:48 +00:00
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static inline void init_bsp_APIC(void) { }
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2020-01-23 11:54:53 +00:00
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static inline void apic_intr_mode_select(void) { }
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2017-09-13 09:12:45 +00:00
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static inline void apic_intr_mode_init(void) { }
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2017-09-13 21:29:38 +00:00
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static inline void lapic_assign_system_vectors(void) { }
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static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
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2019-06-28 07:23:07 +00:00
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static inline bool apic_needs_pit(void) { return true; }
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2015-09-28 10:26:31 +00:00
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#endif /* !CONFIG_X86_LOCAL_APIC */
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2009-04-03 09:15:50 +00:00
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#ifdef CONFIG_X86_X2APIC
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2008-07-10 18:16:52 +00:00
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static inline void native_apic_msr_write(u32 reg, u32 v)
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{
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if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
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reg == APIC_LVR)
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return;
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wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
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}
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2023-08-08 22:04:15 +00:00
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static inline void native_apic_msr_eoi(void)
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2012-05-16 16:03:58 +00:00
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{
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2017-01-20 20:29:41 +00:00
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__wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
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2012-05-16 16:03:58 +00:00
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}
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2008-07-10 18:16:52 +00:00
|
|
|
static inline u32 native_apic_msr_read(u32 reg)
|
|
|
|
{
|
2010-11-08 21:20:29 +00:00
|
|
|
u64 msr;
|
2008-07-10 18:16:52 +00:00
|
|
|
|
|
|
|
if (reg == APIC_DFR)
|
|
|
|
return -1;
|
|
|
|
|
2010-11-08 21:20:29 +00:00
|
|
|
rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
|
|
|
|
return (u32)msr;
|
2008-07-10 18:16:52 +00:00
|
|
|
}
|
|
|
|
|
2009-02-17 07:02:14 +00:00
|
|
|
static inline void native_x2apic_icr_write(u32 low, u32 id)
|
|
|
|
{
|
|
|
|
wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u64 native_x2apic_icr_read(void)
|
|
|
|
{
|
|
|
|
unsigned long val;
|
|
|
|
|
|
|
|
rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2015-01-15 21:22:11 +00:00
|
|
|
extern int x2apic_mode;
|
2009-04-20 20:02:27 +00:00
|
|
|
extern int x2apic_phys;
|
2020-10-24 21:35:01 +00:00
|
|
|
extern void __init x2apic_set_max_apicid(u32 apicid);
|
2015-01-15 21:22:26 +00:00
|
|
|
extern void x2apic_setup(void);
|
2008-09-03 23:58:31 +00:00
|
|
|
static inline int x2apic_enabled(void)
|
|
|
|
{
|
2016-03-29 15:41:57 +00:00
|
|
|
return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
|
2008-09-03 23:58:31 +00:00
|
|
|
}
|
2009-04-20 20:02:27 +00:00
|
|
|
|
2016-03-29 15:41:57 +00:00
|
|
|
#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
|
2015-09-28 10:26:31 +00:00
|
|
|
#else /* !CONFIG_X86_X2APIC */
|
2015-01-15 21:22:26 +00:00
|
|
|
static inline void x2apic_setup(void) { }
|
2015-01-15 21:22:19 +00:00
|
|
|
static inline int x2apic_enabled(void) { return 0; }
|
2023-08-08 22:03:45 +00:00
|
|
|
static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
|
2015-01-15 21:22:11 +00:00
|
|
|
#define x2apic_mode (0)
|
|
|
|
#define x2apic_supported() (0)
|
2015-09-28 10:26:31 +00:00
|
|
|
#endif /* !CONFIG_X86_X2APIC */
|
2022-11-29 21:50:08 +00:00
|
|
|
extern void __init check_x2apic(void);
|
2008-01-30 12:30:15 +00:00
|
|
|
|
2017-06-19 23:37:44 +00:00
|
|
|
struct irq_data;
|
|
|
|
|
2009-02-17 12:52:29 +00:00
|
|
|
/*
|
|
|
|
* Copyright 2004 James Cleverdon, IBM.
|
|
|
|
*
|
|
|
|
* Generic APIC sub-arch data struct.
|
|
|
|
*
|
|
|
|
* Hacked for x86-64 by James Cleverdon from i386 architecture code by
|
|
|
|
* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
|
|
|
|
* James Cleverdon.
|
|
|
|
*/
|
2009-02-17 15:28:46 +00:00
|
|
|
struct apic {
|
2017-09-13 21:29:23 +00:00
|
|
|
/* Hotpath functions first */
|
2023-08-08 22:04:15 +00:00
|
|
|
void (*eoi)(void);
|
|
|
|
void (*native_eoi)(void);
|
2017-09-13 21:29:23 +00:00
|
|
|
void (*write)(u32 reg, u32 v);
|
|
|
|
u32 (*read)(u32 reg);
|
|
|
|
|
|
|
|
/* IPI related functions */
|
|
|
|
void (*wait_icr_idle)(void);
|
|
|
|
u32 (*safe_wait_icr_idle)(void);
|
|
|
|
|
|
|
|
void (*send_IPI)(int cpu, int vector);
|
|
|
|
void (*send_IPI_mask)(const struct cpumask *mask, int vector);
|
|
|
|
void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
|
|
|
|
void (*send_IPI_allbutself)(int vector);
|
|
|
|
void (*send_IPI_all)(int vector);
|
|
|
|
void (*send_IPI_self)(int vector);
|
|
|
|
|
2020-10-24 21:35:05 +00:00
|
|
|
enum apic_delivery_modes delivery_mode;
|
2023-08-08 22:04:11 +00:00
|
|
|
|
|
|
|
u32 disable_esr : 1,
|
|
|
|
dest_mode_logical : 1,
|
|
|
|
x2apic_set_max_apicid : 1;
|
2017-09-13 21:29:23 +00:00
|
|
|
|
2017-09-13 21:29:37 +00:00
|
|
|
u32 (*calc_dest_apicid)(unsigned int cpu);
|
2017-09-13 21:29:23 +00:00
|
|
|
|
|
|
|
/* ICR related functions */
|
|
|
|
u64 (*icr_read)(void);
|
|
|
|
void (*icr_write)(u32 low, u32 high);
|
|
|
|
|
2023-08-08 22:04:10 +00:00
|
|
|
/* The limit of the APIC ID space. */
|
|
|
|
u32 max_apic_id;
|
|
|
|
|
2017-09-13 21:29:23 +00:00
|
|
|
/* Probe, setup and smpboot functions */
|
|
|
|
int (*probe)(void);
|
|
|
|
int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
|
2023-08-08 22:04:02 +00:00
|
|
|
bool (*apic_id_registered)(void);
|
2017-09-13 21:29:23 +00:00
|
|
|
|
|
|
|
bool (*check_apicid_used)(physid_mask_t *map, int apicid);
|
|
|
|
void (*init_apic_ldr)(void);
|
|
|
|
void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
|
|
|
|
int (*cpu_present_to_apicid)(int mps_cpu);
|
|
|
|
int (*phys_pkg_id)(int cpuid_apic, int index_msb);
|
|
|
|
|
|
|
|
u32 (*get_apic_id)(unsigned long x);
|
|
|
|
u32 (*set_apic_id)(unsigned int id);
|
2009-02-17 12:52:29 +00:00
|
|
|
|
|
|
|
/* wakeup_secondary_cpu */
|
2017-09-13 21:29:23 +00:00
|
|
|
int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
|
2022-04-05 23:29:29 +00:00
|
|
|
/* wakeup secondary CPU using 64-bit wakeup point */
|
|
|
|
int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
|
2009-02-17 12:52:29 +00:00
|
|
|
|
2017-09-13 21:29:23 +00:00
|
|
|
char *name;
|
2009-02-17 12:52:29 +00:00
|
|
|
};
|
|
|
|
|
2009-02-26 11:47:40 +00:00
|
|
|
/*
|
|
|
|
* Pointer to the local APIC driver in use on this system (there's
|
|
|
|
* always just one such driver in use - the kernel decides via an
|
|
|
|
* early probing process which one it picks - and then sticks to it):
|
|
|
|
*/
|
2009-02-17 15:28:46 +00:00
|
|
|
extern struct apic *apic;
|
2009-02-26 11:47:40 +00:00
|
|
|
|
2011-05-21 00:51:17 +00:00
|
|
|
/*
|
|
|
|
* APIC drivers are probed based on how they are listed in the .apicdrivers
|
|
|
|
* section. So the order is important and enforced by the ordering
|
|
|
|
* of different apic driver files in the Makefile.
|
|
|
|
*
|
|
|
|
* For the files having two apic drivers, we use apic_drivers()
|
|
|
|
* to enforce the order with in them.
|
|
|
|
*/
|
|
|
|
#define apic_driver(sym) \
|
2012-10-05 00:11:42 +00:00
|
|
|
static const struct apic *__apicdrivers_##sym __used \
|
2011-05-21 00:51:17 +00:00
|
|
|
__aligned(sizeof(struct apic *)) \
|
2020-10-22 02:36:07 +00:00
|
|
|
__section(".apicdrivers") = { &sym }
|
2011-05-21 00:51:17 +00:00
|
|
|
|
|
|
|
#define apic_drivers(sym1, sym2) \
|
|
|
|
static struct apic *__apicdrivers_##sym1##sym2[2] __used \
|
|
|
|
__aligned(sizeof(struct apic *)) \
|
2020-10-22 02:36:07 +00:00
|
|
|
__section(".apicdrivers") = { &sym1, &sym2 }
|
2011-05-21 00:51:17 +00:00
|
|
|
|
|
|
|
extern struct apic *__apicdrivers[], *__apicdrivers_end[];
|
|
|
|
|
2009-02-26 11:47:40 +00:00
|
|
|
/*
|
|
|
|
* APIC functionality to boot other CPUs - only used on SMP:
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_SMP
|
2017-09-13 21:29:53 +00:00
|
|
|
extern int lapic_can_unplug_cpu(void);
|
2009-02-26 11:47:40 +00:00
|
|
|
#endif
|
2009-02-17 12:52:29 +00:00
|
|
|
|
2010-03-17 10:37:00 +00:00
|
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
2011-12-13 02:51:53 +00:00
|
|
|
|
2009-02-17 12:52:29 +00:00
|
|
|
static inline u32 apic_read(u32 reg)
|
|
|
|
{
|
|
|
|
return apic->read(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void apic_write(u32 reg, u32 val)
|
|
|
|
{
|
|
|
|
apic->write(reg, val);
|
|
|
|
}
|
|
|
|
|
2012-05-16 16:03:52 +00:00
|
|
|
static inline void apic_eoi(void)
|
|
|
|
{
|
2023-08-08 22:04:15 +00:00
|
|
|
apic->eoi();
|
2012-05-16 16:03:52 +00:00
|
|
|
}
|
|
|
|
|
2009-02-17 12:52:29 +00:00
|
|
|
static inline u64 apic_icr_read(void)
|
|
|
|
{
|
|
|
|
return apic->icr_read();
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void apic_icr_write(u32 low, u32 high)
|
|
|
|
{
|
|
|
|
apic->icr_write(low, high);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void apic_wait_icr_idle(void)
|
|
|
|
{
|
2023-08-08 22:04:04 +00:00
|
|
|
if (apic->wait_icr_idle)
|
|
|
|
apic->wait_icr_idle();
|
2009-02-17 12:52:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 safe_apic_wait_icr_idle(void)
|
|
|
|
{
|
2023-08-08 22:04:05 +00:00
|
|
|
return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
|
2009-02-17 12:52:29 +00:00
|
|
|
}
|
|
|
|
|
2023-08-08 22:04:09 +00:00
|
|
|
static inline bool apic_id_valid(u32 apic_id)
|
|
|
|
{
|
2023-08-08 22:04:12 +00:00
|
|
|
return apic_id <= apic->max_apic_id;
|
2023-08-08 22:04:09 +00:00
|
|
|
}
|
|
|
|
|
2023-08-08 22:04:15 +00:00
|
|
|
extern void __init apic_set_eoi_cb(void (*eoi)(void));
|
2012-07-15 12:56:46 +00:00
|
|
|
|
2010-03-17 10:37:00 +00:00
|
|
|
#else /* CONFIG_X86_LOCAL_APIC */
|
|
|
|
|
|
|
|
static inline u32 apic_read(u32 reg) { return 0; }
|
|
|
|
static inline void apic_write(u32 reg, u32 val) { }
|
2012-05-16 16:03:52 +00:00
|
|
|
static inline void apic_eoi(void) { }
|
2010-03-17 10:37:00 +00:00
|
|
|
static inline u64 apic_icr_read(void) { return 0; }
|
|
|
|
static inline void apic_icr_write(u32 low, u32 high) { }
|
|
|
|
static inline void apic_wait_icr_idle(void) { }
|
|
|
|
static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
|
2023-08-08 22:04:15 +00:00
|
|
|
static inline void apic_set_eoi_cb(void (*eoi)(void)) {}
|
2010-03-17 10:37:00 +00:00
|
|
|
|
|
|
|
#endif /* CONFIG_X86_LOCAL_APIC */
|
2009-02-17 12:52:29 +00:00
|
|
|
|
2018-06-04 15:33:55 +00:00
|
|
|
extern void apic_ack_irq(struct irq_data *data);
|
|
|
|
|
2020-01-31 14:26:52 +00:00
|
|
|
static inline bool lapic_vector_set_in_irr(unsigned int vector)
|
|
|
|
{
|
|
|
|
u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
|
|
|
|
|
|
|
|
return !!(irr & (1U << (vector % 32)));
|
|
|
|
}
|
|
|
|
|
2009-02-17 12:52:29 +00:00
|
|
|
static inline unsigned default_get_apic_id(unsigned long x)
|
|
|
|
{
|
|
|
|
unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
|
|
|
|
|
2009-06-08 13:55:09 +00:00
|
|
|
if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
|
2009-02-17 12:52:29 +00:00
|
|
|
return (x >> 24) & 0xFF;
|
|
|
|
else
|
|
|
|
return (x >> 24) & 0x0F;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2014-07-31 06:53:27 +00:00
|
|
|
* Warm reset vector position:
|
2009-02-17 12:52:29 +00:00
|
|
|
*/
|
2014-07-31 06:53:27 +00:00
|
|
|
#define TRAMPOLINE_PHYS_LOW 0x467
|
|
|
|
#define TRAMPOLINE_PHYS_HIGH 0x469
|
2009-02-17 12:52:29 +00:00
|
|
|
|
2011-09-28 15:44:54 +00:00
|
|
|
extern void generic_bigsmp_probe(void);
|
2009-02-17 12:52:29 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
|
|
|
|
|
|
|
#include <asm/smp.h>
|
|
|
|
|
2017-09-13 21:29:22 +00:00
|
|
|
extern struct apic apic_noop;
|
2009-02-17 12:52:29 +00:00
|
|
|
|
|
|
|
static inline unsigned int read_apic_id(void)
|
|
|
|
{
|
2017-09-13 21:29:22 +00:00
|
|
|
unsigned int reg = apic_read(APIC_ID);
|
2009-02-17 12:52:29 +00:00
|
|
|
|
|
|
|
return apic->get_apic_id(reg);
|
|
|
|
}
|
|
|
|
|
2022-04-05 23:29:30 +00:00
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
|
|
|
|
extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler);
|
2023-08-08 22:03:55 +00:00
|
|
|
extern int default_acpi_madt_oem_check(char *, char *);
|
2023-08-08 22:04:01 +00:00
|
|
|
extern void x86_64_probe_apic(void);
|
2023-08-08 22:03:55 +00:00
|
|
|
#else
|
|
|
|
static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
|
2023-08-08 22:04:01 +00:00
|
|
|
static inline void x86_64_probe_apic(void) { }
|
2022-04-05 23:29:30 +00:00
|
|
|
#endif
|
|
|
|
|
2018-04-10 01:16:06 +00:00
|
|
|
extern int default_apic_id_valid(u32 apicid);
|
2017-09-13 21:29:37 +00:00
|
|
|
|
|
|
|
extern u32 apic_default_calc_apicid(unsigned int cpu);
|
|
|
|
extern u32 apic_flat_calc_apicid(unsigned int cpu);
|
|
|
|
|
2017-09-13 21:29:22 +00:00
|
|
|
extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
|
|
|
|
extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
|
2009-02-17 12:52:29 +00:00
|
|
|
extern int default_cpu_present_to_apicid(int mps_cpu);
|
|
|
|
|
2023-08-08 22:03:43 +00:00
|
|
|
#else /* CONFIG_X86_LOCAL_APIC */
|
|
|
|
|
|
|
|
static inline unsigned int read_apic_id(void) { return 0; }
|
|
|
|
|
|
|
|
#endif /* !CONFIG_X86_LOCAL_APIC */
|
2017-09-13 21:29:22 +00:00
|
|
|
|
2018-05-29 15:50:22 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2019-07-22 18:47:22 +00:00
|
|
|
void apic_smt_update(void);
|
2018-05-29 15:50:22 +00:00
|
|
|
#else
|
2019-07-22 18:47:22 +00:00
|
|
|
static inline void apic_smt_update(void) { }
|
2018-05-29 15:50:22 +00:00
|
|
|
#endif
|
|
|
|
|
2020-08-26 11:16:33 +00:00
|
|
|
struct msi_msg;
|
2020-10-24 21:35:09 +00:00
|
|
|
struct irq_cfg;
|
2020-08-26 11:16:33 +00:00
|
|
|
|
2020-10-24 21:35:09 +00:00
|
|
|
extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
|
|
|
|
bool dmar);
|
2020-08-26 11:16:33 +00:00
|
|
|
|
2013-08-20 07:01:07 +00:00
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extern void ioapic_zap_locks(void);
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2008-10-23 05:26:29 +00:00
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#endif /* _ASM_X86_APIC_H */
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