2016-09-09 14:32:33 +00:00
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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struct amdgpu_gtt_mgr {
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struct drm_mm mm;
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spinlock_t lock;
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2017-08-07 15:11:33 +00:00
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atomic64_t available;
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2016-09-09 14:32:33 +00:00
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};
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2017-10-16 14:50:32 +00:00
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struct amdgpu_gtt_node {
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struct drm_mm_node node;
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struct ttm_buffer_object *tbo;
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};
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2016-09-09 14:32:33 +00:00
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/**
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* amdgpu_gtt_mgr_init - init GTT manager and DRM MM
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*
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* @man: TTM memory type manager
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* @p_size: maximum size of GTT
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*
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* Allocate and initialize the GTT manager.
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*/
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static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,
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unsigned long p_size)
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{
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2017-07-07 11:16:37 +00:00
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struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
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2016-09-09 14:32:33 +00:00
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struct amdgpu_gtt_mgr *mgr;
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2017-06-28 10:18:54 +00:00
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uint64_t start, size;
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2016-09-09 14:32:33 +00:00
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mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
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if (!mgr)
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return -ENOMEM;
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2017-06-28 10:18:54 +00:00
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start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
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2018-01-12 13:52:22 +00:00
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size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
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2017-06-28 10:18:54 +00:00
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drm_mm_init(&mgr->mm, start, size);
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2016-09-09 14:32:33 +00:00
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spin_lock_init(&mgr->lock);
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2017-08-07 15:11:33 +00:00
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atomic64_set(&mgr->available, p_size);
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2016-09-09 14:32:33 +00:00
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man->priv = mgr;
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return 0;
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}
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/**
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* amdgpu_gtt_mgr_fini - free and destroy GTT manager
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*
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* @man: TTM memory type manager
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*
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* Destroy and free the GTT manager, returns -EBUSY if ranges are still
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* allocated inside it.
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*/
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static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
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{
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struct amdgpu_gtt_mgr *mgr = man->priv;
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2018-01-19 16:21:04 +00:00
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spin_lock(&mgr->lock);
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2016-09-09 14:32:33 +00:00
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drm_mm_takedown(&mgr->mm);
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spin_unlock(&mgr->lock);
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kfree(mgr);
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man->priv = NULL;
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return 0;
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}
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2017-06-30 08:41:07 +00:00
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/**
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2017-10-27 12:17:09 +00:00
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* amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space
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2017-06-30 08:41:07 +00:00
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*
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* @mem: the mem object to check
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*
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* Check if a mem object has already address space allocated.
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*/
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2017-10-27 12:17:09 +00:00
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bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem)
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2017-06-30 08:41:07 +00:00
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{
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2017-10-16 14:50:32 +00:00
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struct amdgpu_gtt_node *node = mem->mm_node;
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2017-06-30 08:41:07 +00:00
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2017-10-16 14:50:32 +00:00
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return (node->node.start != AMDGPU_BO_INVALID_OFFSET);
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2017-06-30 08:41:07 +00:00
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}
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2016-09-09 14:32:33 +00:00
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/**
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* amdgpu_gtt_mgr_alloc - allocate new ranges
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*
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* @man: TTM memory type manager
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* @tbo: TTM BO we need this range for
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* @place: placement flags and restrictions
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* @mem: the resulting mem object
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*
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* Allocate the address space for a node.
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*/
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2017-08-22 14:58:07 +00:00
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static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *tbo,
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const struct ttm_place *place,
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struct ttm_mem_reg *mem)
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2016-09-09 14:32:33 +00:00
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{
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2017-07-07 11:16:37 +00:00
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struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
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2016-09-09 14:32:33 +00:00
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struct amdgpu_gtt_mgr *mgr = man->priv;
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2017-10-16 14:50:32 +00:00
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struct amdgpu_gtt_node *node = mem->mm_node;
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2017-02-02 21:04:38 +00:00
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enum drm_mm_insert_mode mode;
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2016-09-09 14:32:33 +00:00
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unsigned long fpfn, lpfn;
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int r;
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2017-10-27 12:17:09 +00:00
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if (amdgpu_gtt_mgr_has_gart_addr(mem))
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2016-09-09 14:32:33 +00:00
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return 0;
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if (place)
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fpfn = place->fpfn;
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else
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fpfn = 0;
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if (place && place->lpfn)
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lpfn = place->lpfn;
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else
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2017-07-07 11:16:37 +00:00
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lpfn = adev->gart.num_cpu_pages;
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2016-09-09 14:32:33 +00:00
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2017-02-02 21:04:38 +00:00
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mode = DRM_MM_INSERT_BEST;
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if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
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mode = DRM_MM_INSERT_HIGH;
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2016-09-09 14:32:33 +00:00
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spin_lock(&mgr->lock);
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2017-10-16 14:50:32 +00:00
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r = drm_mm_insert_node_in_range(&mgr->mm, &node->node, mem->num_pages,
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mem->page_alignment, 0, fpfn, lpfn,
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mode);
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2016-09-09 14:32:33 +00:00
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spin_unlock(&mgr->lock);
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2017-08-22 14:58:07 +00:00
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if (!r)
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2017-10-16 14:50:32 +00:00
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mem->start = node->node.start;
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2016-09-09 14:32:33 +00:00
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return r;
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}
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/**
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* amdgpu_gtt_mgr_new - allocate a new node
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*
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* @man: TTM memory type manager
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* @tbo: TTM BO we need this range for
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* @place: placement flags and restrictions
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* @mem: the resulting mem object
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*
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* Dummy, allocate the node but no space for it yet.
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*/
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static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
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struct ttm_buffer_object *tbo,
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const struct ttm_place *place,
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struct ttm_mem_reg *mem)
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{
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struct amdgpu_gtt_mgr *mgr = man->priv;
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2017-10-16 14:50:32 +00:00
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struct amdgpu_gtt_node *node;
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2016-09-09 14:32:33 +00:00
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int r;
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spin_lock(&mgr->lock);
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2017-10-16 09:18:54 +00:00
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if ((&tbo->mem == mem || tbo->mem.mem_type != TTM_PL_TT) &&
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atomic64_read(&mgr->available) < mem->num_pages) {
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2016-09-09 14:32:33 +00:00
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spin_unlock(&mgr->lock);
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return 0;
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}
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2017-08-07 15:11:33 +00:00
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atomic64_sub(mem->num_pages, &mgr->available);
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2016-09-09 14:32:33 +00:00
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spin_unlock(&mgr->lock);
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node = kzalloc(sizeof(*node), GFP_KERNEL);
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2016-12-02 08:51:20 +00:00
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if (!node) {
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r = -ENOMEM;
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goto err_out;
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}
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2016-09-09 14:32:33 +00:00
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2017-10-16 14:50:32 +00:00
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node->node.start = AMDGPU_BO_INVALID_OFFSET;
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node->node.size = mem->num_pages;
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node->tbo = tbo;
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2016-09-09 14:32:33 +00:00
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mem->mm_node = node;
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if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
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r = amdgpu_gtt_mgr_alloc(man, tbo, place, mem);
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if (unlikely(r)) {
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kfree(node);
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mem->mm_node = NULL;
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2016-12-02 08:51:20 +00:00
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r = 0;
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goto err_out;
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2016-09-09 14:32:33 +00:00
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}
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} else {
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2017-10-16 14:50:32 +00:00
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mem->start = node->node.start;
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2016-09-09 14:32:33 +00:00
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}
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return 0;
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2016-12-02 08:51:20 +00:00
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err_out:
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2017-08-07 15:11:33 +00:00
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atomic64_add(mem->num_pages, &mgr->available);
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2016-12-02 08:51:20 +00:00
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return r;
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2016-09-09 14:32:33 +00:00
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}
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/**
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* amdgpu_gtt_mgr_del - free ranges
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*
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* @man: TTM memory type manager
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* @tbo: TTM BO we need this range for
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* @place: placement flags and restrictions
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* @mem: TTM memory object
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*
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* Free the allocated GTT again.
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*/
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static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man,
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struct ttm_mem_reg *mem)
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{
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struct amdgpu_gtt_mgr *mgr = man->priv;
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2017-10-16 14:50:32 +00:00
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struct amdgpu_gtt_node *node = mem->mm_node;
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2016-09-09 14:32:33 +00:00
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if (!node)
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return;
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spin_lock(&mgr->lock);
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2017-10-16 14:50:32 +00:00
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if (node->node.start != AMDGPU_BO_INVALID_OFFSET)
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drm_mm_remove_node(&node->node);
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2016-09-09 14:32:33 +00:00
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spin_unlock(&mgr->lock);
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2017-08-07 15:11:33 +00:00
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atomic64_add(mem->num_pages, &mgr->available);
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2016-09-09 14:32:33 +00:00
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kfree(node);
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mem->mm_node = NULL;
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}
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2017-08-07 15:11:33 +00:00
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/**
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* amdgpu_gtt_mgr_usage - return usage of GTT domain
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*
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* @man: TTM memory type manager
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*
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* Return how many bytes are used in the GTT domain
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*/
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uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man)
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{
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struct amdgpu_gtt_mgr *mgr = man->priv;
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2017-10-16 09:18:54 +00:00
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s64 result = man->size - atomic64_read(&mgr->available);
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2017-08-07 15:11:33 +00:00
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2017-10-16 09:18:54 +00:00
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return (result > 0 ? result : 0) * PAGE_SIZE;
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2017-08-07 15:11:33 +00:00
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}
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2017-10-16 14:50:32 +00:00
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int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man)
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{
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struct amdgpu_gtt_mgr *mgr = man->priv;
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struct amdgpu_gtt_node *node;
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struct drm_mm_node *mm_node;
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int r = 0;
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spin_lock(&mgr->lock);
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drm_mm_for_each_node(mm_node, &mgr->mm) {
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node = container_of(mm_node, struct amdgpu_gtt_node, node);
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r = amdgpu_ttm_recover_gart(node->tbo);
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if (r)
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break;
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}
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spin_unlock(&mgr->lock);
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return r;
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}
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2016-09-09 14:32:33 +00:00
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/**
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* amdgpu_gtt_mgr_debug - dump VRAM table
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*
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* @man: TTM memory type manager
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2017-08-07 09:13:41 +00:00
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* @printer: DRM printer to use
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2016-09-09 14:32:33 +00:00
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*
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* Dump the table content using printk.
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*/
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static void amdgpu_gtt_mgr_debug(struct ttm_mem_type_manager *man,
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2017-08-07 09:13:41 +00:00
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struct drm_printer *printer)
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2016-09-09 14:32:33 +00:00
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{
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struct amdgpu_gtt_mgr *mgr = man->priv;
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spin_lock(&mgr->lock);
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2017-08-07 09:13:41 +00:00
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drm_mm_print(&mgr->mm, printer);
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2016-09-09 14:32:33 +00:00
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spin_unlock(&mgr->lock);
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2017-08-07 13:47:51 +00:00
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2017-10-16 09:18:54 +00:00
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drm_printf(printer, "man size:%llu pages, gtt available:%lld pages, usage:%lluMB\n",
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2017-08-07 15:11:33 +00:00
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man->size, (u64)atomic64_read(&mgr->available),
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amdgpu_gtt_mgr_usage(man) >> 20);
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2016-09-09 14:32:33 +00:00
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}
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const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func = {
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2016-12-17 01:02:32 +00:00
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.init = amdgpu_gtt_mgr_init,
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.takedown = amdgpu_gtt_mgr_fini,
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.get_node = amdgpu_gtt_mgr_new,
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.put_node = amdgpu_gtt_mgr_del,
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.debug = amdgpu_gtt_mgr_debug
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2016-09-09 14:32:33 +00:00
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};
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