2019-06-03 05:44:50 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2013-04-08 16:17:03 +00:00
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/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ASM_ESR_H
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#define __ASM_ESR_H
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2015-07-24 15:37:47 +00:00
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#include <asm/memory.h>
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2017-06-09 11:49:30 +00:00
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#include <asm/sysreg.h>
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2015-07-24 15:37:47 +00:00
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_UNKNOWN (0x00)
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#define ESR_ELx_EC_WFx (0x01)
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/* Unallocated EC: 0x02 */
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#define ESR_ELx_EC_CP15_32 (0x03)
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#define ESR_ELx_EC_CP15_64 (0x04)
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#define ESR_ELx_EC_CP14_MR (0x05)
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#define ESR_ELx_EC_CP14_LS (0x06)
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#define ESR_ELx_EC_FP_ASIMD (0x07)
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2018-12-07 18:39:19 +00:00
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#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
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2018-12-07 18:39:20 +00:00
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#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
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/* Unallocated EC: 0x0A - 0x0B */
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_CP14_64 (0x0C)
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2020-03-16 16:50:45 +00:00
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#define ESR_ELx_EC_BTI (0x0D)
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_ILL (0x0E)
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/* Unallocated EC: 0x0F - 0x10 */
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#define ESR_ELx_EC_SVC32 (0x11)
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2018-12-07 18:39:19 +00:00
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#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
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#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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/* Unallocated EC: 0x14 */
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#define ESR_ELx_EC_SVC64 (0x15)
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2018-12-07 18:39:19 +00:00
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#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
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#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_SYS64 (0x18)
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2017-10-31 15:51:00 +00:00
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#define ESR_ELx_EC_SVE (0x19)
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2019-07-16 07:14:19 +00:00
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#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
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2020-09-14 08:36:53 +00:00
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/* Unallocated EC: 0x1B */
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#define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */
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2022-04-19 11:22:13 +00:00
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#define ESR_ELx_EC_SME (0x1D)
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/* Unallocated EC: 0x1E */
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2018-12-07 18:39:19 +00:00
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#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_IABT_LOW (0x20)
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#define ESR_ELx_EC_IABT_CUR (0x21)
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#define ESR_ELx_EC_PC_ALIGN (0x22)
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/* Unallocated EC: 0x23 */
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#define ESR_ELx_EC_DABT_LOW (0x24)
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#define ESR_ELx_EC_DABT_CUR (0x25)
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#define ESR_ELx_EC_SP_ALIGN (0x26)
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2023-05-09 14:22:31 +00:00
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#define ESR_ELx_EC_MOPS (0x27)
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_FP_EXC32 (0x28)
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/* Unallocated EC: 0x29 - 0x2B */
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#define ESR_ELx_EC_FP_EXC64 (0x2C)
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/* Unallocated EC: 0x2D - 0x2E */
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#define ESR_ELx_EC_SERROR (0x2F)
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#define ESR_ELx_EC_BREAKPT_LOW (0x30)
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#define ESR_ELx_EC_BREAKPT_CUR (0x31)
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#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
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#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
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#define ESR_ELx_EC_WATCHPT_LOW (0x34)
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#define ESR_ELx_EC_WATCHPT_CUR (0x35)
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/* Unallocated EC: 0x36 - 0x37 */
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#define ESR_ELx_EC_BKPT32 (0x38)
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/* Unallocated EC: 0x39 */
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2018-12-07 18:39:19 +00:00
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#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
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2020-03-09 07:21:42 +00:00
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/* Unallocated EC: 0x3B */
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_BRK64 (0x3C)
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/* Unallocated EC: 0x3D - 0x3F */
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#define ESR_ELx_EC_MAX (0x3F)
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#define ESR_ELx_EC_SHIFT (26)
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KVM: arm64: Extract ESR_ELx.EC only
Since ARMv8.0 the upper 32 bits of ESR_ELx have been RES0, and recently
some of the upper bits gained a meaning and can be non-zero. For
example, when FEAT_LS64 is implemented, ESR_ELx[36:32] contain ISS2,
which for an ST64BV or ST64BV0 can be non-zero. This can be seen in ARM
DDI 0487G.b, page D13-3145, section D13.2.37.
Generally, we must not rely on RES0 bit remaining zero in future, and
when extracting ESR_ELx.EC we must mask out all other bits.
All C code uses the ESR_ELx_EC() macro, which masks out the irrelevant
bits, and therefore no alterations are required to C code to avoid
consuming irrelevant bits.
In a couple of places the KVM assembly extracts ESR_ELx.EC using LSR on
an X register, and so could in theory consume previously RES0 bits. In
both cases this is for comparison with EC values ESR_ELx_EC_HVC32 and
ESR_ELx_EC_HVC64, for which the upper bits of ESR_ELx must currently be
zero, but this could change in future.
This patch adjusts the KVM vectors to use UBFX rather than LSR to
extract ESR_ELx.EC, ensuring these are robust to future additions to
ESR_ELx.
Cc: stable@vger.kernel.org
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211103110545.4613-1-mark.rutland@arm.com
2021-11-03 11:05:45 +00:00
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#define ESR_ELx_EC_WIDTH (6)
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
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#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
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2016-05-31 11:33:01 +00:00
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#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
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arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
|
|
|
|
2017-08-04 08:31:42 +00:00
|
|
|
#define ESR_ELx_IL_SHIFT (25)
|
|
|
|
|
#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
|
2023-05-11 06:05:14 +00:00
|
|
|
#define ESR_ELx_ISS_MASK (GENMASK(24, 0))
|
2022-04-19 11:22:24 +00:00
|
|
|
#define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK)
|
2023-05-11 06:05:15 +00:00
|
|
|
#define ESR_ELx_ISS2_SHIFT (32)
|
|
|
|
|
#define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))
|
|
|
|
|
#define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
|
2016-09-09 13:07:15 +00:00
|
|
|
|
|
|
|
|
/* ISS field definitions shared by different classes */
|
2017-08-04 08:31:42 +00:00
|
|
|
#define ESR_ELx_WNR_SHIFT (6)
|
|
|
|
|
#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
|
2016-09-09 13:07:15 +00:00
|
|
|
|
2018-01-15 19:38:57 +00:00
|
|
|
/* Asynchronous Error Type */
|
|
|
|
|
#define ESR_ELx_IDS_SHIFT (24)
|
|
|
|
|
#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
|
|
|
|
|
#define ESR_ELx_AET_SHIFT (10)
|
|
|
|
|
#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
|
|
|
|
|
#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
|
|
|
|
|
#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
|
|
|
|
|
#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
|
|
|
|
|
#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
|
|
|
|
|
|
2016-09-09 13:07:15 +00:00
|
|
|
/* Shared ISS field definitions for Data/Instruction aborts */
|
2017-08-04 08:31:42 +00:00
|
|
|
#define ESR_ELx_SET_SHIFT (11)
|
|
|
|
|
#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
|
|
|
|
|
#define ESR_ELx_FnV_SHIFT (10)
|
|
|
|
|
#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
|
|
|
|
|
#define ESR_ELx_EA_SHIFT (9)
|
|
|
|
|
#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
|
|
|
|
|
#define ESR_ELx_S1PTW_SHIFT (7)
|
|
|
|
|
#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
|
2016-09-09 13:07:15 +00:00
|
|
|
|
|
|
|
|
/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
|
|
|
|
|
#define ESR_ELx_FSC (0x3F)
|
|
|
|
|
#define ESR_ELx_FSC_TYPE (0x3C)
|
2020-12-01 20:10:34 +00:00
|
|
|
#define ESR_ELx_FSC_LEVEL (0x03)
|
2016-09-09 13:07:15 +00:00
|
|
|
#define ESR_ELx_FSC_EXTABT (0x10)
|
2020-12-22 20:01:28 +00:00
|
|
|
#define ESR_ELx_FSC_MTE (0x11)
|
2018-01-15 19:38:57 +00:00
|
|
|
#define ESR_ELx_FSC_SERROR (0x11)
|
2016-09-09 13:07:15 +00:00
|
|
|
#define ESR_ELx_FSC_ACCESS (0x08)
|
|
|
|
|
#define ESR_ELx_FSC_FAULT (0x04)
|
|
|
|
|
#define ESR_ELx_FSC_PERM (0x0C)
|
2024-02-14 12:29:14 +00:00
|
|
|
#define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n))
|
2022-12-20 14:49:30 +00:00
|
|
|
#define ESR_ELx_FSC_SECC (0x18)
|
2024-02-14 12:29:14 +00:00
|
|
|
#define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n))
|
2016-09-09 13:07:15 +00:00
|
|
|
|
|
|
|
|
/* ISS field definitions for Data Aborts */
|
2017-08-04 08:31:42 +00:00
|
|
|
#define ESR_ELx_ISV_SHIFT (24)
|
|
|
|
|
#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
|
arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
|
|
|
#define ESR_ELx_SAS_SHIFT (22)
|
|
|
|
|
#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
|
2017-08-04 08:31:42 +00:00
|
|
|
#define ESR_ELx_SSE_SHIFT (21)
|
|
|
|
|
#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
|
arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
|
|
|
#define ESR_ELx_SRT_SHIFT (16)
|
|
|
|
|
#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
|
2017-08-04 08:31:42 +00:00
|
|
|
#define ESR_ELx_SF_SHIFT (15)
|
|
|
|
|
#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
|
|
|
|
|
#define ESR_ELx_AR_SHIFT (14)
|
|
|
|
|
#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
|
|
|
|
|
#define ESR_ELx_CM_SHIFT (8)
|
|
|
|
|
#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
|
2016-09-09 13:07:15 +00:00
|
|
|
|
2023-05-11 06:05:15 +00:00
|
|
|
/* ISS2 field definitions for Data Aborts */
|
|
|
|
|
#define ESR_ELx_TnD_SHIFT (10)
|
|
|
|
|
#define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
|
|
|
|
|
#define ESR_ELx_TagAccess_SHIFT (9)
|
|
|
|
|
#define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
|
|
|
|
|
#define ESR_ELx_GCS_SHIFT (8)
|
|
|
|
|
#define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
|
|
|
|
|
#define ESR_ELx_Overlay_SHIFT (6)
|
|
|
|
|
#define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
|
|
|
|
|
#define ESR_ELx_DirtyBit_SHIFT (5)
|
|
|
|
|
#define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
|
|
|
|
|
#define ESR_ELx_Xs_SHIFT (0)
|
|
|
|
|
#define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))
|
|
|
|
|
|
2016-09-09 13:07:15 +00:00
|
|
|
/* ISS field definitions for exceptions taken in to Hyp */
|
arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
|
|
|
#define ESR_ELx_CV (UL(1) << 24)
|
|
|
|
|
#define ESR_ELx_COND_SHIFT (20)
|
|
|
|
|
#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
|
2022-04-19 18:27:47 +00:00
|
|
|
#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
|
|
|
|
|
#define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
|
2022-04-19 18:27:46 +00:00
|
|
|
#define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
|
|
|
|
|
#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
|
2018-10-01 11:19:43 +00:00
|
|
|
#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
|
arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
|
|
|
#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
|
2022-04-25 11:44:40 +00:00
|
|
|
#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
|
arm64: introduce common ESR_ELx_* definitions
Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
the encodings are common. While encodings are architected to refer to
the current EL or a lower EL, the macros refer to particular ELs (e.g.
ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
and their naming is misleading.
This patch introduces common ESR_ELx_* macros that can be used in all
cases, in preparation for later patches which will migrate existing
users over. Some additional cleanups are made in the process:
* Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
replaced with more general _LOW and _CUR suffixes, matching the
architectural intent.
* ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
EC encoding covers traps from both WFE and WFI. Similarly,
ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
* Multi-bit fields are given consistently named _SHIFT and _MASK macros.
* UL() is used for compatiblity with assembly files.
* Comments are added for currently unallocated ESR_ELx.EC encodings.
For fields other than ESR_ELx.EC, macros are only implemented for fields
for which there is already an ESR_EL{1,2}_* macro.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
2014-11-24 12:03:32 +00:00
|
|
|
|
2018-01-15 19:38:59 +00:00
|
|
|
#define DISR_EL1_IDS (UL(1) << 24)
|
|
|
|
|
/*
|
|
|
|
|
* DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
|
|
|
|
|
* different things in the future...
|
|
|
|
|
*/
|
|
|
|
|
#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
|
|
|
|
|
|
2015-07-24 15:37:45 +00:00
|
|
|
/* ESR value templates for specific events */
|
2022-04-19 18:27:46 +00:00
|
|
|
#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \
|
|
|
|
|
(ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
|
2018-10-01 11:19:43 +00:00
|
|
|
#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
|
|
|
|
|
ESR_ELx_WFx_ISS_WFI)
|
2015-07-24 15:37:45 +00:00
|
|
|
|
|
|
|
|
/* BRK instruction trap from AArch64 state */
|
2019-02-26 15:06:42 +00:00
|
|
|
#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
|
2015-07-24 15:37:45 +00:00
|
|
|
|
2016-09-09 13:07:15 +00:00
|
|
|
/* ISS field definitions for System instruction traps */
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP1_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP2_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRN_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRM_MASK)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
|
|
|
|
|
(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
|
|
|
|
|
((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
|
|
|
|
|
((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
|
|
|
|
|
((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
|
|
|
|
|
((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
|
2016-09-09 13:07:16 +00:00
|
|
|
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_MASK)
|
2018-09-20 04:06:19 +00:00
|
|
|
#define ESR_ELx_SYS64_ISS_RT(esr) \
|
|
|
|
|
(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
|
2016-09-09 13:07:15 +00:00
|
|
|
/*
|
|
|
|
|
* User space cache operations have the following sysreg encoding
|
|
|
|
|
* in System instructions.
|
2019-04-09 09:52:42 +00:00
|
|
|
* op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
|
2016-09-09 13:07:15 +00:00
|
|
|
*/
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
|
2019-04-09 09:52:42 +00:00
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
|
2017-07-25 10:55:41 +00:00
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
|
2016-09-09 13:07:15 +00:00
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP1_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP2_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRN_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_MASK)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
|
|
|
|
|
(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_WRITE)
|
2018-09-20 04:06:21 +00:00
|
|
|
/*
|
|
|
|
|
* User space MRS operations which are supported for emulation
|
|
|
|
|
* have the following sysreg encoding in System instructions.
|
|
|
|
|
* op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
|
|
|
|
|
*/
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP1_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRN_MASK | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_MASK)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
|
|
|
|
|
(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_READ)
|
2016-09-09 13:07:16 +00:00
|
|
|
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
|
|
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_READ)
|
|
|
|
|
|
2017-02-01 11:48:58 +00:00
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_READ)
|
2017-04-24 08:04:03 +00:00
|
|
|
|
2021-10-17 12:42:24 +00:00
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_READ)
|
|
|
|
|
|
2017-04-24 08:04:03 +00:00
|
|
|
#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
|
|
|
|
|
ESR_ELx_SYS64_ISS_DIR_READ)
|
|
|
|
|
|
2017-06-09 11:49:30 +00:00
|
|
|
#define esr_sys64_to_sysreg(e) \
|
|
|
|
|
sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP0_SHIFT), \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP1_SHIFT), \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRN_SHIFT), \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRM_SHIFT), \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP2_SHIFT))
|
|
|
|
|
|
|
|
|
|
#define esr_cp15_to_sysreg(e) \
|
|
|
|
|
sys_reg(3, \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP1_SHIFT), \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRN_SHIFT), \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_CRM_SHIFT), \
|
|
|
|
|
(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
|
|
|
|
|
ESR_ELx_SYS64_ISS_OP2_SHIFT))
|
|
|
|
|
|
2023-02-09 17:58:13 +00:00
|
|
|
/* ISS field definitions for ERET/ERETAA/ERETAB trapping */
|
|
|
|
|
#define ESR_ELx_ERET_ISS_ERET 0x2
|
|
|
|
|
#define ESR_ELx_ERET_ISS_ERETA 0x1
|
|
|
|
|
|
2018-03-01 17:44:07 +00:00
|
|
|
/*
|
|
|
|
|
* ISS field definitions for floating-point exception traps
|
|
|
|
|
* (FP_EXC_32/FP_EXC_64).
|
|
|
|
|
*
|
|
|
|
|
* (The FPEXC_* constants are used instead for common bits.)
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
|
|
|
|
|
|
2018-09-27 16:15:28 +00:00
|
|
|
/*
|
|
|
|
|
* ISS field definitions for CP15 accesses
|
|
|
|
|
*/
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
|
|
|
|
|
ESR_ELx_CP15_32_ISS_OP2_MASK | \
|
|
|
|
|
ESR_ELx_CP15_32_ISS_CRN_MASK | \
|
|
|
|
|
ESR_ELx_CP15_32_ISS_CRM_MASK | \
|
|
|
|
|
ESR_ELx_CP15_32_ISS_DIR_MASK)
|
|
|
|
|
#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
|
|
|
|
|
(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
|
|
|
|
|
((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
|
|
|
|
|
((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
|
|
|
|
|
((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
|
|
|
|
|
(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
|
|
|
|
|
((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
|
|
|
|
|
ESR_ELx_CP15_64_ISS_CRM_MASK | \
|
|
|
|
|
ESR_ELx_CP15_64_ISS_DIR_MASK)
|
|
|
|
|
|
2018-09-27 16:15:32 +00:00
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
|
|
|
|
|
ESR_ELx_CP15_64_ISS_DIR_READ)
|
|
|
|
|
|
2021-10-17 12:42:24 +00:00
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
|
|
|
|
|
ESR_ELx_CP15_64_ISS_DIR_READ)
|
|
|
|
|
|
2018-09-27 16:15:33 +00:00
|
|
|
#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
|
|
|
|
|
ESR_ELx_CP15_32_ISS_DIR_READ)
|
|
|
|
|
|
2022-04-19 11:22:13 +00:00
|
|
|
/*
|
|
|
|
|
* ISS values for SME traps
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define ESR_ELx_SME_ISS_SME_DISABLED 0
|
|
|
|
|
#define ESR_ELx_SME_ISS_ILL 1
|
|
|
|
|
#define ESR_ELx_SME_ISS_SM_DISABLED 2
|
|
|
|
|
#define ESR_ELx_SME_ISS_ZA_DISABLED 3
|
2023-01-16 16:04:40 +00:00
|
|
|
#define ESR_ELx_SME_ISS_ZT_DISABLED 4
|
2022-04-19 11:22:13 +00:00
|
|
|
|
2023-05-09 14:22:31 +00:00
|
|
|
/* ISS field definitions for MOPS exceptions */
|
|
|
|
|
#define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
|
|
|
|
|
#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
|
|
|
|
|
#define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
|
|
|
|
|
#define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
|
|
|
|
|
#define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
|
|
|
|
|
#define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
|
|
|
|
|
#define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
|
|
|
|
|
|
2014-11-18 12:16:30 +00:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
#include <asm/types.h>
|
|
|
|
|
|
arm64: Treat ESR_ELx as a 64-bit register
In the initial release of the ARM Architecture Reference Manual for
ARMv8-A, the ESR_ELx registers were defined as 32-bit registers. This
changed in 2018 with version D.a (ARM DDI 0487D.a) of the architecture,
when they became 64-bit registers, with bits [63:32] defined as RES0. In
version G.a, a new field was added to ESR_ELx, ISS2, which covers bits
[36:32]. This field is used when the Armv8.7 extension FEAT_LS64 is
implemented.
As a result of the evolution of the register width, Linux stores it as
both a 64-bit value and a 32-bit value, which hasn't affected correctness
so far as Linux only uses the lower 32 bits of the register.
Make the register type consistent and always treat it as 64-bit wide. The
register is redefined as an "unsigned long", which is an unsigned
double-word (64-bit quantity) for the LP64 machine (aapcs64 [1], Table 1,
page 14). The type was chosen because "unsigned int" is the most frequent
type for ESR_ELx and because FAR_ELx, which is used together with ESR_ELx
in exception handling, is also declared as "unsigned long". The 64-bit type
also makes adding support for architectural features that use fields above
bit 31 easier in the future.
The KVM hypervisor will receive a similar update in a subsequent patch.
[1] https://github.com/ARM-software/abi-aa/releases/download/2021Q3/aapcs64.pdf
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425114444.368693-4-alexandru.elisei@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-04-25 11:44:42 +00:00
|
|
|
static inline bool esr_is_data_abort(unsigned long esr)
|
2017-08-04 08:31:42 +00:00
|
|
|
{
|
arm64: Treat ESR_ELx as a 64-bit register
In the initial release of the ARM Architecture Reference Manual for
ARMv8-A, the ESR_ELx registers were defined as 32-bit registers. This
changed in 2018 with version D.a (ARM DDI 0487D.a) of the architecture,
when they became 64-bit registers, with bits [63:32] defined as RES0. In
version G.a, a new field was added to ESR_ELx, ISS2, which covers bits
[36:32]. This field is used when the Armv8.7 extension FEAT_LS64 is
implemented.
As a result of the evolution of the register width, Linux stores it as
both a 64-bit value and a 32-bit value, which hasn't affected correctness
so far as Linux only uses the lower 32 bits of the register.
Make the register type consistent and always treat it as 64-bit wide. The
register is redefined as an "unsigned long", which is an unsigned
double-word (64-bit quantity) for the LP64 machine (aapcs64 [1], Table 1,
page 14). The type was chosen because "unsigned int" is the most frequent
type for ESR_ELx and because FAR_ELx, which is used together with ESR_ELx
in exception handling, is also declared as "unsigned long". The 64-bit type
also makes adding support for architectural features that use fields above
bit 31 easier in the future.
The KVM hypervisor will receive a similar update in a subsequent patch.
[1] https://github.com/ARM-software/abi-aa/releases/download/2021Q3/aapcs64.pdf
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425114444.368693-4-alexandru.elisei@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-04-25 11:44:42 +00:00
|
|
|
const unsigned long ec = ESR_ELx_EC(esr);
|
2017-08-04 08:31:42 +00:00
|
|
|
|
|
|
|
|
return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
|
|
|
|
|
}
|
|
|
|
|
|
2023-11-28 14:04:01 +00:00
|
|
|
static inline bool esr_fsc_is_translation_fault(unsigned long esr)
|
|
|
|
|
{
|
2024-02-14 12:29:14 +00:00
|
|
|
/* Translation fault, level -1 */
|
|
|
|
|
if ((esr & ESR_ELx_FSC) == 0b101011)
|
|
|
|
|
return true;
|
2023-11-28 14:04:01 +00:00
|
|
|
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_FAULT;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool esr_fsc_is_permission_fault(unsigned long esr)
|
|
|
|
|
{
|
|
|
|
|
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_PERM;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
|
|
|
|
|
{
|
|
|
|
|
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_ACCESS;
|
|
|
|
|
}
|
|
|
|
|
|
arm64: Treat ESR_ELx as a 64-bit register
In the initial release of the ARM Architecture Reference Manual for
ARMv8-A, the ESR_ELx registers were defined as 32-bit registers. This
changed in 2018 with version D.a (ARM DDI 0487D.a) of the architecture,
when they became 64-bit registers, with bits [63:32] defined as RES0. In
version G.a, a new field was added to ESR_ELx, ISS2, which covers bits
[36:32]. This field is used when the Armv8.7 extension FEAT_LS64 is
implemented.
As a result of the evolution of the register width, Linux stores it as
both a 64-bit value and a 32-bit value, which hasn't affected correctness
so far as Linux only uses the lower 32 bits of the register.
Make the register type consistent and always treat it as 64-bit wide. The
register is redefined as an "unsigned long", which is an unsigned
double-word (64-bit quantity) for the LP64 machine (aapcs64 [1], Table 1,
page 14). The type was chosen because "unsigned int" is the most frequent
type for ESR_ELx and because FAR_ELx, which is used together with ESR_ELx
in exception handling, is also declared as "unsigned long". The 64-bit type
also makes adding support for architectural features that use fields above
bit 31 easier in the future.
The KVM hypervisor will receive a similar update in a subsequent patch.
[1] https://github.com/ARM-software/abi-aa/releases/download/2021Q3/aapcs64.pdf
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425114444.368693-4-alexandru.elisei@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-04-25 11:44:42 +00:00
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const char *esr_get_class_string(unsigned long esr);
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2014-11-18 12:16:30 +00:00
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#endif /* __ASSEMBLY */
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2013-04-08 16:17:03 +00:00
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#endif /* __ASM_ESR_H */
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