linux-stable/drivers/bus/mhi/ep/Kconfig

config MHI_BUS_EP
	tristate "Modem Host Interface (MHI) bus Endpoint implementation"
	help
	  Bus driver for MHI protocol. Modem Host Interface (MHI) is a
	  communication protocol used by a host processor to control
	  and communicate a modem device over a high speed peripheral
	  bus or shared memory.

	  MHI_BUS_EP implements the MHI protocol for the endpoint devices,
	  such as SDX55 modem connected to the host machine over PCIe.
bus: mhi: ep: Add support for registering MHI endpoint controllers This commit adds support for registering MHI endpoint controller drivers with the MHI endpoint stack. MHI endpoint controller drivers manage the interaction with the host machines (such as x86). They are also the MHI endpoint bus master in charge of managing the physical link between the host and endpoint device. Eventhough the MHI spec is bus agnostic, the current implementation is entirely based on PCIe bus. The endpoint controller driver encloses all information about the underlying physical bus like PCIe. The registration process involves parsing the channel configuration and allocating an MHI EP device. Channels used in the endpoint stack follows the perspective of the MHI host stack. i.e., UL - From host to endpoint DL - From endpoint to host Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220405135754.6622-2-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2022-04-05 13:57:37 +00:00			`config MHI_BUS_EP`
			`tristate "Modem Host Interface (MHI) bus Endpoint implementation"`
			`help`
			`Bus driver for MHI protocol. Modem Host Interface (MHI) is a`
			`communication protocol used by a host processor to control`
			`and communicate a modem device over a high speed peripheral`
			`bus or shared memory.`

			`MHI_BUS_EP implements the MHI protocol for the endpoint devices,`
			`such as SDX55 modem connected to the host machine over PCIe.`