2017-11-03 10:28:30 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2008-07-24 09:27:36 +00:00
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/*
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* MUSB OTG driver peripheral support
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*
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* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2006 by Texas Instruments
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* Copyright (C) 2006-2007 Nokia Corporation
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2009-11-18 19:51:18 +00:00
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* Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
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2008-07-24 09:27:36 +00:00
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2008-07-24 09:27:36 +00:00
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#include "musb_core.h"
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2016-06-30 17:12:27 +00:00
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#include "musb_trace.h"
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2008-07-24 09:27:36 +00:00
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/* ----------------------------------------------------------------------- */
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2011-01-04 11:47:02 +00:00
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#define is_buffer_mapped(req) (is_dma_capable() && \
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(req->map_state != UN_MAPPED))
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2010-11-15 10:24:01 +00:00
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/* Maps the buffer to dma */
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static inline void map_dma_buffer(struct musb_request *request,
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2011-01-04 11:47:02 +00:00
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struct musb *musb, struct musb_ep *musb_ep)
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2010-11-15 10:24:01 +00:00
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{
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2011-01-04 11:47:03 +00:00
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int compatible = true;
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struct dma_controller *dma = musb->dma_controller;
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2011-01-04 11:47:02 +00:00
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request->map_state = UN_MAPPED;
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if (!is_dma_capable() || !musb_ep->dma)
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return;
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2011-01-04 11:47:03 +00:00
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/* Check if DMA engine can handle this request.
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* DMA code must reject the USB request explicitly.
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* Default behaviour is to map the request.
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*/
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if (dma->is_compatible)
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compatible = dma->is_compatible(musb_ep->dma,
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musb_ep->packet_sz, request->request.buf,
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request->request.length);
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if (!compatible)
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return;
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2010-11-15 10:24:01 +00:00
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if (request->request.dma == DMA_ADDR_INVALID) {
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2013-08-13 17:35:43 +00:00
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dma_addr_t dma_addr;
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int ret;
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dma_addr = dma_map_single(
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2010-11-15 10:24:01 +00:00
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musb->controller,
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request->request.buf,
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request->request.length,
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request->tx
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? DMA_TO_DEVICE
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: DMA_FROM_DEVICE);
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2013-08-13 17:35:43 +00:00
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ret = dma_mapping_error(musb->controller, dma_addr);
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if (ret)
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return;
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request->request.dma = dma_addr;
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2011-01-04 11:47:02 +00:00
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request->map_state = MUSB_MAPPED;
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2010-11-15 10:24:01 +00:00
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} else {
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dma_sync_single_for_device(musb->controller,
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request->request.dma,
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request->request.length,
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request->tx
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? DMA_TO_DEVICE
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: DMA_FROM_DEVICE);
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2011-01-04 11:47:02 +00:00
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request->map_state = PRE_MAPPED;
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2010-11-15 10:24:01 +00:00
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}
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}
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/* Unmap the buffer from dma and maps it back to cpu */
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static inline void unmap_dma_buffer(struct musb_request *request,
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struct musb *musb)
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{
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2013-03-15 13:28:50 +00:00
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struct musb_ep *musb_ep = request->ep;
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if (!is_buffer_mapped(request) || !musb_ep->dma)
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2011-01-04 11:47:02 +00:00
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return;
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2010-11-15 10:24:01 +00:00
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if (request->request.dma == DMA_ADDR_INVALID) {
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2011-05-11 09:44:08 +00:00
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dev_vdbg(musb->controller,
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"not unmapping a never mapped buffer\n");
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2010-11-15 10:24:01 +00:00
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return;
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}
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2011-01-04 11:47:02 +00:00
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if (request->map_state == MUSB_MAPPED) {
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2010-11-15 10:24:01 +00:00
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dma_unmap_single(musb->controller,
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request->request.dma,
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request->request.length,
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request->tx
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? DMA_TO_DEVICE
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: DMA_FROM_DEVICE);
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request->request.dma = DMA_ADDR_INVALID;
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2011-01-04 11:47:02 +00:00
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} else { /* PRE_MAPPED */
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2010-11-15 10:24:01 +00:00
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dma_sync_single_for_cpu(musb->controller,
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request->request.dma,
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request->request.length,
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request->tx
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? DMA_TO_DEVICE
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: DMA_FROM_DEVICE);
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}
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2011-01-04 11:47:02 +00:00
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request->map_state = UN_MAPPED;
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2010-11-15 10:24:01 +00:00
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}
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2008-07-24 09:27:36 +00:00
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/*
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* Immediately complete a request.
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*
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* @param request the request to complete
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* @param status the status to complete the request with
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* Context: controller locked, IRQs blocked.
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*/
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void musb_g_giveback(
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struct musb_ep *ep,
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struct usb_request *request,
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int status)
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__releases(ep->musb->lock)
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__acquires(ep->musb->lock)
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{
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struct musb_request *req;
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struct musb *musb;
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int busy = ep->busy;
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req = to_musb_request(request);
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2011-02-16 10:40:05 +00:00
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list_del(&req->list);
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2008-07-24 09:27:36 +00:00
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if (req->request.status == -EINPROGRESS)
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req->request.status = status;
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musb = req->musb;
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ep->busy = 1;
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spin_unlock(&musb->lock);
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2013-03-15 13:28:50 +00:00
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if (!dma_mapping_error(&musb->g.dev, request->dma))
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unmap_dma_buffer(req, musb);
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2016-06-30 17:12:27 +00:00
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trace_musb_req_gb(req);
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2014-09-24 20:43:19 +00:00
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usb_gadget_giveback_request(&req->ep->end_point, &req->request);
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2008-07-24 09:27:36 +00:00
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spin_lock(&musb->lock);
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ep->busy = busy;
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}
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/* ----------------------------------------------------------------------- */
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/*
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* Abort requests queued to an endpoint using the status. Synchronous.
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* caller locked controller and blocked irqs, and selected this ep.
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*/
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static void nuke(struct musb_ep *ep, const int status)
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{
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2011-05-11 09:44:08 +00:00
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struct musb *musb = ep->musb;
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2008-07-24 09:27:36 +00:00
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struct musb_request *req = NULL;
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void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
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ep->busy = 1;
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if (is_dma_capable() && ep->dma) {
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struct dma_controller *c = ep->musb->dma_controller;
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int value;
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2009-03-27 01:27:47 +00:00
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2008-07-24 09:27:36 +00:00
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if (ep->is_in) {
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2009-03-27 01:27:47 +00:00
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/*
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* The programming guide says that we must not clear
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* the DMAMODE bit before DMAENAB, so we only
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* clear it in the second write...
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*/
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2008-07-24 09:27:36 +00:00
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musb_writew(epio, MUSB_TXCSR,
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2009-03-27 01:27:47 +00:00
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MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
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2008-07-24 09:27:36 +00:00
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musb_writew(epio, MUSB_TXCSR,
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0 | MUSB_TXCSR_FLUSHFIFO);
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} else {
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musb_writew(epio, MUSB_RXCSR,
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0 | MUSB_RXCSR_FLUSHFIFO);
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musb_writew(epio, MUSB_RXCSR,
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0 | MUSB_RXCSR_FLUSHFIFO);
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}
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value = c->channel_abort(ep->dma);
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2016-06-30 17:12:22 +00:00
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musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
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2008-07-24 09:27:36 +00:00
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c->channel_release(ep->dma);
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ep->dma = NULL;
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}
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2011-02-16 10:40:05 +00:00
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while (!list_empty(&ep->req_list)) {
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req = list_first_entry(&ep->req_list, struct musb_request, list);
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2008-07-24 09:27:36 +00:00
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musb_g_giveback(ep, &req->request, status);
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}
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}
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/* ----------------------------------------------------------------------- */
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/* Data transfers - pure PIO, pure DMA, or mixed mode */
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/*
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* This assumes the separate CPPI engine is responding to DMA requests
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* from the usb core ... sequenced a bit differently from mentor dma.
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*/
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static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
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{
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if (can_bulk_split(musb, ep->type))
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return ep->hw_ep->max_packet_sz_tx;
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else
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return ep->packet_sz;
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}
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/*
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* An endpoint is transmitting data. This can be called either from
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* the IRQ routine or from ep.queue() to kickstart a request on an
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* endpoint.
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*
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* Context: controller locked, IRQs blocked, endpoint selected
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*/
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static void txstate(struct musb *musb, struct musb_request *req)
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{
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u8 epnum = req->epnum;
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struct musb_ep *musb_ep;
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void __iomem *epio = musb->endpoints[epnum].regs;
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struct usb_request *request;
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u16 fifo_count = 0, csr;
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int use_dma = 0;
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musb_ep = req->ep;
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2012-05-18 20:48:04 +00:00
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/* Check if EP is disabled */
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if (!musb_ep->desc) {
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2016-06-30 17:12:22 +00:00
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musb_dbg(musb, "ep:%s disabled - ignore request",
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2012-05-18 20:48:04 +00:00
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musb_ep->end_point.name);
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return;
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}
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2008-07-24 09:27:36 +00:00
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/* we shouldn't get here while DMA is active ... but we do ... */
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if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
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2016-06-30 17:12:22 +00:00
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musb_dbg(musb, "dma pending...");
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2008-07-24 09:27:36 +00:00
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return;
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}
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/* read TXCSR before */
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csr = musb_readw(epio, MUSB_TXCSR);
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request = &req->request;
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fifo_count = min(max_ep_writesize(musb, musb_ep),
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(int)(request->length - request->actual));
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if (csr & MUSB_TXCSR_TXPKTRDY) {
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2016-06-30 17:12:22 +00:00
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musb_dbg(musb, "%s old packet still ready , txcsr %03x",
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2008-07-24 09:27:36 +00:00
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musb_ep->end_point.name, csr);
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return;
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}
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if (csr & MUSB_TXCSR_P_SENDSTALL) {
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2016-06-30 17:12:22 +00:00
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musb_dbg(musb, "%s stalling, txcsr %03x",
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2008-07-24 09:27:36 +00:00
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musb_ep->end_point.name, csr);
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return;
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}
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2016-06-30 17:12:22 +00:00
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musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
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2008-07-24 09:27:36 +00:00
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epnum, musb_ep->packet_sz, fifo_count,
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csr);
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#ifndef CONFIG_MUSB_PIO_ONLY
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2011-01-04 11:47:02 +00:00
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if (is_buffer_mapped(req)) {
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2008-07-24 09:27:36 +00:00
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struct dma_controller *c = musb->dma_controller;
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2010-09-20 07:32:06 +00:00
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size_t request_size;
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/* setup DMA, then program endpoint CSR */
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request_size = min_t(size_t, request->length - request->actual,
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musb_ep->dma->max_len);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2012-07-20 05:37:23 +00:00
|
|
|
use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* MUSB_TXCSR_P_ISO is still set correctly */
|
|
|
|
|
2015-08-06 15:47:16 +00:00
|
|
|
if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
|
2009-04-02 19:07:08 +00:00
|
|
|
if (request_size < musb_ep->packet_sz)
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep->dma->desired_mode = 0;
|
|
|
|
else
|
|
|
|
musb_ep->dma->desired_mode = 1;
|
|
|
|
|
|
|
|
use_dma = use_dma && c->channel_program(
|
|
|
|
musb_ep->dma, musb_ep->packet_sz,
|
|
|
|
musb_ep->dma->desired_mode,
|
2009-12-22 02:18:02 +00:00
|
|
|
request->dma + request->actual, request_size);
|
2008-07-24 09:27:36 +00:00
|
|
|
if (use_dma) {
|
|
|
|
if (musb_ep->dma->desired_mode == 0) {
|
2009-03-27 01:27:47 +00:00
|
|
|
/*
|
|
|
|
* We must not clear the DMAMODE bit
|
|
|
|
* before the DMAENAB bit -- and the
|
|
|
|
* latter doesn't always get cleared
|
|
|
|
* before we get here...
|
|
|
|
*/
|
|
|
|
csr &= ~(MUSB_TXCSR_AUTOSET
|
|
|
|
| MUSB_TXCSR_DMAENAB);
|
|
|
|
musb_writew(epio, MUSB_TXCSR, csr
|
|
|
|
| MUSB_TXCSR_P_WZC_BITS);
|
|
|
|
csr &= ~MUSB_TXCSR_DMAMODE;
|
2008-07-24 09:27:36 +00:00
|
|
|
csr |= (MUSB_TXCSR_DMAENAB |
|
|
|
|
MUSB_TXCSR_MODE);
|
|
|
|
/* against programming guide */
|
2010-09-24 10:44:04 +00:00
|
|
|
} else {
|
|
|
|
csr |= (MUSB_TXCSR_DMAENAB
|
2008-07-24 09:27:36 +00:00
|
|
|
| MUSB_TXCSR_DMAMODE
|
|
|
|
| MUSB_TXCSR_MODE);
|
2012-12-06 05:42:48 +00:00
|
|
|
/*
|
|
|
|
* Enable Autoset according to table
|
|
|
|
* below
|
|
|
|
* bulk_split hb_mult Autoset_Enable
|
|
|
|
* 0 0 Yes(Normal)
|
|
|
|
* 0 >0 No(High BW ISO)
|
|
|
|
* 1 0 Yes(HS bulk)
|
|
|
|
* 1 >0 Yes(FS bulk)
|
|
|
|
*/
|
|
|
|
if (!musb_ep->hb_mult ||
|
2015-12-10 20:50:12 +00:00
|
|
|
can_bulk_split(musb,
|
|
|
|
musb_ep->type))
|
2010-09-24 10:44:04 +00:00
|
|
|
csr |= MUSB_TXCSR_AUTOSET;
|
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
csr &= ~MUSB_TXCSR_P_UNDERRUN;
|
2010-09-24 10:44:04 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-01 19:29:27 +00:00
|
|
|
if (is_cppi_enabled(musb)) {
|
2013-08-13 17:38:23 +00:00
|
|
|
/* program endpoint CSR first, then setup DMA */
|
|
|
|
csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
|
|
|
|
csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
|
|
|
|
MUSB_TXCSR_MODE;
|
|
|
|
musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
|
|
|
|
~MUSB_TXCSR_P_UNDERRUN) | csr);
|
|
|
|
|
|
|
|
/* ensure writebuffer is empty */
|
|
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* NOTE host side sets DMAENAB later than this; both are
|
|
|
|
* OK since the transfer dma glue (between CPPI and
|
|
|
|
* Mentor fifos) just tells CPPI it could start. Data
|
|
|
|
* only moves to the USB TX fifo when both fifos are
|
|
|
|
* ready.
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* "mode" is irrelevant here; handle terminating ZLPs
|
|
|
|
* like PIO does, since the hardware RNDIS mode seems
|
|
|
|
* unreliable except for the
|
|
|
|
* last-packet-is-already-short case.
|
|
|
|
*/
|
|
|
|
use_dma = use_dma && c->channel_program(
|
|
|
|
musb_ep->dma, musb_ep->packet_sz,
|
|
|
|
0,
|
|
|
|
request->dma + request->actual,
|
|
|
|
request_size);
|
|
|
|
if (!use_dma) {
|
|
|
|
c->channel_release(musb_ep->dma);
|
|
|
|
musb_ep->dma = NULL;
|
|
|
|
csr &= ~MUSB_TXCSR_DMAENAB;
|
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
/* invariant: prequest->buf is non-null */
|
|
|
|
}
|
2015-05-01 19:29:27 +00:00
|
|
|
} else if (tusb_dma_omap(musb))
|
2013-08-13 17:38:23 +00:00
|
|
|
use_dma = use_dma && c->channel_program(
|
|
|
|
musb_ep->dma, musb_ep->packet_sz,
|
|
|
|
request->zero,
|
|
|
|
request->dma + request->actual,
|
|
|
|
request_size);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (!use_dma) {
|
2010-11-15 10:24:01 +00:00
|
|
|
/*
|
|
|
|
* Unmap the dma buffer back to cpu if dma channel
|
|
|
|
* programming fails
|
|
|
|
*/
|
2011-01-04 11:47:02 +00:00
|
|
|
unmap_dma_buffer(req, musb);
|
2010-11-15 10:24:01 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_write_fifo(musb_ep->hw_ep, fifo_count,
|
|
|
|
(u8 *) (request->buf + request->actual));
|
|
|
|
request->actual += fifo_count;
|
|
|
|
csr |= MUSB_TXCSR_TXPKTRDY;
|
|
|
|
csr &= ~MUSB_TXCSR_P_UNDERRUN;
|
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* host may already have the data when this message shows... */
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep->end_point.name, use_dma ? "dma" : "pio",
|
|
|
|
request->actual, request->length,
|
|
|
|
musb_readw(epio, MUSB_TXCSR),
|
|
|
|
fifo_count,
|
|
|
|
musb_readw(epio, MUSB_TXMAXP));
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIFO state update (e.g. data ready).
|
|
|
|
* Called from IRQ, with controller locked.
|
|
|
|
*/
|
|
|
|
void musb_g_tx(struct musb *musb, u8 epnum)
|
|
|
|
{
|
|
|
|
u16 csr;
|
2011-02-16 10:40:05 +00:00
|
|
|
struct musb_request *req;
|
2008-07-24 09:27:36 +00:00
|
|
|
struct usb_request *request;
|
|
|
|
u8 __iomem *mbase = musb->mregs;
|
|
|
|
struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
|
|
|
|
void __iomem *epio = musb->endpoints[epnum].regs;
|
|
|
|
struct dma_channel *dma;
|
|
|
|
|
|
|
|
musb_ep_select(mbase, epnum);
|
2011-02-16 10:40:05 +00:00
|
|
|
req = next_request(musb_ep);
|
|
|
|
request = &req->request;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
dma = is_dma_capable() ? musb_ep->dma : NULL;
|
2009-11-18 19:55:28 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
|
|
|
|
* probably rates reporting as a host error.
|
|
|
|
*/
|
|
|
|
if (csr & MUSB_TXCSR_P_SENTSTALL) {
|
|
|
|
csr |= MUSB_TXCSR_P_WZC_BITS;
|
|
|
|
csr &= ~MUSB_TXCSR_P_SENTSTALL;
|
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (csr & MUSB_TXCSR_P_UNDERRUN) {
|
|
|
|
/* We NAKed, no big deal... little reason to care. */
|
|
|
|
csr |= MUSB_TXCSR_P_WZC_BITS;
|
|
|
|
csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
|
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
2011-05-11 09:44:08 +00:00
|
|
|
dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
|
|
|
|
epnum, request);
|
2009-11-18 19:55:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
|
|
|
|
/*
|
|
|
|
* SHOULD NOT HAPPEN... has with CPPI though, after
|
|
|
|
* changing SENDSTALL (and other cases); harmless?
|
2008-07-24 09:27:36 +00:00
|
|
|
*/
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
|
2009-11-18 19:55:28 +00:00
|
|
|
return;
|
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2021-01-23 14:25:00 +00:00
|
|
|
if (req) {
|
2009-11-18 19:55:28 +00:00
|
|
|
|
2018-04-30 16:20:54 +00:00
|
|
|
trace_musb_req_tx(req);
|
|
|
|
|
2009-11-18 19:55:28 +00:00
|
|
|
if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
csr |= MUSB_TXCSR_P_WZC_BITS;
|
2009-11-18 19:55:28 +00:00
|
|
|
csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
|
2011-03-15 15:24:24 +00:00
|
|
|
MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
2009-11-18 19:55:28 +00:00
|
|
|
/* Ensure writebuffer is empty. */
|
|
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
|
|
request->actual += musb_ep->dma->actual_len;
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
|
2009-11-18 19:55:28 +00:00
|
|
|
epnum, csr, musb_ep->dma->actual_len, request);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
2010-09-24 10:44:14 +00:00
|
|
|
/*
|
|
|
|
* First, maybe a terminating short packet. Some DMA
|
|
|
|
* engines might handle this by themselves.
|
|
|
|
*/
|
2015-05-01 19:29:30 +00:00
|
|
|
if ((request->zero && request->length)
|
2010-09-24 10:44:14 +00:00
|
|
|
&& (request->length % musb_ep->packet_sz == 0)
|
2019-01-30 14:13:21 +00:00
|
|
|
&& (request->actual == request->length)) {
|
2015-05-01 19:29:30 +00:00
|
|
|
|
2010-09-24 10:44:14 +00:00
|
|
|
/*
|
|
|
|
* On DMA completion, FIFO may not be
|
|
|
|
* available yet...
|
|
|
|
*/
|
|
|
|
if (csr & MUSB_TXCSR_TXPKTRDY)
|
|
|
|
return;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2010-09-24 10:44:14 +00:00
|
|
|
musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
|
|
|
|
| MUSB_TXCSR_TXPKTRDY);
|
|
|
|
request->zero = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (request->actual == request->length) {
|
|
|
|
musb_g_giveback(musb_ep, request, 0);
|
2012-02-17 09:24:52 +00:00
|
|
|
/*
|
|
|
|
* In the giveback function the MUSB lock is
|
|
|
|
* released and acquired after sometime. During
|
|
|
|
* this time period the INDEX register could get
|
|
|
|
* changed by the gadget_queue function especially
|
|
|
|
* on SMP systems. Reselect the INDEX to be sure
|
|
|
|
* we are reading/modifying the right registers
|
|
|
|
*/
|
|
|
|
musb_ep_select(mbase, epnum);
|
2011-02-16 10:40:05 +00:00
|
|
|
req = musb_ep->desc ? next_request(musb_ep) : NULL;
|
|
|
|
if (!req) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s idle now",
|
2010-09-24 10:44:14 +00:00
|
|
|
musb_ep->end_point.name);
|
|
|
|
return;
|
2009-12-16 17:38:31 +00:00
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
2011-02-16 10:40:05 +00:00
|
|
|
txstate(musb, req);
|
2009-11-18 19:55:28 +00:00
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------ */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Context: controller locked, IRQs blocked, endpoint selected
|
|
|
|
*/
|
|
|
|
static void rxstate(struct musb *musb, struct musb_request *req)
|
|
|
|
{
|
|
|
|
const u8 epnum = req->epnum;
|
|
|
|
struct usb_request *request = &req->request;
|
2010-09-20 07:32:01 +00:00
|
|
|
struct musb_ep *musb_ep;
|
2008-07-24 09:27:36 +00:00
|
|
|
void __iomem *epio = musb->endpoints[epnum].regs;
|
2012-07-16 19:25:04 +00:00
|
|
|
unsigned len = 0;
|
|
|
|
u16 fifo_count;
|
2009-11-18 19:51:18 +00:00
|
|
|
u16 csr = musb_readw(epio, MUSB_RXCSR);
|
2010-09-20 07:32:01 +00:00
|
|
|
struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
|
2011-07-20 05:11:58 +00:00
|
|
|
u8 use_mode_1;
|
2010-09-20 07:32:01 +00:00
|
|
|
|
|
|
|
if (hw_ep->is_shared_fifo)
|
|
|
|
musb_ep = &hw_ep->ep_in;
|
|
|
|
else
|
|
|
|
musb_ep = &hw_ep->ep_out;
|
|
|
|
|
2012-07-16 19:25:04 +00:00
|
|
|
fifo_count = musb_ep->packet_sz;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2012-05-18 20:48:04 +00:00
|
|
|
/* Check if EP is disabled */
|
|
|
|
if (!musb_ep->desc) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "ep:%s disabled - ignore request",
|
2012-05-18 20:48:04 +00:00
|
|
|
musb_ep->end_point.name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-11-18 19:51:18 +00:00
|
|
|
/* We shouldn't get here while DMA is active, but we do... */
|
|
|
|
if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "DMA pending...");
|
2009-11-18 19:51:18 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (csr & MUSB_RXCSR_P_SENDSTALL) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s stalling, RXCSR %04x",
|
2009-11-18 19:51:18 +00:00
|
|
|
musb_ep->end_point.name, csr);
|
|
|
|
return;
|
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2015-05-01 19:29:27 +00:00
|
|
|
if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
struct dma_controller *c = musb->dma_controller;
|
|
|
|
struct dma_channel *channel = musb_ep->dma;
|
|
|
|
|
|
|
|
/* NOTE: CPPI won't actually stop advancing the DMA
|
|
|
|
* queue after short packet transfers, so this is almost
|
|
|
|
* always going to run as IRQ-per-packet DMA so that
|
|
|
|
* faults will be handled correctly.
|
|
|
|
*/
|
|
|
|
if (c->channel_program(channel,
|
|
|
|
musb_ep->packet_sz,
|
|
|
|
!request->short_not_ok,
|
|
|
|
request->dma + request->actual,
|
|
|
|
request->length - request->actual)) {
|
|
|
|
|
|
|
|
/* make sure that if an rxpkt arrived after the irq,
|
|
|
|
* the cppi engine will be ready to take it as soon
|
|
|
|
* as DMA is enabled
|
|
|
|
*/
|
|
|
|
csr &= ~(MUSB_RXCSR_AUTOCLEAR
|
|
|
|
| MUSB_RXCSR_DMAMODE);
|
|
|
|
csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (csr & MUSB_RXCSR_RXPKTRDY) {
|
2012-07-16 19:25:04 +00:00
|
|
|
fifo_count = musb_readw(epio, MUSB_RXCOUNT);
|
2011-07-20 05:11:58 +00:00
|
|
|
|
|
|
|
/*
|
2012-10-26 06:55:31 +00:00
|
|
|
* Enable Mode 1 on RX transfers only when short_not_ok flag
|
|
|
|
* is set. Currently short_not_ok flag is set only from
|
|
|
|
* file_storage and f_mass_storage drivers
|
2011-07-20 05:11:58 +00:00
|
|
|
*/
|
2012-10-26 06:55:31 +00:00
|
|
|
|
|
|
|
if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
|
2011-07-20 05:11:58 +00:00
|
|
|
use_mode_1 = 1;
|
|
|
|
else
|
|
|
|
use_mode_1 = 0;
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
if (request->actual < request->length) {
|
2015-08-06 15:47:16 +00:00
|
|
|
if (!is_buffer_mapped(req))
|
|
|
|
goto buffer_aint_mapped;
|
|
|
|
|
|
|
|
if (musb_dma_inventra(musb)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
struct dma_controller *c;
|
|
|
|
struct dma_channel *channel;
|
|
|
|
int use_dma = 0;
|
2013-02-06 08:19:15 +00:00
|
|
|
unsigned int transfer_size;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
c = musb->dma_controller;
|
|
|
|
channel = musb_ep->dma;
|
|
|
|
|
2012-10-26 06:55:31 +00:00
|
|
|
/* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
|
|
|
|
* mode 0 only. So we do not get endpoint interrupts due to DMA
|
|
|
|
* completion. We only get interrupts from DMA controller.
|
|
|
|
*
|
2021-05-08 07:21:56 +00:00
|
|
|
* We could operate in DMA mode 1 if we knew the size of the transfer
|
2012-10-26 06:55:31 +00:00
|
|
|
* in advance. For mass storage class, request->length = what the host
|
|
|
|
* sends, so that'd work. But for pretty much everything else,
|
|
|
|
* request->length is routinely more than what the host sends. For
|
|
|
|
* most these gadgets, end of is signified either by a short packet,
|
|
|
|
* or filling the last byte of the buffer. (Sending extra data in
|
|
|
|
* that last pckate should trigger an overflow fault.) But in mode 1,
|
|
|
|
* we don't get DMA completion interrupt for short packets.
|
|
|
|
*
|
|
|
|
* Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
|
|
|
|
* to get endpoint interrupt on every DMA req, but that didn't seem
|
|
|
|
* to work reliably.
|
|
|
|
*
|
|
|
|
* REVISIT an updated g_file_storage can set req->short_not_ok, which
|
|
|
|
* then becomes usable as a runtime "use mode 1" hint...
|
|
|
|
*/
|
|
|
|
|
2011-07-20 05:11:58 +00:00
|
|
|
/* Experimental: Mode1 works with mass storage use cases */
|
|
|
|
if (use_mode_1) {
|
2010-09-25 10:50:43 +00:00
|
|
|
csr |= MUSB_RXCSR_AUTOCLEAR;
|
2011-07-20 05:11:58 +00:00
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
csr |= MUSB_RXCSR_DMAENAB;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* this special sequence (enabling and then
|
|
|
|
* disabling MUSB_RXCSR_DMAMODE) is required
|
|
|
|
* to get DMAReq to activate
|
|
|
|
*/
|
|
|
|
musb_writew(epio, MUSB_RXCSR,
|
|
|
|
csr | MUSB_RXCSR_DMAMODE);
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
|
2013-02-06 08:19:15 +00:00
|
|
|
transfer_size = min_t(unsigned int,
|
|
|
|
request->length -
|
|
|
|
request->actual,
|
2012-08-07 13:26:32 +00:00
|
|
|
channel->max_len);
|
|
|
|
musb_ep->dma->desired_mode = 1;
|
2011-07-20 05:11:58 +00:00
|
|
|
} else {
|
|
|
|
if (!musb_ep->hb_mult &&
|
|
|
|
musb_ep->hw_ep->rx_double_buffered)
|
|
|
|
csr |= MUSB_RXCSR_AUTOCLEAR;
|
|
|
|
csr |= MUSB_RXCSR_DMAENAB;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2012-08-07 13:26:32 +00:00
|
|
|
transfer_size = min(request->length - request->actual,
|
2012-07-16 19:25:04 +00:00
|
|
|
(unsigned)fifo_count);
|
2012-08-07 13:26:32 +00:00
|
|
|
musb_ep->dma->desired_mode = 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
2012-08-07 13:26:32 +00:00
|
|
|
use_dma = c->channel_program(
|
|
|
|
channel,
|
|
|
|
musb_ep->packet_sz,
|
|
|
|
channel->desired_mode,
|
|
|
|
request->dma
|
|
|
|
+ request->actual,
|
|
|
|
transfer_size);
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
if (use_dma)
|
2011-03-22 14:55:56 +00:00
|
|
|
return;
|
|
|
|
}
|
2015-08-06 15:47:16 +00:00
|
|
|
|
|
|
|
if ((musb_dma_ux500(musb)) &&
|
2011-03-22 14:55:56 +00:00
|
|
|
(request->actual < request->length)) {
|
|
|
|
|
|
|
|
struct dma_controller *c;
|
|
|
|
struct dma_channel *channel;
|
2013-02-06 08:19:15 +00:00
|
|
|
unsigned int transfer_size = 0;
|
2011-03-22 14:55:56 +00:00
|
|
|
|
|
|
|
c = musb->dma_controller;
|
|
|
|
channel = musb_ep->dma;
|
|
|
|
|
|
|
|
/* In case first packet is short */
|
2012-07-16 19:25:04 +00:00
|
|
|
if (fifo_count < musb_ep->packet_sz)
|
|
|
|
transfer_size = fifo_count;
|
2011-03-22 14:55:56 +00:00
|
|
|
else if (request->short_not_ok)
|
2013-02-06 08:19:15 +00:00
|
|
|
transfer_size = min_t(unsigned int,
|
|
|
|
request->length -
|
2011-03-22 14:55:56 +00:00
|
|
|
request->actual,
|
|
|
|
channel->max_len);
|
|
|
|
else
|
2013-02-06 08:19:15 +00:00
|
|
|
transfer_size = min_t(unsigned int,
|
|
|
|
request->length -
|
2011-03-22 14:55:56 +00:00
|
|
|
request->actual,
|
2012-07-16 19:25:04 +00:00
|
|
|
(unsigned)fifo_count);
|
2011-03-22 14:55:56 +00:00
|
|
|
|
|
|
|
csr &= ~MUSB_RXCSR_DMAMODE;
|
|
|
|
csr |= (MUSB_RXCSR_DMAENAB |
|
|
|
|
MUSB_RXCSR_AUTOCLEAR);
|
|
|
|
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
|
|
|
|
if (transfer_size <= musb_ep->packet_sz) {
|
|
|
|
musb_ep->dma->desired_mode = 0;
|
|
|
|
} else {
|
|
|
|
musb_ep->dma->desired_mode = 1;
|
|
|
|
/* Mode must be set after DMAENAB */
|
|
|
|
csr |= MUSB_RXCSR_DMAMODE;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (c->channel_program(channel,
|
|
|
|
musb_ep->packet_sz,
|
|
|
|
channel->desired_mode,
|
|
|
|
request->dma
|
|
|
|
+ request->actual,
|
|
|
|
transfer_size))
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-07-16 19:25:04 +00:00
|
|
|
len = request->length - request->actual;
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep->end_point.name,
|
2012-07-16 19:25:04 +00:00
|
|
|
fifo_count, len,
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep->packet_sz);
|
|
|
|
|
2009-02-21 23:29:42 +00:00
|
|
|
fifo_count = min_t(unsigned, len, fifo_count);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2015-08-06 15:47:16 +00:00
|
|
|
if (tusb_dma_omap(musb)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
struct dma_controller *c = musb->dma_controller;
|
|
|
|
struct dma_channel *channel = musb_ep->dma;
|
|
|
|
u32 dma_addr = request->dma + request->actual;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = c->channel_program(channel,
|
|
|
|
musb_ep->packet_sz,
|
|
|
|
channel->desired_mode,
|
|
|
|
dma_addr,
|
|
|
|
fifo_count);
|
|
|
|
if (ret)
|
|
|
|
return;
|
|
|
|
}
|
2015-08-06 15:47:16 +00:00
|
|
|
|
2010-11-15 10:24:01 +00:00
|
|
|
/*
|
|
|
|
* Unmap the dma buffer back to cpu if dma channel
|
|
|
|
* programming fails. This buffer is mapped if the
|
|
|
|
* channel allocation is successful
|
|
|
|
*/
|
2015-08-06 15:47:16 +00:00
|
|
|
unmap_dma_buffer(req, musb);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear DMAENAB and AUTOCLEAR for the
|
|
|
|
* PIO mode transfer
|
|
|
|
*/
|
|
|
|
csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2015-08-06 15:47:16 +00:00
|
|
|
buffer_aint_mapped:
|
2022-09-06 02:21:19 +00:00
|
|
|
fifo_count = min_t(unsigned int,
|
|
|
|
request->length - request->actual,
|
|
|
|
(unsigned int)fifo_count);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
|
|
|
|
(request->buf + request->actual));
|
|
|
|
request->actual += fifo_count;
|
|
|
|
|
|
|
|
/* REVISIT if we left anything in the fifo, flush
|
|
|
|
* it and report -EOVERFLOW
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* ack the read! */
|
|
|
|
csr |= MUSB_RXCSR_P_WZC_BITS;
|
|
|
|
csr &= ~MUSB_RXCSR_RXPKTRDY;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* reach the end or short packet detected */
|
2012-07-16 19:25:04 +00:00
|
|
|
if (request->actual == request->length ||
|
|
|
|
fifo_count < musb_ep->packet_sz)
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_g_giveback(musb_ep, request, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Data ready for a request; called from IRQ
|
|
|
|
*/
|
|
|
|
void musb_g_rx(struct musb *musb, u8 epnum)
|
|
|
|
{
|
|
|
|
u16 csr;
|
2011-02-16 10:40:05 +00:00
|
|
|
struct musb_request *req;
|
2008-07-24 09:27:36 +00:00
|
|
|
struct usb_request *request;
|
|
|
|
void __iomem *mbase = musb->mregs;
|
2010-09-20 07:32:01 +00:00
|
|
|
struct musb_ep *musb_ep;
|
2008-07-24 09:27:36 +00:00
|
|
|
void __iomem *epio = musb->endpoints[epnum].regs;
|
|
|
|
struct dma_channel *dma;
|
2010-09-20 07:32:01 +00:00
|
|
|
struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
|
|
|
|
|
|
|
|
if (hw_ep->is_shared_fifo)
|
|
|
|
musb_ep = &hw_ep->ep_in;
|
|
|
|
else
|
|
|
|
musb_ep = &hw_ep->ep_out;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
musb_ep_select(mbase, epnum);
|
|
|
|
|
2011-02-16 10:40:05 +00:00
|
|
|
req = next_request(musb_ep);
|
|
|
|
if (!req)
|
2009-12-22 10:48:19 +00:00
|
|
|
return;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2016-06-30 17:12:27 +00:00
|
|
|
trace_musb_req_rx(req);
|
2011-02-16 10:40:05 +00:00
|
|
|
request = &req->request;
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
csr = musb_readw(epio, MUSB_RXCSR);
|
|
|
|
dma = is_dma_capable() ? musb_ep->dma : NULL;
|
|
|
|
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
|
2008-07-24 09:27:36 +00:00
|
|
|
csr, dma ? " (dma)" : "", request);
|
|
|
|
|
|
|
|
if (csr & MUSB_RXCSR_P_SENTSTALL) {
|
|
|
|
csr |= MUSB_RXCSR_P_WZC_BITS;
|
|
|
|
csr &= ~MUSB_RXCSR_P_SENTSTALL;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
2009-11-18 19:51:18 +00:00
|
|
|
return;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (csr & MUSB_RXCSR_P_OVERRUN) {
|
|
|
|
/* csr |= MUSB_RXCSR_P_WZC_BITS; */
|
|
|
|
csr &= ~MUSB_RXCSR_P_OVERRUN;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
|
2010-09-24 10:44:12 +00:00
|
|
|
if (request->status == -EINPROGRESS)
|
2008-07-24 09:27:36 +00:00
|
|
|
request->status = -EOVERFLOW;
|
|
|
|
}
|
|
|
|
if (csr & MUSB_RXCSR_INCOMPRX) {
|
|
|
|
/* REVISIT not necessarily an error */
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
|
|
|
|
/* "should not happen"; likely RXPKTRDY pending for DMA */
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s busy, csr %04x",
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep->end_point.name, csr);
|
2009-11-18 19:51:18 +00:00
|
|
|
return;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
|
|
|
|
csr &= ~(MUSB_RXCSR_AUTOCLEAR
|
|
|
|
| MUSB_RXCSR_DMAENAB
|
|
|
|
| MUSB_RXCSR_DMAMODE);
|
|
|
|
musb_writew(epio, MUSB_RXCSR,
|
|
|
|
MUSB_RXCSR_P_WZC_BITS | csr);
|
|
|
|
|
|
|
|
request->actual += musb_ep->dma->actual_len;
|
|
|
|
|
2011-03-22 14:55:56 +00:00
|
|
|
#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
|
|
|
|
defined(CONFIG_USB_UX500_DMA)
|
2008-07-24 09:27:36 +00:00
|
|
|
/* Autoclear doesn't clear RxPktRdy for short packets */
|
2010-09-25 10:50:43 +00:00
|
|
|
if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
|
2008-07-24 09:27:36 +00:00
|
|
|
|| (dma->actual_len
|
|
|
|
& (musb_ep->packet_sz - 1))) {
|
|
|
|
/* ack the read! */
|
|
|
|
csr &= ~MUSB_RXCSR_RXPKTRDY;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* incomplete, and not short? wait for next IN packet */
|
|
|
|
if ((request->actual < request->length)
|
|
|
|
&& (musb_ep->dma->actual_len
|
2010-09-25 10:50:43 +00:00
|
|
|
== musb_ep->packet_sz)) {
|
|
|
|
/* In double buffer case, continue to unload fifo if
|
|
|
|
* there is Rx packet in FIFO.
|
|
|
|
**/
|
|
|
|
csr = musb_readw(epio, MUSB_RXCSR);
|
|
|
|
if ((csr & MUSB_RXCSR_RXPKTRDY) &&
|
|
|
|
hw_ep->rx_double_buffered)
|
|
|
|
goto exit;
|
2009-11-18 19:51:18 +00:00
|
|
|
return;
|
2010-09-25 10:50:43 +00:00
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
#endif
|
|
|
|
musb_g_giveback(musb_ep, request, 0);
|
2012-02-17 09:24:52 +00:00
|
|
|
/*
|
|
|
|
* In the giveback function the MUSB lock is
|
|
|
|
* released and acquired after sometime. During
|
|
|
|
* this time period the INDEX register could get
|
|
|
|
* changed by the gadget_queue function especially
|
|
|
|
* on SMP systems. Reselect the INDEX to be sure
|
|
|
|
* we are reading/modifying the right registers
|
|
|
|
*/
|
|
|
|
musb_ep_select(mbase, epnum);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2011-02-16 10:40:05 +00:00
|
|
|
req = next_request(musb_ep);
|
|
|
|
if (!req)
|
2009-11-18 19:51:18 +00:00
|
|
|
return;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
2011-03-22 14:55:56 +00:00
|
|
|
#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
|
|
|
|
defined(CONFIG_USB_UX500_DMA)
|
2010-09-25 10:50:43 +00:00
|
|
|
exit:
|
2010-11-22 08:52:41 +00:00
|
|
|
#endif
|
2010-09-24 10:44:12 +00:00
|
|
|
/* Analyze request */
|
2011-02-16 10:40:05 +00:00
|
|
|
rxstate(musb, req);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------ */
|
|
|
|
|
|
|
|
static int musb_gadget_enable(struct usb_ep *ep,
|
|
|
|
const struct usb_endpoint_descriptor *desc)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
struct musb_ep *musb_ep;
|
|
|
|
struct musb_hw_ep *hw_ep;
|
|
|
|
void __iomem *regs;
|
|
|
|
struct musb *musb;
|
|
|
|
void __iomem *mbase;
|
|
|
|
u8 epnum;
|
|
|
|
u16 csr;
|
|
|
|
unsigned tmp;
|
|
|
|
int status = -EINVAL;
|
|
|
|
|
|
|
|
if (!ep || !desc)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
musb_ep = to_musb_ep(ep);
|
|
|
|
hw_ep = musb_ep->hw_ep;
|
|
|
|
regs = hw_ep->regs;
|
|
|
|
musb = musb_ep->musb;
|
|
|
|
mbase = musb->mregs;
|
|
|
|
epnum = musb_ep->current_epnum;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
|
|
|
|
if (musb_ep->desc) {
|
|
|
|
status = -EBUSY;
|
|
|
|
goto fail;
|
|
|
|
}
|
2009-01-25 01:57:24 +00:00
|
|
|
musb_ep->type = usb_endpoint_type(desc);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* check direction and (later) maxpacket size against endpoint */
|
2009-01-25 01:57:24 +00:00
|
|
|
if (usb_endpoint_num(desc) != epnum)
|
2008-07-24 09:27:36 +00:00
|
|
|
goto fail;
|
|
|
|
|
|
|
|
/* REVISIT this rules out high bandwidth periodic transfers */
|
2016-09-28 10:40:40 +00:00
|
|
|
tmp = usb_endpoint_maxp_mult(desc) - 1;
|
|
|
|
if (tmp) {
|
2010-09-24 10:44:04 +00:00
|
|
|
int ok;
|
|
|
|
|
|
|
|
if (usb_endpoint_dir_in(desc))
|
|
|
|
ok = musb->hb_iso_tx;
|
|
|
|
else
|
|
|
|
ok = musb->hb_iso_rx;
|
|
|
|
|
|
|
|
if (!ok) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "no support for high bandwidth ISO");
|
2010-09-24 10:44:04 +00:00
|
|
|
goto fail;
|
|
|
|
}
|
2016-09-28 10:40:40 +00:00
|
|
|
musb_ep->hb_mult = tmp;
|
2010-09-24 10:44:04 +00:00
|
|
|
} else {
|
|
|
|
musb_ep->hb_mult = 0;
|
|
|
|
}
|
|
|
|
|
2016-09-28 10:40:40 +00:00
|
|
|
musb_ep->packet_sz = usb_endpoint_maxp(desc);
|
2010-09-24 10:44:04 +00:00
|
|
|
tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* enable the interrupts for the endpoint, set the endpoint
|
|
|
|
* packet size (or fail), set the mode, clear the fifo
|
|
|
|
*/
|
|
|
|
musb_ep_select(mbase, epnum);
|
2009-01-25 01:57:24 +00:00
|
|
|
if (usb_endpoint_dir_in(desc)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
if (hw_ep->is_shared_fifo)
|
|
|
|
musb_ep->is_in = 1;
|
|
|
|
if (!musb_ep->is_in)
|
|
|
|
goto fail;
|
2010-09-24 10:44:04 +00:00
|
|
|
|
|
|
|
if (tmp > hw_ep->max_packet_sz_tx) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "packet size beyond hardware FIFO size");
|
2008-07-24 09:27:36 +00:00
|
|
|
goto fail;
|
2010-09-24 10:44:04 +00:00
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2012-10-30 18:52:26 +00:00
|
|
|
musb->intrtxe |= (1 << epnum);
|
|
|
|
musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* REVISIT if can_bulk_split(), use by updating "tmp";
|
|
|
|
* likewise high bandwidth periodic tx
|
|
|
|
*/
|
2010-01-29 01:44:18 +00:00
|
|
|
/* Set TXMAXP with the FIFO size of the endpoint
|
2010-10-20 00:08:25 +00:00
|
|
|
* to disable double buffering mode.
|
2010-01-29 01:44:18 +00:00
|
|
|
*/
|
2018-03-09 16:37:54 +00:00
|
|
|
if (can_bulk_split(musb, musb_ep->type))
|
|
|
|
musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
|
|
|
|
musb_ep->packet_sz) - 1;
|
|
|
|
musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
|
|
|
|
| (musb_ep->hb_mult << 11));
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
|
|
|
|
if (musb_readw(regs, MUSB_TXCSR)
|
|
|
|
& MUSB_TXCSR_FIFONOTEMPTY)
|
|
|
|
csr |= MUSB_TXCSR_FLUSHFIFO;
|
|
|
|
if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
|
|
|
|
csr |= MUSB_TXCSR_P_ISO;
|
|
|
|
|
|
|
|
/* set twice in case of double buffering */
|
|
|
|
musb_writew(regs, MUSB_TXCSR, csr);
|
|
|
|
/* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
|
|
|
|
musb_writew(regs, MUSB_TXCSR, csr);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
|
|
|
|
if (hw_ep->is_shared_fifo)
|
|
|
|
musb_ep->is_in = 0;
|
|
|
|
if (musb_ep->is_in)
|
|
|
|
goto fail;
|
2010-09-24 10:44:04 +00:00
|
|
|
|
|
|
|
if (tmp > hw_ep->max_packet_sz_rx) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "packet size beyond hardware FIFO size");
|
2008-07-24 09:27:36 +00:00
|
|
|
goto fail;
|
2010-09-24 10:44:04 +00:00
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2012-10-30 18:52:25 +00:00
|
|
|
musb->intrrxe |= (1 << epnum);
|
|
|
|
musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* REVISIT if can_bulk_combine() use by updating "tmp"
|
|
|
|
* likewise high bandwidth periodic rx
|
|
|
|
*/
|
2010-01-29 01:44:18 +00:00
|
|
|
/* Set RXMAXP with the FIFO size of the endpoint
|
|
|
|
* to disable double buffering mode.
|
|
|
|
*/
|
2018-03-09 16:37:54 +00:00
|
|
|
musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
|
|
|
|
| (musb_ep->hb_mult << 11));
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* force shared fifo to OUT-only mode */
|
|
|
|
if (hw_ep->is_shared_fifo) {
|
|
|
|
csr = musb_readw(regs, MUSB_TXCSR);
|
|
|
|
csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
|
|
|
|
musb_writew(regs, MUSB_TXCSR, csr);
|
|
|
|
}
|
|
|
|
|
|
|
|
csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
|
|
|
|
if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
|
|
|
|
csr |= MUSB_RXCSR_P_ISO;
|
|
|
|
else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
|
|
|
|
csr |= MUSB_RXCSR_DISNYET;
|
|
|
|
|
|
|
|
/* set twice in case of double buffering */
|
|
|
|
musb_writew(regs, MUSB_RXCSR, csr);
|
|
|
|
musb_writew(regs, MUSB_RXCSR, csr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NOTE: all the I/O code _should_ work fine without DMA, in case
|
|
|
|
* for some reason you run out of channels here.
|
|
|
|
*/
|
|
|
|
if (is_dma_capable() && musb->dma_controller) {
|
|
|
|
struct dma_controller *c = musb->dma_controller;
|
|
|
|
|
|
|
|
musb_ep->dma = c->channel_alloc(c, hw_ep,
|
|
|
|
(desc->bEndpointAddress & USB_DIR_IN));
|
|
|
|
} else
|
|
|
|
musb_ep->dma = NULL;
|
|
|
|
|
|
|
|
musb_ep->desc = desc;
|
|
|
|
musb_ep->busy = 0;
|
2009-11-18 19:51:51 +00:00
|
|
|
musb_ep->wedged = 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
status = 0;
|
|
|
|
|
|
|
|
pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
|
|
|
|
musb_driver_name, musb_ep->end_point.name,
|
2017-08-24 16:38:32 +00:00
|
|
|
musb_ep_xfertype_string(musb_ep->type),
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep->is_in ? "IN" : "OUT",
|
|
|
|
musb_ep->dma ? "dma, " : "",
|
|
|
|
musb_ep->packet_sz);
|
|
|
|
|
2016-11-16 19:21:24 +00:00
|
|
|
schedule_delayed_work(&musb->irq_work, 0);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
fail:
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable an endpoint flushing all requests queued.
|
|
|
|
*/
|
|
|
|
static int musb_gadget_disable(struct usb_ep *ep)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
struct musb *musb;
|
|
|
|
u8 epnum;
|
|
|
|
struct musb_ep *musb_ep;
|
|
|
|
void __iomem *epio;
|
|
|
|
|
|
|
|
musb_ep = to_musb_ep(ep);
|
|
|
|
musb = musb_ep->musb;
|
|
|
|
epnum = musb_ep->current_epnum;
|
|
|
|
epio = musb->endpoints[epnum].regs;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
musb_ep_select(musb->mregs, epnum);
|
|
|
|
|
|
|
|
/* zero the endpoint sizes */
|
|
|
|
if (musb_ep->is_in) {
|
2012-10-30 18:52:26 +00:00
|
|
|
musb->intrtxe &= ~(1 << epnum);
|
|
|
|
musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_writew(epio, MUSB_TXMAXP, 0);
|
|
|
|
} else {
|
2012-10-30 18:52:25 +00:00
|
|
|
musb->intrrxe &= ~(1 << epnum);
|
|
|
|
musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_writew(epio, MUSB_RXMAXP, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* abort all pending DMA and requests */
|
|
|
|
nuke(musb_ep, -ESHUTDOWN);
|
|
|
|
|
2016-04-25 20:53:29 +00:00
|
|
|
musb_ep->desc = NULL;
|
|
|
|
musb_ep->end_point.desc = NULL;
|
|
|
|
|
2016-11-16 19:21:24 +00:00
|
|
|
schedule_delayed_work(&musb->irq_work, 0);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&(musb->lock), flags);
|
|
|
|
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s", musb_ep->end_point.name);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2019-10-02 14:32:45 +00:00
|
|
|
return 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate a request for an endpoint.
|
|
|
|
* Reused by ep0 code.
|
|
|
|
*/
|
|
|
|
struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
|
|
|
|
{
|
|
|
|
struct musb_ep *musb_ep = to_musb_ep(ep);
|
2023-08-04 09:32:52 +00:00
|
|
|
struct musb_request *request;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
request = kzalloc(sizeof *request, gfp_flags);
|
2016-06-30 17:12:22 +00:00
|
|
|
if (!request)
|
2010-12-01 09:03:54 +00:00
|
|
|
return NULL;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2010-12-01 09:03:54 +00:00
|
|
|
request->request.dma = DMA_ADDR_INVALID;
|
|
|
|
request->epnum = musb_ep->current_epnum;
|
|
|
|
request->ep = musb_ep;
|
|
|
|
|
2016-06-30 17:12:27 +00:00
|
|
|
trace_musb_req_alloc(request);
|
2008-07-24 09:27:36 +00:00
|
|
|
return &request->request;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free a request
|
|
|
|
* Reused by ep0 code.
|
|
|
|
*/
|
|
|
|
void musb_free_request(struct usb_ep *ep, struct usb_request *req)
|
|
|
|
{
|
2016-06-30 17:12:27 +00:00
|
|
|
struct musb_request *request = to_musb_request(req);
|
|
|
|
|
|
|
|
trace_musb_req_free(request);
|
|
|
|
kfree(request);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static LIST_HEAD(buffers);
|
|
|
|
|
|
|
|
struct free_record {
|
|
|
|
struct list_head list;
|
|
|
|
struct device *dev;
|
|
|
|
unsigned bytes;
|
|
|
|
dma_addr_t dma;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Context: controller locked, IRQs blocked.
|
|
|
|
*/
|
2010-09-11 18:23:12 +00:00
|
|
|
void musb_ep_restart(struct musb *musb, struct musb_request *req)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
2016-06-30 17:12:27 +00:00
|
|
|
trace_musb_req_start(req);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep_select(musb->mregs, req->epnum);
|
|
|
|
if (req->tx)
|
|
|
|
txstate(musb, req);
|
|
|
|
else
|
|
|
|
rxstate(musb, req);
|
|
|
|
}
|
|
|
|
|
2016-11-16 19:21:23 +00:00
|
|
|
static int musb_ep_restart_resume_work(struct musb *musb, void *data)
|
|
|
|
{
|
|
|
|
struct musb_request *req = data;
|
|
|
|
|
|
|
|
musb_ep_restart(musb, req);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
|
|
|
|
gfp_t gfp_flags)
|
|
|
|
{
|
|
|
|
struct musb_ep *musb_ep;
|
|
|
|
struct musb_request *request;
|
|
|
|
struct musb *musb;
|
2016-11-16 19:21:23 +00:00
|
|
|
int status;
|
2008-07-24 09:27:36 +00:00
|
|
|
unsigned long lockflags;
|
|
|
|
|
|
|
|
if (!ep || !req)
|
|
|
|
return -EINVAL;
|
|
|
|
if (!req->buf)
|
|
|
|
return -ENODATA;
|
|
|
|
|
|
|
|
musb_ep = to_musb_ep(ep);
|
|
|
|
musb = musb_ep->musb;
|
|
|
|
|
|
|
|
request = to_musb_request(req);
|
|
|
|
request->musb = musb;
|
|
|
|
|
|
|
|
if (request->ep != musb_ep)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2016-11-16 19:21:23 +00:00
|
|
|
status = pm_runtime_get(musb->controller);
|
|
|
|
if ((status != -EINPROGRESS) && status < 0) {
|
|
|
|
dev_err(musb->controller,
|
|
|
|
"pm runtime get failed in %s\n",
|
|
|
|
__func__);
|
|
|
|
pm_runtime_put_noidle(musb->controller);
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
status = 0;
|
|
|
|
|
2016-06-30 17:12:27 +00:00
|
|
|
trace_musb_req_enq(request);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* request is mine now... */
|
|
|
|
request->request.actual = 0;
|
|
|
|
request->request.status = -EINPROGRESS;
|
|
|
|
request->epnum = musb_ep->current_epnum;
|
|
|
|
request->tx = musb_ep->is_in;
|
|
|
|
|
2011-01-04 11:47:02 +00:00
|
|
|
map_dma_buffer(request, musb, musb_ep);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, lockflags);
|
|
|
|
|
|
|
|
/* don't queue if the ep is down */
|
|
|
|
if (!musb_ep->desc) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "req %p queued to %s while ep %s",
|
2008-07-24 09:27:36 +00:00
|
|
|
req, ep->name, "disabled");
|
|
|
|
status = -ESHUTDOWN;
|
2013-06-19 15:38:15 +00:00
|
|
|
unmap_dma_buffer(request, musb);
|
|
|
|
goto unlock;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* add request to the list */
|
2011-02-16 10:40:05 +00:00
|
|
|
list_add_tail(&request->list, &musb_ep->req_list);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* it this is the head of the queue, start i/o ... */
|
2016-11-16 19:21:23 +00:00
|
|
|
if (!musb_ep->busy && &request->list == musb_ep->req_list.next) {
|
|
|
|
status = musb_queue_resume_work(musb,
|
|
|
|
musb_ep_restart_resume_work,
|
|
|
|
request);
|
2021-10-21 09:36:44 +00:00
|
|
|
if (status < 0) {
|
2016-11-16 19:21:23 +00:00
|
|
|
dev_err(musb->controller, "%s resume work: %i\n",
|
|
|
|
__func__, status);
|
2021-10-21 09:36:44 +00:00
|
|
|
list_del(&request->list);
|
|
|
|
}
|
2016-11-16 19:21:23 +00:00
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2013-06-19 15:38:15 +00:00
|
|
|
unlock:
|
2008-07-24 09:27:36 +00:00
|
|
|
spin_unlock_irqrestore(&musb->lock, lockflags);
|
2016-10-19 17:03:40 +00:00
|
|
|
pm_runtime_mark_last_busy(musb->controller);
|
|
|
|
pm_runtime_put_autosuspend(musb->controller);
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
|
|
|
|
{
|
|
|
|
struct musb_ep *musb_ep = to_musb_ep(ep);
|
2011-02-28 08:44:50 +00:00
|
|
|
struct musb_request *req = to_musb_request(request);
|
|
|
|
struct musb_request *r;
|
2008-07-24 09:27:36 +00:00
|
|
|
unsigned long flags;
|
|
|
|
int status = 0;
|
|
|
|
struct musb *musb = musb_ep->musb;
|
|
|
|
|
2016-06-30 17:12:27 +00:00
|
|
|
if (!ep || !request || req->ep != musb_ep)
|
2008-07-24 09:27:36 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
2016-06-30 17:12:27 +00:00
|
|
|
trace_musb_req_deq(req);
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
|
|
|
|
list_for_each_entry(r, &musb_ep->req_list, list) {
|
2011-02-28 08:44:50 +00:00
|
|
|
if (r == req)
|
2008-07-24 09:27:36 +00:00
|
|
|
break;
|
|
|
|
}
|
2011-02-28 08:44:50 +00:00
|
|
|
if (r != req) {
|
2016-06-30 17:12:22 +00:00
|
|
|
dev_err(musb->controller, "request %p not queued to %s\n",
|
|
|
|
request, ep->name);
|
2008-07-24 09:27:36 +00:00
|
|
|
status = -EINVAL;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* if the hardware doesn't have the request, easy ... */
|
2011-03-22 09:38:49 +00:00
|
|
|
if (musb_ep->req_list.next != &req->list || musb_ep->busy)
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_g_giveback(musb_ep, request, -ECONNRESET);
|
|
|
|
|
|
|
|
/* ... else abort the dma transfer ... */
|
|
|
|
else if (is_dma_capable() && musb_ep->dma) {
|
|
|
|
struct dma_controller *c = musb->dma_controller;
|
|
|
|
|
|
|
|
musb_ep_select(musb->mregs, musb_ep->current_epnum);
|
|
|
|
if (c->channel_abort)
|
|
|
|
status = c->channel_abort(musb_ep->dma);
|
|
|
|
else
|
|
|
|
status = -EBUSY;
|
|
|
|
if (status == 0)
|
|
|
|
musb_g_giveback(musb_ep, request, -ECONNRESET);
|
|
|
|
} else {
|
|
|
|
/* NOTE: by sticking to easily tested hardware/driver states,
|
|
|
|
* we leave counting of in-flight packets imprecise.
|
|
|
|
*/
|
|
|
|
musb_g_giveback(musb_ep, request, -ECONNRESET);
|
|
|
|
}
|
|
|
|
|
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2019-10-24 15:28:33 +00:00
|
|
|
* Set or clear the halt bit of an endpoint. A halted endpoint won't tx/rx any
|
2008-07-24 09:27:36 +00:00
|
|
|
* data but will queue requests.
|
|
|
|
*
|
|
|
|
* exported to ep0 code
|
|
|
|
*/
|
2009-12-04 13:47:46 +00:00
|
|
|
static int musb_gadget_set_halt(struct usb_ep *ep, int value)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
|
|
|
struct musb_ep *musb_ep = to_musb_ep(ep);
|
|
|
|
u8 epnum = musb_ep->current_epnum;
|
|
|
|
struct musb *musb = musb_ep->musb;
|
|
|
|
void __iomem *epio = musb->endpoints[epnum].regs;
|
|
|
|
void __iomem *mbase;
|
|
|
|
unsigned long flags;
|
|
|
|
u16 csr;
|
2009-11-18 19:51:18 +00:00
|
|
|
struct musb_request *request;
|
2008-07-24 09:27:36 +00:00
|
|
|
int status = 0;
|
|
|
|
|
|
|
|
if (!ep)
|
|
|
|
return -EINVAL;
|
|
|
|
mbase = musb->mregs;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
|
|
|
|
if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
|
|
|
|
status = -EINVAL;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
musb_ep_select(mbase, epnum);
|
|
|
|
|
2011-02-16 10:40:05 +00:00
|
|
|
request = next_request(musb_ep);
|
2009-11-18 19:51:18 +00:00
|
|
|
if (value) {
|
|
|
|
if (request) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "request in progress, cannot halt %s",
|
2009-11-18 19:51:18 +00:00
|
|
|
ep->name);
|
|
|
|
status = -EAGAIN;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
/* Cannot portably stall with non-empty FIFO */
|
|
|
|
if (musb_ep->is_in) {
|
|
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
|
|
if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "FIFO busy, cannot halt %s",
|
|
|
|
ep->name);
|
2009-11-18 19:51:18 +00:00
|
|
|
status = -EAGAIN;
|
|
|
|
goto done;
|
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
2009-11-18 19:51:51 +00:00
|
|
|
} else
|
|
|
|
musb_ep->wedged = 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* set/clear the stall and toggle bits */
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
|
2008-07-24 09:27:36 +00:00
|
|
|
if (musb_ep->is_in) {
|
|
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
|
|
csr |= MUSB_TXCSR_P_WZC_BITS
|
|
|
|
| MUSB_TXCSR_CLRDATATOG;
|
|
|
|
if (value)
|
|
|
|
csr |= MUSB_TXCSR_P_SENDSTALL;
|
|
|
|
else
|
|
|
|
csr &= ~(MUSB_TXCSR_P_SENDSTALL
|
|
|
|
| MUSB_TXCSR_P_SENTSTALL);
|
|
|
|
csr &= ~MUSB_TXCSR_TXPKTRDY;
|
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
} else {
|
|
|
|
csr = musb_readw(epio, MUSB_RXCSR);
|
|
|
|
csr |= MUSB_RXCSR_P_WZC_BITS
|
|
|
|
| MUSB_RXCSR_FLUSHFIFO
|
|
|
|
| MUSB_RXCSR_CLRDATATOG;
|
|
|
|
if (value)
|
|
|
|
csr |= MUSB_RXCSR_P_SENDSTALL;
|
|
|
|
else
|
|
|
|
csr &= ~(MUSB_RXCSR_P_SENDSTALL
|
|
|
|
| MUSB_RXCSR_P_SENTSTALL);
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* maybe start the first request in the queue */
|
|
|
|
if (!musb_ep->busy && !value && request) {
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "restarting the request");
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_ep_restart(musb, request);
|
|
|
|
}
|
|
|
|
|
2009-11-18 19:51:18 +00:00
|
|
|
done:
|
2008-07-24 09:27:36 +00:00
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2009-11-18 19:51:51 +00:00
|
|
|
/*
|
|
|
|
* Sets the halt feature with the clear requests ignored
|
|
|
|
*/
|
2009-12-04 13:47:46 +00:00
|
|
|
static int musb_gadget_set_wedge(struct usb_ep *ep)
|
2009-11-18 19:51:51 +00:00
|
|
|
{
|
|
|
|
struct musb_ep *musb_ep = to_musb_ep(ep);
|
|
|
|
|
|
|
|
if (!ep)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
musb_ep->wedged = 1;
|
|
|
|
|
|
|
|
return usb_ep_set_halt(ep);
|
|
|
|
}
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
static int musb_gadget_fifo_status(struct usb_ep *ep)
|
|
|
|
{
|
|
|
|
struct musb_ep *musb_ep = to_musb_ep(ep);
|
|
|
|
void __iomem *epio = musb_ep->hw_ep->regs;
|
|
|
|
int retval = -EINVAL;
|
|
|
|
|
|
|
|
if (musb_ep->desc && !musb_ep->is_in) {
|
|
|
|
struct musb *musb = musb_ep->musb;
|
|
|
|
int epnum = musb_ep->current_epnum;
|
|
|
|
void __iomem *mbase = musb->mregs;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
|
|
|
|
musb_ep_select(mbase, epnum);
|
|
|
|
/* FIXME return zero unless RXPKTRDY is set */
|
|
|
|
retval = musb_readw(epio, MUSB_RXCOUNT);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
}
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void musb_gadget_fifo_flush(struct usb_ep *ep)
|
|
|
|
{
|
|
|
|
struct musb_ep *musb_ep = to_musb_ep(ep);
|
|
|
|
struct musb *musb = musb_ep->musb;
|
|
|
|
u8 epnum = musb_ep->current_epnum;
|
|
|
|
void __iomem *epio = musb->endpoints[epnum].regs;
|
|
|
|
void __iomem *mbase;
|
|
|
|
unsigned long flags;
|
2012-10-30 18:52:26 +00:00
|
|
|
u16 csr;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
mbase = musb->mregs;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
musb_ep_select(mbase, (u8) epnum);
|
|
|
|
|
|
|
|
/* disable interrupts */
|
2012-10-30 18:52:26 +00:00
|
|
|
musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
if (musb_ep->is_in) {
|
|
|
|
csr = musb_readw(epio, MUSB_TXCSR);
|
|
|
|
if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
|
|
|
|
csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
|
2011-06-08 14:12:02 +00:00
|
|
|
/*
|
|
|
|
* Setting both TXPKTRDY and FLUSHFIFO makes controller
|
|
|
|
* to interrupt current FIFO loading, but not flushing
|
|
|
|
* the already loaded ones.
|
|
|
|
*/
|
|
|
|
csr &= ~MUSB_TXCSR_TXPKTRDY;
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
/* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
|
|
|
|
musb_writew(epio, MUSB_TXCSR, csr);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
csr = musb_readw(epio, MUSB_RXCSR);
|
|
|
|
csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
musb_writew(epio, MUSB_RXCSR, csr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* re-enable interrupt */
|
2012-10-30 18:52:26 +00:00
|
|
|
musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
|
2008-07-24 09:27:36 +00:00
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct usb_ep_ops musb_ep_ops = {
|
|
|
|
.enable = musb_gadget_enable,
|
|
|
|
.disable = musb_gadget_disable,
|
|
|
|
.alloc_request = musb_alloc_request,
|
|
|
|
.free_request = musb_free_request,
|
|
|
|
.queue = musb_gadget_queue,
|
|
|
|
.dequeue = musb_gadget_dequeue,
|
|
|
|
.set_halt = musb_gadget_set_halt,
|
2009-11-18 19:51:51 +00:00
|
|
|
.set_wedge = musb_gadget_set_wedge,
|
2008-07-24 09:27:36 +00:00
|
|
|
.fifo_status = musb_gadget_fifo_status,
|
|
|
|
.fifo_flush = musb_gadget_fifo_flush
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static int musb_gadget_get_frame(struct usb_gadget *gadget)
|
|
|
|
{
|
|
|
|
struct musb *musb = gadget_to_musb(gadget);
|
|
|
|
|
|
|
|
return (int)musb_readw(musb->mregs, MUSB_FRAME);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int musb_gadget_wakeup(struct usb_gadget *gadget)
|
|
|
|
{
|
|
|
|
struct musb *musb = gadget_to_musb(gadget);
|
|
|
|
void __iomem *mregs = musb->mregs;
|
|
|
|
unsigned long flags;
|
|
|
|
int status = -EINVAL;
|
|
|
|
u8 power, devctl;
|
|
|
|
int retries;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
|
2022-10-26 18:26:51 +00:00
|
|
|
switch (musb_get_state(musb)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
case OTG_STATE_B_PERIPHERAL:
|
|
|
|
/* NOTE: OTG state machine doesn't include B_SUSPENDED;
|
|
|
|
* that's part of the standard usb 1.1 state machine, and
|
|
|
|
* doesn't affect OTG transitions.
|
|
|
|
*/
|
|
|
|
if (musb->may_wakeup && musb->is_suspended)
|
|
|
|
break;
|
|
|
|
goto done;
|
|
|
|
case OTG_STATE_B_IDLE:
|
|
|
|
/* Start SRP ... OTG not required. */
|
|
|
|
devctl = musb_readb(mregs, MUSB_DEVCTL);
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
|
2008-07-24 09:27:36 +00:00
|
|
|
devctl |= MUSB_DEVCTL_SESSION;
|
|
|
|
musb_writeb(mregs, MUSB_DEVCTL, devctl);
|
|
|
|
devctl = musb_readb(mregs, MUSB_DEVCTL);
|
|
|
|
retries = 100;
|
|
|
|
while (!(devctl & MUSB_DEVCTL_SESSION)) {
|
|
|
|
devctl = musb_readb(mregs, MUSB_DEVCTL);
|
|
|
|
if (retries-- < 1)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
retries = 10000;
|
|
|
|
while (devctl & MUSB_DEVCTL_SESSION) {
|
|
|
|
devctl = musb_readb(mregs, MUSB_DEVCTL);
|
|
|
|
if (retries-- < 1)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2022-10-26 18:26:53 +00:00
|
|
|
if (musb->xceiv) {
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
otg_start_srp(musb->xceiv->otg);
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
}
|
2011-03-22 11:24:22 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
/* Block idling for at least 1s */
|
|
|
|
musb_platform_try_idle(musb,
|
|
|
|
jiffies + msecs_to_jiffies(1 * HZ));
|
|
|
|
|
|
|
|
status = 0;
|
|
|
|
goto done;
|
|
|
|
default:
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "Unhandled wake: %s",
|
2022-10-26 18:26:52 +00:00
|
|
|
musb_otg_state_string(musb));
|
2008-07-24 09:27:36 +00:00
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
status = 0;
|
|
|
|
|
|
|
|
power = musb_readb(mregs, MUSB_POWER);
|
|
|
|
power |= MUSB_POWER_RESUME;
|
|
|
|
musb_writeb(mregs, MUSB_POWER, power);
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "issue wakeup");
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* FIXME do this next chunk in a timer callback, no udelay */
|
|
|
|
mdelay(2);
|
|
|
|
|
|
|
|
power = musb_readb(mregs, MUSB_POWER);
|
|
|
|
power &= ~MUSB_POWER_RESUME;
|
|
|
|
musb_writeb(mregs, MUSB_POWER, power);
|
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
|
|
|
|
{
|
2015-01-28 08:32:41 +00:00
|
|
|
gadget->is_selfpowered = !!is_selfpowered;
|
2008-07-24 09:27:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void musb_pullup(struct musb *musb, int is_on)
|
|
|
|
{
|
|
|
|
u8 power;
|
|
|
|
|
|
|
|
power = musb_readb(musb->mregs, MUSB_POWER);
|
|
|
|
if (is_on)
|
|
|
|
power |= MUSB_POWER_SOFTCONN;
|
|
|
|
else
|
|
|
|
power &= ~MUSB_POWER_SOFTCONN;
|
|
|
|
|
|
|
|
/* FIXME if on, HdrcStart; if off, HdrcStop */
|
|
|
|
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "gadget D+ pullup %s",
|
2011-06-23 12:26:16 +00:00
|
|
|
is_on ? "on" : "off");
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_writeb(musb->mregs, MUSB_POWER, power);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
|
|
|
|
{
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "<= %s =>\n", __func__);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME iff driver's softconnect flag is set (as it is during probe,
|
|
|
|
* though that can clear it), just musb_pullup().
|
|
|
|
*/
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
|
|
|
|
{
|
|
|
|
struct musb *musb = gadget_to_musb(gadget);
|
|
|
|
|
2012-02-13 11:24:18 +00:00
|
|
|
return usb_phy_set_power(musb->xceiv, mA);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
2016-05-31 15:05:14 +00:00
|
|
|
static void musb_gadget_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct musb *musb;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
musb = container_of(work, struct musb, gadget_work.work);
|
|
|
|
pm_runtime_get_sync(musb->controller);
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
musb_pullup(musb, musb->softconnect);
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
pm_runtime_mark_last_busy(musb->controller);
|
|
|
|
pm_runtime_put_autosuspend(musb->controller);
|
|
|
|
}
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
|
|
|
|
{
|
|
|
|
struct musb *musb = gadget_to_musb(gadget);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
is_on = !!is_on;
|
|
|
|
|
|
|
|
/* NOTE: this assumes we are sensing vbus; we'd rather
|
|
|
|
* not pullup unless the B-session is active.
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
if (is_on != musb->softconnect) {
|
|
|
|
musb->softconnect = is_on;
|
2016-05-31 15:05:14 +00:00
|
|
|
schedule_delayed_work(&musb->gadget_work, 0);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
2011-07-21 00:09:34 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-23 12:26:16 +00:00
|
|
|
static int musb_gadget_start(struct usb_gadget *g,
|
|
|
|
struct usb_gadget_driver *driver);
|
2014-10-17 17:05:12 +00:00
|
|
|
static int musb_gadget_stop(struct usb_gadget *g);
|
2011-06-28 13:33:47 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
static const struct usb_gadget_ops musb_gadget_operations = {
|
|
|
|
.get_frame = musb_gadget_get_frame,
|
|
|
|
.wakeup = musb_gadget_wakeup,
|
|
|
|
.set_selfpowered = musb_gadget_set_self_powered,
|
|
|
|
/* .vbus_session = musb_gadget_vbus_session, */
|
|
|
|
.vbus_draw = musb_gadget_vbus_draw,
|
|
|
|
.pullup = musb_gadget_pullup,
|
2011-06-23 12:26:16 +00:00
|
|
|
.udc_start = musb_gadget_start,
|
|
|
|
.udc_stop = musb_gadget_stop,
|
2008-07-24 09:27:36 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
/* Registration */
|
|
|
|
|
|
|
|
/* Only this registration code "knows" the rule (from USB standards)
|
|
|
|
* about there being only one external upstream port. It assumes
|
|
|
|
* all peripheral ports are external...
|
|
|
|
*/
|
|
|
|
|
2012-11-19 18:21:48 +00:00
|
|
|
static void
|
2008-07-24 09:27:36 +00:00
|
|
|
init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
|
|
|
|
{
|
|
|
|
struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
|
|
|
|
|
|
|
|
memset(ep, 0, sizeof *ep);
|
|
|
|
|
|
|
|
ep->current_epnum = epnum;
|
|
|
|
ep->musb = musb;
|
|
|
|
ep->hw_ep = hw_ep;
|
|
|
|
ep->is_in = is_in;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&ep->req_list);
|
|
|
|
|
|
|
|
sprintf(ep->name, "ep%d%s", epnum,
|
|
|
|
(!epnum || hw_ep->is_shared_fifo) ? "" : (
|
|
|
|
is_in ? "in" : "out"));
|
|
|
|
ep->end_point.name = ep->name;
|
|
|
|
INIT_LIST_HEAD(&ep->end_point.ep_list);
|
|
|
|
if (!epnum) {
|
2013-12-13 11:23:38 +00:00
|
|
|
usb_ep_set_maxpacket_limit(&ep->end_point, 64);
|
2015-07-31 14:00:46 +00:00
|
|
|
ep->end_point.caps.type_control = true;
|
2008-07-24 09:27:36 +00:00
|
|
|
ep->end_point.ops = &musb_g_ep0_ops;
|
|
|
|
musb->g.ep0 = &ep->end_point;
|
|
|
|
} else {
|
|
|
|
if (is_in)
|
2013-12-13 11:23:38 +00:00
|
|
|
usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
|
2008-07-24 09:27:36 +00:00
|
|
|
else
|
2013-12-13 11:23:38 +00:00
|
|
|
usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
|
2015-07-31 14:00:46 +00:00
|
|
|
ep->end_point.caps.type_iso = true;
|
|
|
|
ep->end_point.caps.type_bulk = true;
|
|
|
|
ep->end_point.caps.type_int = true;
|
2008-07-24 09:27:36 +00:00
|
|
|
ep->end_point.ops = &musb_ep_ops;
|
|
|
|
list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
|
|
|
|
}
|
2015-07-31 14:00:46 +00:00
|
|
|
|
|
|
|
if (!epnum || hw_ep->is_shared_fifo) {
|
|
|
|
ep->end_point.caps.dir_in = true;
|
|
|
|
ep->end_point.caps.dir_out = true;
|
|
|
|
} else if (is_in)
|
|
|
|
ep->end_point.caps.dir_in = true;
|
|
|
|
else
|
|
|
|
ep->end_point.caps.dir_out = true;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the endpoints exposed to peripheral drivers, with backlinks
|
|
|
|
* to the rest of the driver state.
|
|
|
|
*/
|
2012-11-19 18:21:48 +00:00
|
|
|
static inline void musb_g_init_endpoints(struct musb *musb)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
|
|
|
u8 epnum;
|
|
|
|
struct musb_hw_ep *hw_ep;
|
|
|
|
unsigned count = 0;
|
|
|
|
|
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 19:38:34 +00:00
|
|
|
/* initialize endpoint list just once */
|
2008-07-24 09:27:36 +00:00
|
|
|
INIT_LIST_HEAD(&(musb->g.ep_list));
|
|
|
|
|
|
|
|
for (epnum = 0, hw_ep = musb->endpoints;
|
|
|
|
epnum < musb->nr_endpoints;
|
|
|
|
epnum++, hw_ep++) {
|
|
|
|
if (hw_ep->is_shared_fifo /* || !epnum */) {
|
|
|
|
init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
|
|
|
|
count++;
|
|
|
|
} else {
|
|
|
|
if (hw_ep->max_packet_sz_tx) {
|
|
|
|
init_peripheral_ep(musb, &hw_ep->ep_in,
|
|
|
|
epnum, 1);
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
if (hw_ep->max_packet_sz_rx) {
|
|
|
|
init_peripheral_ep(musb, &hw_ep->ep_out,
|
|
|
|
epnum, 0);
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called once during driver setup to initialize and link into
|
|
|
|
* the driver model; memory is zeroed.
|
|
|
|
*/
|
2012-11-19 18:21:48 +00:00
|
|
|
int musb_gadget_setup(struct musb *musb)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
|
|
|
int status;
|
|
|
|
|
|
|
|
/* REVISIT minor race: if (erroneously) setting up two
|
|
|
|
* musb peripherals at the same time, only the bus lock
|
|
|
|
* is probably held.
|
|
|
|
*/
|
|
|
|
|
|
|
|
musb->g.ops = &musb_gadget_operations;
|
2011-11-19 17:27:37 +00:00
|
|
|
musb->g.max_speed = USB_SPEED_HIGH;
|
2008-07-24 09:27:36 +00:00
|
|
|
musb->g.speed = USB_SPEED_UNKNOWN;
|
|
|
|
|
2013-09-17 17:43:13 +00:00
|
|
|
MUSB_DEV_MODE(musb);
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_B_IDLE);
|
2013-09-17 17:43:13 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
/* this "gadget" abstracts/virtualizes the controller */
|
|
|
|
musb->g.name = musb_driver_name;
|
2018-05-21 13:42:19 +00:00
|
|
|
/* don't support otg protocols */
|
2013-11-19 22:18:20 +00:00
|
|
|
musb->g.is_otg = 0;
|
2016-05-31 15:05:14 +00:00
|
|
|
INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb_g_init_endpoints(musb);
|
|
|
|
|
|
|
|
musb->is_active = 0;
|
|
|
|
musb_platform_try_idle(musb, 0);
|
|
|
|
|
2011-06-28 13:33:47 +00:00
|
|
|
status = usb_add_gadget_udc(musb->controller, &musb->g);
|
|
|
|
if (status)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err:
|
2011-08-10 09:01:57 +00:00
|
|
|
musb->g.dev.parent = NULL;
|
2011-06-28 13:33:47 +00:00
|
|
|
device_unregister(&musb->g.dev);
|
2008-07-24 09:27:36 +00:00
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
void musb_gadget_cleanup(struct musb *musb)
|
|
|
|
{
|
2018-05-21 13:42:15 +00:00
|
|
|
if (musb->port_mode == MUSB_HOST)
|
2013-08-20 16:35:44 +00:00
|
|
|
return;
|
2016-05-31 15:05:14 +00:00
|
|
|
|
|
|
|
cancel_delayed_work_sync(&musb->gadget_work);
|
2011-06-28 13:33:47 +00:00
|
|
|
usb_del_gadget_udc(&musb->g);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Register the gadget driver. Used by gadget drivers when
|
|
|
|
* registering themselves with the controller.
|
|
|
|
*
|
|
|
|
* -EINVAL something went wrong (not driver)
|
|
|
|
* -EBUSY another gadget is already using the controller
|
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 19:38:34 +00:00
|
|
|
* -ENOMEM no memory to perform the operation
|
2008-07-24 09:27:36 +00:00
|
|
|
*
|
|
|
|
* @param driver the gadget driver
|
|
|
|
* @return <0 if error, 0 if everything is fine
|
|
|
|
*/
|
2011-06-23 12:26:16 +00:00
|
|
|
static int musb_gadget_start(struct usb_gadget *g,
|
|
|
|
struct usb_gadget_driver *driver)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
2011-06-23 12:26:16 +00:00
|
|
|
struct musb *musb = gadget_to_musb(g);
|
2011-01-17 08:34:38 +00:00
|
|
|
unsigned long flags;
|
2011-11-24 13:46:26 +00:00
|
|
|
int retval = 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2011-11-24 13:46:26 +00:00
|
|
|
if (driver->max_speed < USB_SPEED_HIGH) {
|
|
|
|
retval = -EINVAL;
|
|
|
|
goto err;
|
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
usb: musb: Idle path retention and offmode support for OMAP3
This patch supports the retention and offmode support in the idle path for
musb driver using runtime pm APIs.
This is restricted to support offmode and retention only when device not
connected.When device/cable connected with gadget driver loaded,configured
to no idle/standby which will not allow the core transition to retention
or off.
There is no context save/restore done by hardware for musb in OMAP3
and OMAP4,driver has to take care of saving and restoring the context
during offmode.
Musb has a requirement of configuring sysconfig register to force
idle/standby mode and set the ENFORCE bit in module STANDBY register
for retention and offmode support.
Runtime pm and hwmod frameworks will take care of configuring to force
idle/standby when pm_runtime_put_sync is called and back to no
idle/standby when pm_runeime_get_sync is called.
Compile, boot tested and also tested the retention in the idle path on
OMAP3630Zoom3. And tested the global suspend/resume with offmode enabled.
Usb basic functionality tested on OMAP4430SDP.
There is some problem with idle path offmode in mainline, I could not test
with offmode. But I have tested this patch with resetting the controller
in the idle path when wakeup from retention just to make sure that the
context is lost, and restore path is working fine.
Removed .suspend/.resume fnction pointers and functions because there
is no need of having these functions as all required work is done
at runtime in the driver.
There is no need to call the runtime pm api with glue driver device
as glue layer device is the parent of musb core device, when runtime apis
are called for the child, parent device runtime functionality
will be invoked.
Design overview:
pm_runtime_get_sync: When called with musb core device takes care of
enabling the clock, calling runtime callback function of omap2430 glue
layer, runtime call back of musb driver and configure the musb sysconfig
to no idle/standby
pm_runtime_put: Takes care of calling runtime callback function of omap2430
glue layer, runtime call back of musb driver, Configure the musb sysconfig
to force idle/standby and disable the clock.
During musb driver load: Call pm_runtime_get_sync.
End of musb driver load: Call pm_runtime_put
During gadget driver load: Call pm_runtime_get_sync,
End of gadget driver load: Call pm_runtime_put if there is no device
or cable is connected.
During unload of the gadget driver:Call pm_runtime_get_sync if cable/device
is not connected.
End of the gadget driver unload : pm_runtime_put
During unload of musb driver : Call pm_runtime_get_sync
End of unload: Call pm_runtime_put
On connect of usb cable/device -> transceiver notification(VBUS and ID-GND):
pm_runtime_get_sync only if the gadget driver loaded.
On disconnect of the cable/device -> Disconnect Notification:
pm_runtime_put if the gadget driver is loaded.
Signed-off-by: Hema HK <hemahk@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-02-28 08:49:34 +00:00
|
|
|
pm_runtime_get_sync(musb->controller);
|
|
|
|
|
2011-06-23 12:26:16 +00:00
|
|
|
musb->softconnect = 0;
|
2011-01-17 08:34:38 +00:00
|
|
|
musb->gadget_driver = driver;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2011-01-17 08:34:38 +00:00
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
2013-10-14 20:06:15 +00:00
|
|
|
musb->is_active = 1;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2022-10-26 18:26:53 +00:00
|
|
|
if (musb->xceiv)
|
|
|
|
otg_set_peripheral(musb->xceiv->otg, &musb->g);
|
2022-10-26 18:26:54 +00:00
|
|
|
else
|
|
|
|
phy_set_mode(musb->phy, PHY_MODE_USB_DEVICE);
|
2022-10-26 18:26:53 +00:00
|
|
|
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_B_IDLE);
|
2011-01-17 08:34:38 +00:00
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2013-10-11 08:38:13 +00:00
|
|
|
musb_start(musb);
|
|
|
|
|
2011-11-24 13:46:26 +00:00
|
|
|
/* REVISIT: funcall to other code, which also
|
|
|
|
* handles power budgeting ... this way also
|
|
|
|
* ensures HdrcStart is indirectly called.
|
|
|
|
*/
|
2022-10-26 18:26:53 +00:00
|
|
|
if (musb->xceiv && musb->xceiv->last_event == USB_EVENT_ID)
|
2013-03-24 15:36:55 +00:00
|
|
|
musb_platform_set_vbus(musb, 1);
|
2011-01-17 08:34:38 +00:00
|
|
|
|
2016-05-31 15:05:13 +00:00
|
|
|
pm_runtime_mark_last_busy(musb->controller);
|
|
|
|
pm_runtime_put_autosuspend(musb->controller);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2011-01-17 08:34:38 +00:00
|
|
|
return 0;
|
|
|
|
|
2011-11-24 13:46:26 +00:00
|
|
|
err:
|
2008-07-24 09:27:36 +00:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Unregister the gadget driver. Used by gadget drivers when
|
|
|
|
* unregistering themselves from the controller.
|
|
|
|
*
|
|
|
|
* @param driver the gadget driver to unregister
|
|
|
|
*/
|
2014-10-17 17:05:12 +00:00
|
|
|
static int musb_gadget_stop(struct usb_gadget *g)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
2011-06-23 12:26:16 +00:00
|
|
|
struct musb *musb = gadget_to_musb(g);
|
2011-01-17 08:34:38 +00:00
|
|
|
unsigned long flags;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2016-05-31 15:05:13 +00:00
|
|
|
pm_runtime_get_sync(musb->controller);
|
usb: musb: Idle path retention and offmode support for OMAP3
This patch supports the retention and offmode support in the idle path for
musb driver using runtime pm APIs.
This is restricted to support offmode and retention only when device not
connected.When device/cable connected with gadget driver loaded,configured
to no idle/standby which will not allow the core transition to retention
or off.
There is no context save/restore done by hardware for musb in OMAP3
and OMAP4,driver has to take care of saving and restoring the context
during offmode.
Musb has a requirement of configuring sysconfig register to force
idle/standby mode and set the ENFORCE bit in module STANDBY register
for retention and offmode support.
Runtime pm and hwmod frameworks will take care of configuring to force
idle/standby when pm_runtime_put_sync is called and back to no
idle/standby when pm_runeime_get_sync is called.
Compile, boot tested and also tested the retention in the idle path on
OMAP3630Zoom3. And tested the global suspend/resume with offmode enabled.
Usb basic functionality tested on OMAP4430SDP.
There is some problem with idle path offmode in mainline, I could not test
with offmode. But I have tested this patch with resetting the controller
in the idle path when wakeup from retention just to make sure that the
context is lost, and restore path is working fine.
Removed .suspend/.resume fnction pointers and functions because there
is no need of having these functions as all required work is done
at runtime in the driver.
There is no need to call the runtime pm api with glue driver device
as glue layer device is the parent of musb core device, when runtime apis
are called for the child, parent device runtime functionality
will be invoked.
Design overview:
pm_runtime_get_sync: When called with musb core device takes care of
enabling the clock, calling runtime callback function of omap2430 glue
layer, runtime call back of musb driver and configure the musb sysconfig
to no idle/standby
pm_runtime_put: Takes care of calling runtime callback function of omap2430
glue layer, runtime call back of musb driver, Configure the musb sysconfig
to force idle/standby and disable the clock.
During musb driver load: Call pm_runtime_get_sync.
End of musb driver load: Call pm_runtime_put
During gadget driver load: Call pm_runtime_get_sync,
End of gadget driver load: Call pm_runtime_put if there is no device
or cable is connected.
During unload of the gadget driver:Call pm_runtime_get_sync if cable/device
is not connected.
End of the gadget driver unload : pm_runtime_put
During unload of musb driver : Call pm_runtime_get_sync
End of unload: Call pm_runtime_put
On connect of usb cable/device -> transceiver notification(VBUS and ID-GND):
pm_runtime_get_sync only if the gadget driver loaded.
On disconnect of the cable/device -> Disconnect Notification:
pm_runtime_put if the gadget driver is loaded.
Signed-off-by: Hema HK <hemahk@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-02-28 08:49:34 +00:00
|
|
|
|
2011-01-17 08:34:38 +00:00
|
|
|
/*
|
|
|
|
* REVISIT always use otg_set_peripheral() here too;
|
2008-07-24 09:27:36 +00:00
|
|
|
* this needs to shut down the OTG engine.
|
|
|
|
*/
|
|
|
|
|
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
|
|
|
|
musb_hnp_stop(musb);
|
|
|
|
|
2011-01-17 08:34:38 +00:00
|
|
|
(void) musb_gadget_vbus_draw(&musb->g, 0);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_UNDEFINED);
|
2015-02-02 23:14:12 +00:00
|
|
|
musb_stop(musb);
|
2022-10-26 18:26:53 +00:00
|
|
|
|
|
|
|
if (musb->xceiv)
|
|
|
|
otg_set_peripheral(musb->xceiv->otg, NULL);
|
2022-10-26 18:26:54 +00:00
|
|
|
else
|
|
|
|
phy_set_mode(musb->phy, PHY_MODE_INVALID);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2011-01-17 08:34:38 +00:00
|
|
|
musb->is_active = 0;
|
2013-03-10 00:49:14 +00:00
|
|
|
musb->gadget_driver = NULL;
|
2011-01-17 08:34:38 +00:00
|
|
|
musb_platform_try_idle(musb, 0);
|
2008-07-24 09:27:36 +00:00
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
|
2011-11-24 13:46:26 +00:00
|
|
|
/*
|
|
|
|
* FIXME we need to be able to register another
|
|
|
|
* gadget driver here and have everything work;
|
|
|
|
* that currently misbehaves.
|
|
|
|
*/
|
2011-01-17 08:34:38 +00:00
|
|
|
|
2016-09-22 20:58:29 +00:00
|
|
|
/* Force check of devctl register for PM runtime */
|
2016-05-31 15:05:11 +00:00
|
|
|
pm_runtime_mark_last_busy(musb->controller);
|
|
|
|
pm_runtime_put_autosuspend(musb->controller);
|
usb: musb: Idle path retention and offmode support for OMAP3
This patch supports the retention and offmode support in the idle path for
musb driver using runtime pm APIs.
This is restricted to support offmode and retention only when device not
connected.When device/cable connected with gadget driver loaded,configured
to no idle/standby which will not allow the core transition to retention
or off.
There is no context save/restore done by hardware for musb in OMAP3
and OMAP4,driver has to take care of saving and restoring the context
during offmode.
Musb has a requirement of configuring sysconfig register to force
idle/standby mode and set the ENFORCE bit in module STANDBY register
for retention and offmode support.
Runtime pm and hwmod frameworks will take care of configuring to force
idle/standby when pm_runtime_put_sync is called and back to no
idle/standby when pm_runeime_get_sync is called.
Compile, boot tested and also tested the retention in the idle path on
OMAP3630Zoom3. And tested the global suspend/resume with offmode enabled.
Usb basic functionality tested on OMAP4430SDP.
There is some problem with idle path offmode in mainline, I could not test
with offmode. But I have tested this patch with resetting the controller
in the idle path when wakeup from retention just to make sure that the
context is lost, and restore path is working fine.
Removed .suspend/.resume fnction pointers and functions because there
is no need of having these functions as all required work is done
at runtime in the driver.
There is no need to call the runtime pm api with glue driver device
as glue layer device is the parent of musb core device, when runtime apis
are called for the child, parent device runtime functionality
will be invoked.
Design overview:
pm_runtime_get_sync: When called with musb core device takes care of
enabling the clock, calling runtime callback function of omap2430 glue
layer, runtime call back of musb driver and configure the musb sysconfig
to no idle/standby
pm_runtime_put: Takes care of calling runtime callback function of omap2430
glue layer, runtime call back of musb driver, Configure the musb sysconfig
to force idle/standby and disable the clock.
During musb driver load: Call pm_runtime_get_sync.
End of musb driver load: Call pm_runtime_put
During gadget driver load: Call pm_runtime_get_sync,
End of gadget driver load: Call pm_runtime_put if there is no device
or cable is connected.
During unload of the gadget driver:Call pm_runtime_get_sync if cable/device
is not connected.
End of the gadget driver unload : pm_runtime_put
During unload of musb driver : Call pm_runtime_get_sync
End of unload: Call pm_runtime_put
On connect of usb cable/device -> transceiver notification(VBUS and ID-GND):
pm_runtime_get_sync only if the gadget driver loaded.
On disconnect of the cable/device -> Disconnect Notification:
pm_runtime_put if the gadget driver is loaded.
Signed-off-by: Hema HK <hemahk@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-02-28 08:49:34 +00:00
|
|
|
|
2011-01-17 08:34:38 +00:00
|
|
|
return 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
/* lifecycle operations called through plat_uds.c */
|
|
|
|
|
|
|
|
void musb_g_resume(struct musb *musb)
|
|
|
|
{
|
|
|
|
musb->is_suspended = 0;
|
2022-10-26 18:26:51 +00:00
|
|
|
switch (musb_get_state(musb)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
case OTG_STATE_B_IDLE:
|
|
|
|
break;
|
|
|
|
case OTG_STATE_B_WAIT_ACON:
|
|
|
|
case OTG_STATE_B_PERIPHERAL:
|
|
|
|
musb->is_active = 1;
|
|
|
|
if (musb->gadget_driver && musb->gadget_driver->resume) {
|
|
|
|
spin_unlock(&musb->lock);
|
|
|
|
musb->gadget_driver->resume(&musb->g);
|
|
|
|
spin_lock(&musb->lock);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARNING("unhandled RESUME transition (%s)\n",
|
2022-10-26 18:26:52 +00:00
|
|
|
musb_otg_state_string(musb));
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called when SOF packets stop for 3+ msec */
|
|
|
|
void musb_g_suspend(struct musb *musb)
|
|
|
|
{
|
|
|
|
u8 devctl;
|
|
|
|
|
|
|
|
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2022-10-26 18:26:51 +00:00
|
|
|
switch (musb_get_state(musb)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
case OTG_STATE_B_IDLE:
|
|
|
|
if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
|
2008-07-24 09:27:36 +00:00
|
|
|
break;
|
|
|
|
case OTG_STATE_B_PERIPHERAL:
|
|
|
|
musb->is_suspended = 1;
|
|
|
|
if (musb->gadget_driver && musb->gadget_driver->suspend) {
|
|
|
|
spin_unlock(&musb->lock);
|
|
|
|
musb->gadget_driver->suspend(&musb->g);
|
|
|
|
spin_lock(&musb->lock);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
|
|
|
|
* A_PERIPHERAL may need care too
|
|
|
|
*/
|
2016-06-30 17:12:22 +00:00
|
|
|
WARNING("unhandled SUSPEND transition (%s)",
|
2022-10-26 18:26:52 +00:00
|
|
|
musb_otg_state_string(musb));
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Called during SRP */
|
|
|
|
void musb_g_wakeup(struct musb *musb)
|
|
|
|
{
|
|
|
|
musb_gadget_wakeup(&musb->g);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called when VBUS drops below session threshold, and in other cases */
|
|
|
|
void musb_g_disconnect(struct musb *musb)
|
|
|
|
{
|
|
|
|
void __iomem *mregs = musb->mregs;
|
|
|
|
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
|
|
|
|
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* clear HR */
|
|
|
|
musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
|
|
|
|
|
|
|
|
/* don't draw vbus until new b-default session */
|
|
|
|
(void) musb_gadget_vbus_draw(&musb->g, 0);
|
|
|
|
|
|
|
|
musb->g.speed = USB_SPEED_UNKNOWN;
|
|
|
|
if (musb->gadget_driver && musb->gadget_driver->disconnect) {
|
|
|
|
spin_unlock(&musb->lock);
|
|
|
|
musb->gadget_driver->disconnect(&musb->g);
|
|
|
|
spin_lock(&musb->lock);
|
|
|
|
}
|
|
|
|
|
2022-10-26 18:26:51 +00:00
|
|
|
switch (musb_get_state(musb)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
default:
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
|
2022-10-26 18:26:52 +00:00
|
|
|
musb_otg_state_string(musb));
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_A_IDLE);
|
2009-03-31 19:35:09 +00:00
|
|
|
MUSB_HST_MODE(musb);
|
2008-07-24 09:27:36 +00:00
|
|
|
break;
|
|
|
|
case OTG_STATE_A_PERIPHERAL:
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_A_WAIT_BCON);
|
2009-03-31 19:35:09 +00:00
|
|
|
MUSB_HST_MODE(musb);
|
2008-07-24 09:27:36 +00:00
|
|
|
break;
|
|
|
|
case OTG_STATE_B_WAIT_ACON:
|
|
|
|
case OTG_STATE_B_HOST:
|
|
|
|
case OTG_STATE_B_PERIPHERAL:
|
|
|
|
case OTG_STATE_B_IDLE:
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_B_IDLE);
|
2008-07-24 09:27:36 +00:00
|
|
|
break;
|
|
|
|
case OTG_STATE_B_SRP_INIT:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
musb->is_active = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void musb_g_reset(struct musb *musb)
|
|
|
|
__releases(musb->lock)
|
|
|
|
__acquires(musb->lock)
|
|
|
|
{
|
|
|
|
void __iomem *mbase = musb->mregs;
|
|
|
|
u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
|
|
|
|
u8 power;
|
|
|
|
|
2016-06-30 17:12:22 +00:00
|
|
|
musb_dbg(musb, "<== %s driver '%s'",
|
2008-07-24 09:27:36 +00:00
|
|
|
(devctl & MUSB_DEVCTL_BDEVICE)
|
|
|
|
? "B-Device" : "A-Device",
|
|
|
|
musb->gadget_driver
|
|
|
|
? musb->gadget_driver->driver.name
|
|
|
|
: NULL
|
|
|
|
);
|
|
|
|
|
2014-11-06 06:27:54 +00:00
|
|
|
/* report reset, if we didn't already (flushing EP state) */
|
|
|
|
if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
|
|
|
|
spin_unlock(&musb->lock);
|
|
|
|
usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
|
|
|
|
spin_lock(&musb->lock);
|
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* clear HR */
|
|
|
|
else if (devctl & MUSB_DEVCTL_HR)
|
|
|
|
musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
|
|
|
|
|
|
|
|
|
|
|
|
/* what speed did we negotiate? */
|
|
|
|
power = musb_readb(mbase, MUSB_POWER);
|
|
|
|
musb->g.speed = (power & MUSB_POWER_HSMODE)
|
|
|
|
? USB_SPEED_HIGH : USB_SPEED_FULL;
|
|
|
|
|
|
|
|
/* start in USB_STATE_DEFAULT */
|
|
|
|
musb->is_active = 1;
|
|
|
|
musb->is_suspended = 0;
|
|
|
|
MUSB_DEV_MODE(musb);
|
|
|
|
musb->address = 0;
|
|
|
|
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
|
|
|
|
|
|
|
|
musb->may_wakeup = 0;
|
|
|
|
musb->g.b_hnp_enable = 0;
|
|
|
|
musb->g.a_alt_hnp_support = 0;
|
|
|
|
musb->g.a_hnp_support = 0;
|
2015-07-28 05:20:00 +00:00
|
|
|
musb->g.quirk_zlp_not_supp = 1;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* Normal reset, as B-Device;
|
|
|
|
* or else after HNP, as A-Device
|
|
|
|
*/
|
2013-12-19 20:42:27 +00:00
|
|
|
if (!musb->g.is_otg) {
|
|
|
|
/* USB device controllers that are not OTG compatible
|
|
|
|
* may not have DEVCTL register in silicon.
|
|
|
|
* In that case, do not rely on devctl for setting
|
|
|
|
* peripheral mode.
|
|
|
|
*/
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
|
2013-12-19 20:42:27 +00:00
|
|
|
musb->g.is_a_peripheral = 0;
|
|
|
|
} else if (devctl & MUSB_DEVCTL_BDEVICE) {
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb->g.is_a_peripheral = 0;
|
2011-11-24 13:46:26 +00:00
|
|
|
} else {
|
2022-10-26 18:26:51 +00:00
|
|
|
musb_set_state(musb, OTG_STATE_A_PERIPHERAL);
|
2008-07-24 09:27:36 +00:00
|
|
|
musb->g.is_a_peripheral = 1;
|
2011-11-24 13:46:26 +00:00
|
|
|
}
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* start with default limits on VBUS power draw */
|
2011-11-24 13:46:26 +00:00
|
|
|
(void) musb_gadget_vbus_draw(&musb->g, 8);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|