2019-05-28 16:57:21 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2016-04-27 16:47:12 +00:00
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/*:
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* Hibernate support specific for ARM64
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*
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* Derived from work on ARM hibernation support by:
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*
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* Ubuntu project, hibernation support for mach-dove
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* Copyright (C) 2010 Nokia Corporation (Hiroshi Doyu)
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* Copyright (C) 2010 Texas Instruments, Inc. (Teerth Reddy et al.)
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* https://lkml.org/lkml/2010/6/18/4
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* https://lists.linux-foundation.org/pipermail/linux-pm/2010-June/027422.html
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* https://patchwork.kernel.org/patch/96442/
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*
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* Copyright (C) 2006 Rafael J. Wysocki <rjw@sisk.pl>
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*/
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#define pr_fmt(x) "hibernate: " x
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2016-08-17 12:50:26 +00:00
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#include <linux/cpu.h>
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2016-04-27 16:47:12 +00:00
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#include <linux/kvm_host.h>
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#include <linux/pm.h>
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#include <linux/sched.h>
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#include <linux/suspend.h>
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#include <linux/utsname.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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2016-08-17 12:50:26 +00:00
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#include <asm/cputype.h>
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2017-11-02 12:12:34 +00:00
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#include <asm/daifflags.h>
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2016-04-27 16:47:12 +00:00
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#include <asm/irqflags.h>
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2017-04-03 02:24:35 +00:00
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#include <asm/kexec.h>
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2016-04-27 16:47:12 +00:00
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#include <asm/memory.h>
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#include <asm/mmu_context.h>
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2020-05-13 15:37:51 +00:00
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#include <asm/mte.h>
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2016-04-27 16:47:12 +00:00
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#include <asm/sections.h>
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2016-06-22 09:06:13 +00:00
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#include <asm/smp.h>
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2016-08-17 12:50:26 +00:00
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#include <asm/smp_plat.h>
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2016-04-27 16:47:12 +00:00
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#include <asm/suspend.h>
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arm64: hibernate: avoid potential TLB conflict
In create_safe_exec_page we install a set of global mappings in TTBR0,
then subsequently invalidate TLBs. While TTBR0 points at the zero page,
and the TLBs should be free of stale global entries, we may have stale
ASID-tagged entries (e.g. from the EFI runtime services mappings) for
the same VAs. Per the ARM ARM these ASID-tagged entries may conflict
with newly-allocated global entries, and we must follow a
Break-Before-Make approach to avoid issues resulting from this.
This patch reworks create_safe_exec_page to invalidate TLBs while the
zero page is still in place, ensuring that there are no potential
conflicts when the new TTBR0 value is installed. As a single CPU is
online while this code executes, we do not need to perform broadcast TLB
maintenance, and can call local_flush_tlb_all(), which also subsumes
some barriers. The remaining assembly is converted to use write_sysreg()
and isb().
Other than this, we safely manipulate TTBRs in the hibernate dance. The
code we install as part of the new TTBR0 mapping (the hibernated
kernel's swsusp_arch_suspend_exit) installs a zero page into TTBR1,
invalidates TLBs, then installs its preferred value. Upon being restored
to the middle of swsusp_arch_suspend, the new image will call
__cpu_suspend_exit, which will call cpu_uninstall_idmap, installing the
zero page in TTBR0 and invalidating all TLB entries.
Fixes: 82869ac57b5d ("arm64: kernel: Add support for hibernate/suspend-to-disk")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Tested-by: James Morse <james.morse@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org> # 4.7+
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-08-11 13:11:05 +00:00
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#include <asm/sysreg.h>
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2021-01-25 19:19:08 +00:00
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#include <asm/trans_pgd.h>
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2016-04-27 16:47:12 +00:00
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#include <asm/virt.h>
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/*
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* Hibernate core relies on this value being 0 on resume, and marks it
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* __nosavedata assuming it will keep the resume kernel's '0' value. This
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* doesn't happen with either KASLR.
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*
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* defined as "__visible int in_suspend __nosavedata" in
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* kernel/power/hibernate.c
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*/
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extern int in_suspend;
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/* Do we need to reset el2? */
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2021-09-30 14:30:59 +00:00
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#define el2_reset_needed() (is_hyp_nvhe())
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2016-04-27 16:47:12 +00:00
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/* hyp-stub vectors, used to restore el2 during resume from hibernate. */
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extern char __hyp_stub_vectors[];
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2016-08-17 12:50:26 +00:00
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/*
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* The logical cpu number we should resume on, initialised to a non-cpu
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* number.
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*/
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static int sleep_cpu = -EINVAL;
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2016-04-27 16:47:12 +00:00
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/*
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* Values that may not change over hibernate/resume. We put the build number
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* and date in here so that we guarantee not to resume with a different
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* kernel.
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*/
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struct arch_hibernate_hdr_invariants {
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char uts_version[__NEW_UTS_LEN + 1];
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};
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/* These values need to be know across a hibernate/restore. */
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static struct arch_hibernate_hdr {
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struct arch_hibernate_hdr_invariants invariants;
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/* These are needed to find the relocated kernel if built with kaslr */
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phys_addr_t ttbr1_el1;
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void (*reenter_kernel)(void);
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/*
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* We need to know where the __hyp_stub_vectors are after restore to
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* re-configure el2.
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*/
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phys_addr_t __hyp_stub_vectors;
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2016-08-17 12:50:26 +00:00
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u64 sleep_cpu_mpidr;
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2016-04-27 16:47:12 +00:00
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} resume_hdr;
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static inline void arch_hdr_invariants(struct arch_hibernate_hdr_invariants *i)
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{
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memset(i, 0, sizeof(*i));
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memcpy(i->uts_version, init_utsname()->version, sizeof(i->uts_version));
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}
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int pfn_is_nosave(unsigned long pfn)
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{
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2017-01-10 21:35:49 +00:00
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unsigned long nosave_begin_pfn = sym_to_pfn(&__nosave_begin);
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unsigned long nosave_end_pfn = sym_to_pfn(&__nosave_end - 1);
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2016-04-27 16:47:12 +00:00
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2017-04-03 02:24:35 +00:00
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return ((pfn >= nosave_begin_pfn) && (pfn <= nosave_end_pfn)) ||
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crash_is_nosave(pfn);
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2016-04-27 16:47:12 +00:00
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}
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void notrace save_processor_state(void)
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{
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WARN_ON(num_online_cpus() != 1);
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}
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void notrace restore_processor_state(void)
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{
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}
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int arch_hibernation_header_save(void *addr, unsigned int max_size)
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{
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struct arch_hibernate_hdr *hdr = addr;
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if (max_size < sizeof(*hdr))
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return -EOVERFLOW;
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arch_hdr_invariants(&hdr->invariants);
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2017-01-10 21:35:49 +00:00
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hdr->ttbr1_el1 = __pa_symbol(swapper_pg_dir);
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2016-04-27 16:47:12 +00:00
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hdr->reenter_kernel = _cpu_resume;
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/* We can't use __hyp_get_vectors() because kvm may still be loaded */
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if (el2_reset_needed())
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2017-01-10 21:35:49 +00:00
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hdr->__hyp_stub_vectors = __pa_symbol(__hyp_stub_vectors);
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2016-04-27 16:47:12 +00:00
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else
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hdr->__hyp_stub_vectors = 0;
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2016-08-17 12:50:26 +00:00
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/* Save the mpidr of the cpu we called cpu_suspend() on... */
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if (sleep_cpu < 0) {
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2016-09-17 14:44:17 +00:00
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pr_err("Failing to hibernate on an unknown CPU.\n");
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2016-08-17 12:50:26 +00:00
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return -ENODEV;
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}
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hdr->sleep_cpu_mpidr = cpu_logical_map(sleep_cpu);
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pr_info("Hibernating on CPU %d [mpidr:0x%llx]\n", sleep_cpu,
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hdr->sleep_cpu_mpidr);
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2016-04-27 16:47:12 +00:00
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return 0;
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}
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EXPORT_SYMBOL(arch_hibernation_header_save);
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int arch_hibernation_header_restore(void *addr)
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{
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2016-08-17 12:50:26 +00:00
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int ret;
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2016-04-27 16:47:12 +00:00
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struct arch_hibernate_hdr_invariants invariants;
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struct arch_hibernate_hdr *hdr = addr;
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arch_hdr_invariants(&invariants);
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if (memcmp(&hdr->invariants, &invariants, sizeof(invariants))) {
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pr_crit("Hibernate image not generated by this kernel!\n");
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return -EINVAL;
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}
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2016-08-17 12:50:26 +00:00
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sleep_cpu = get_logical_index(hdr->sleep_cpu_mpidr);
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pr_info("Hibernated on CPU %d [mpidr:0x%llx]\n", sleep_cpu,
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hdr->sleep_cpu_mpidr);
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if (sleep_cpu < 0) {
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pr_crit("Hibernated on a CPU not known to this kernel!\n");
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sleep_cpu = -EINVAL;
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return -EINVAL;
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}
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2020-03-23 13:51:01 +00:00
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ret = bringup_hibernate_cpu(sleep_cpu);
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if (ret) {
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sleep_cpu = -EINVAL;
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return ret;
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2016-08-17 12:50:26 +00:00
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}
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2016-04-27 16:47:12 +00:00
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resume_hdr = *hdr;
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return 0;
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}
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EXPORT_SYMBOL(arch_hibernation_header_restore);
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2021-01-25 19:19:09 +00:00
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static void *hibernate_page_alloc(void *arg)
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{
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2021-02-01 15:03:06 +00:00
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return (void *)get_safe_page((__force gfp_t)(unsigned long)arg);
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2021-01-25 19:19:09 +00:00
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}
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2019-12-04 15:59:23 +00:00
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/*
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* Copies length bytes, starting at src_start into an new page,
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* perform cache maintenance, then maps it at the specified address low
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* address as executable.
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*
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* This is used by hibernate to copy the code it needs to execute when
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* overwriting the kernel text. This function generates a new set of page
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* tables, which it loads into ttbr0.
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*
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* Length is provided as we probably only want 4K of data, even on a 64K
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* page system.
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*/
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static int create_safe_exec_page(void *src_start, size_t length,
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phys_addr_t *phys_dst_addr)
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{
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2021-01-25 19:19:09 +00:00
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struct trans_pgd_info trans_info = {
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.trans_alloc_page = hibernate_page_alloc,
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2021-02-01 15:03:06 +00:00
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.trans_alloc_arg = (__force void *)GFP_ATOMIC,
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2021-01-25 19:19:09 +00:00
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};
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2019-12-04 15:59:23 +00:00
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void *page = (void *)get_safe_page(GFP_ATOMIC);
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2021-01-25 19:19:13 +00:00
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phys_addr_t trans_ttbr0;
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unsigned long t0sz;
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2019-12-04 15:59:23 +00:00
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int rc;
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if (!page)
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return -ENOMEM;
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memcpy(page, src_start, length);
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arm64: Rename arm64-internal cache maintenance functions
Although naming across the codebase isn't that consistent, it
tends to follow certain patterns. Moreover, the term "flush"
isn't defined in the Arm Architecture reference manual, and might
be interpreted to mean clean, invalidate, or both for a cache.
Rename arm64-internal functions to make the naming internally
consistent, as well as making it consistent with the Arm ARM, by
specifying whether it applies to the instruction, data, or both
caches, whether the operation is a clean, invalidate, or both.
Also specify which point the operation applies to, i.e., to the
point of unification (PoU), coherency (PoC), or persistence
(PoP).
This commit applies the following sed transformation to all files
under arch/arm64:
"s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
"s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
"s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
"s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
"s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
"s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
"s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
"s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
"s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
"s/\b__flush_icache_all\b/icache_inval_all_pou/g;"
Note that __clean_dcache_area_poc is deliberately missing a word
boundary check at the beginning in order to match the efistub
symbols in image-vars.h.
Also note that, despite its name, __flush_icache_range operates
on both instruction and data caches. The name change here
reflects that.
No functional change intended.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-05-24 08:30:01 +00:00
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caches_clean_inval_pou((unsigned long)page, (unsigned long)page + length);
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2021-01-25 19:19:13 +00:00
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rc = trans_pgd_idmap_page(&trans_info, &trans_ttbr0, &t0sz, page);
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2019-12-04 15:59:23 +00:00
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if (rc)
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return rc;
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2021-09-30 14:31:01 +00:00
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cpu_install_ttbr0(trans_ttbr0, t0sz);
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2019-12-04 15:59:21 +00:00
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*phys_dst_addr = virt_to_phys(page);
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2016-04-27 16:47:12 +00:00
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2019-12-04 15:59:20 +00:00
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return 0;
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2016-04-27 16:47:12 +00:00
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}
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2020-05-13 15:37:51 +00:00
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#ifdef CONFIG_ARM64_MTE
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static DEFINE_XARRAY(mte_pages);
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static int save_tags(struct page *page, unsigned long pfn)
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{
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void *tag_storage, *ret;
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tag_storage = mte_allocate_tag_storage();
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if (!tag_storage)
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return -ENOMEM;
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mte_save_page_tags(page_address(page), tag_storage);
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ret = xa_store(&mte_pages, pfn, tag_storage, GFP_KERNEL);
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if (WARN(xa_is_err(ret), "Failed to store MTE tags")) {
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mte_free_tag_storage(tag_storage);
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return xa_err(ret);
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} else if (WARN(ret, "swsusp: %s: Duplicate entry", __func__)) {
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mte_free_tag_storage(ret);
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}
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return 0;
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}
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static void swsusp_mte_free_storage(void)
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{
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XA_STATE(xa_state, &mte_pages, 0);
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void *tags;
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xa_lock(&mte_pages);
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xas_for_each(&xa_state, tags, ULONG_MAX) {
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mte_free_tag_storage(tags);
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}
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xa_unlock(&mte_pages);
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xa_destroy(&mte_pages);
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}
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static int swsusp_mte_save_tags(void)
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{
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struct zone *zone;
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unsigned long pfn, max_zone_pfn;
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int ret = 0;
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int n = 0;
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if (!system_supports_mte())
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return 0;
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for_each_populated_zone(zone) {
|
|
|
|
max_zone_pfn = zone_end_pfn(zone);
|
|
|
|
for (pfn = zone->zone_start_pfn; pfn < max_zone_pfn; pfn++) {
|
|
|
|
struct page *page = pfn_to_online_page(pfn);
|
|
|
|
|
|
|
|
if (!page)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!test_bit(PG_mte_tagged, &page->flags))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = save_tags(page, pfn);
|
|
|
|
if (ret) {
|
|
|
|
swsusp_mte_free_storage();
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
pr_info("Saved %d MTE pages\n", n);
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void swsusp_mte_restore_tags(void)
|
|
|
|
{
|
|
|
|
XA_STATE(xa_state, &mte_pages, 0);
|
|
|
|
int n = 0;
|
|
|
|
void *tags;
|
|
|
|
|
|
|
|
xa_lock(&mte_pages);
|
|
|
|
xas_for_each(&xa_state, tags, ULONG_MAX) {
|
|
|
|
unsigned long pfn = xa_state.xa_index;
|
|
|
|
struct page *page = pfn_to_online_page(pfn);
|
|
|
|
|
2020-12-22 20:01:31 +00:00
|
|
|
/*
|
|
|
|
* It is not required to invoke page_kasan_tag_reset(page)
|
|
|
|
* at this point since the tags stored in page->flags are
|
|
|
|
* already restored.
|
|
|
|
*/
|
2020-05-13 15:37:51 +00:00
|
|
|
mte_restore_page_tags(page_address(page), tags);
|
|
|
|
|
|
|
|
mte_free_tag_storage(tags);
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
xa_unlock(&mte_pages);
|
|
|
|
|
|
|
|
pr_info("Restored %d MTE pages\n", n);
|
|
|
|
|
|
|
|
xa_destroy(&mte_pages);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else /* CONFIG_ARM64_MTE */
|
|
|
|
|
|
|
|
static int swsusp_mte_save_tags(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void swsusp_mte_restore_tags(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_ARM64_MTE */
|
|
|
|
|
2016-04-27 16:47:12 +00:00
|
|
|
int swsusp_arch_suspend(void)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
unsigned long flags;
|
|
|
|
struct sleep_stack_data state;
|
|
|
|
|
2016-06-22 09:06:13 +00:00
|
|
|
if (cpus_are_stuck_in_kernel()) {
|
|
|
|
pr_err("Can't hibernate: no mechanism to offline secondary CPUs.\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2017-11-02 12:12:34 +00:00
|
|
|
flags = local_daif_save();
|
2016-04-27 16:47:12 +00:00
|
|
|
|
|
|
|
if (__cpu_suspend_enter(&state)) {
|
2017-04-03 02:24:35 +00:00
|
|
|
/* make the crash dump kernel image visible/saveable */
|
|
|
|
crash_prepare_suspend();
|
|
|
|
|
2020-05-13 15:37:51 +00:00
|
|
|
ret = swsusp_mte_save_tags();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-08-17 12:50:26 +00:00
|
|
|
sleep_cpu = smp_processor_id();
|
2016-04-27 16:47:12 +00:00
|
|
|
ret = swsusp_save();
|
|
|
|
} else {
|
2016-08-24 17:27:30 +00:00
|
|
|
/* Clean kernel core startup/idle code to PoC*/
|
arm64: Rename arm64-internal cache maintenance functions
Although naming across the codebase isn't that consistent, it
tends to follow certain patterns. Moreover, the term "flush"
isn't defined in the Arm Architecture reference manual, and might
be interpreted to mean clean, invalidate, or both for a cache.
Rename arm64-internal functions to make the naming internally
consistent, as well as making it consistent with the Arm ARM, by
specifying whether it applies to the instruction, data, or both
caches, whether the operation is a clean, invalidate, or both.
Also specify which point the operation applies to, i.e., to the
point of unification (PoU), coherency (PoC), or persistence
(PoP).
This commit applies the following sed transformation to all files
under arch/arm64:
"s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
"s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
"s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
"s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
"s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
"s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
"s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
"s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
"s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
"s/\b__flush_icache_all\b/icache_inval_all_pou/g;"
Note that __clean_dcache_area_poc is deliberately missing a word
boundary check at the beginning in order to match the efistub
symbols in image-vars.h.
Also note that, despite its name, __flush_icache_range operates
on both instruction and data caches. The name change here
reflects that.
No functional change intended.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-05-24 08:30:01 +00:00
|
|
|
dcache_clean_inval_poc((unsigned long)__mmuoff_data_start,
|
2021-05-24 08:29:55 +00:00
|
|
|
(unsigned long)__mmuoff_data_end);
|
arm64: Rename arm64-internal cache maintenance functions
Although naming across the codebase isn't that consistent, it
tends to follow certain patterns. Moreover, the term "flush"
isn't defined in the Arm Architecture reference manual, and might
be interpreted to mean clean, invalidate, or both for a cache.
Rename arm64-internal functions to make the naming internally
consistent, as well as making it consistent with the Arm ARM, by
specifying whether it applies to the instruction, data, or both
caches, whether the operation is a clean, invalidate, or both.
Also specify which point the operation applies to, i.e., to the
point of unification (PoU), coherency (PoC), or persistence
(PoP).
This commit applies the following sed transformation to all files
under arch/arm64:
"s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
"s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
"s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
"s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
"s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
"s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
"s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
"s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
"s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
"s/\b__flush_icache_all\b/icache_inval_all_pou/g;"
Note that __clean_dcache_area_poc is deliberately missing a word
boundary check at the beginning in order to match the efistub
symbols in image-vars.h.
Also note that, despite its name, __flush_icache_range operates
on both instruction and data caches. The name change here
reflects that.
No functional change intended.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-05-24 08:30:01 +00:00
|
|
|
dcache_clean_inval_poc((unsigned long)__idmap_text_start,
|
2021-05-24 08:29:55 +00:00
|
|
|
(unsigned long)__idmap_text_end);
|
2016-08-24 17:27:30 +00:00
|
|
|
|
|
|
|
/* Clean kvm setup code to PoC? */
|
2019-01-24 16:32:57 +00:00
|
|
|
if (el2_reset_needed()) {
|
arm64: Rename arm64-internal cache maintenance functions
Although naming across the codebase isn't that consistent, it
tends to follow certain patterns. Moreover, the term "flush"
isn't defined in the Arm Architecture reference manual, and might
be interpreted to mean clean, invalidate, or both for a cache.
Rename arm64-internal functions to make the naming internally
consistent, as well as making it consistent with the Arm ARM, by
specifying whether it applies to the instruction, data, or both
caches, whether the operation is a clean, invalidate, or both.
Also specify which point the operation applies to, i.e., to the
point of unification (PoU), coherency (PoC), or persistence
(PoP).
This commit applies the following sed transformation to all files
under arch/arm64:
"s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
"s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
"s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
"s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
"s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
"s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
"s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
"s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
"s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
"s/\b__flush_icache_all\b/icache_inval_all_pou/g;"
Note that __clean_dcache_area_poc is deliberately missing a word
boundary check at the beginning in order to match the efistub
symbols in image-vars.h.
Also note that, despite its name, __flush_icache_range operates
on both instruction and data caches. The name change here
reflects that.
No functional change intended.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-05-24 08:30:01 +00:00
|
|
|
dcache_clean_inval_poc(
|
2021-05-24 08:29:55 +00:00
|
|
|
(unsigned long)__hyp_idmap_text_start,
|
|
|
|
(unsigned long)__hyp_idmap_text_end);
|
arm64: Rename arm64-internal cache maintenance functions
Although naming across the codebase isn't that consistent, it
tends to follow certain patterns. Moreover, the term "flush"
isn't defined in the Arm Architecture reference manual, and might
be interpreted to mean clean, invalidate, or both for a cache.
Rename arm64-internal functions to make the naming internally
consistent, as well as making it consistent with the Arm ARM, by
specifying whether it applies to the instruction, data, or both
caches, whether the operation is a clean, invalidate, or both.
Also specify which point the operation applies to, i.e., to the
point of unification (PoU), coherency (PoC), or persistence
(PoP).
This commit applies the following sed transformation to all files
under arch/arm64:
"s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
"s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
"s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
"s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
"s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
"s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
"s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
"s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
"s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
"s/\b__flush_icache_all\b/icache_inval_all_pou/g;"
Note that __clean_dcache_area_poc is deliberately missing a word
boundary check at the beginning in order to match the efistub
symbols in image-vars.h.
Also note that, despite its name, __flush_icache_range operates
on both instruction and data caches. The name change here
reflects that.
No functional change intended.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-05-24 08:30:01 +00:00
|
|
|
dcache_clean_inval_poc((unsigned long)__hyp_text_start,
|
2021-05-24 08:29:55 +00:00
|
|
|
(unsigned long)__hyp_text_end);
|
2019-01-24 16:32:57 +00:00
|
|
|
}
|
2016-04-27 16:47:12 +00:00
|
|
|
|
2020-05-13 15:37:51 +00:00
|
|
|
swsusp_mte_restore_tags();
|
|
|
|
|
2017-04-03 02:24:35 +00:00
|
|
|
/* make the crash dump kernel image protected again */
|
|
|
|
crash_post_resume();
|
|
|
|
|
2016-04-27 16:47:12 +00:00
|
|
|
/*
|
|
|
|
* Tell the hibernation core that we've just restored
|
|
|
|
* the memory
|
|
|
|
*/
|
|
|
|
in_suspend = 0;
|
|
|
|
|
2016-08-17 12:50:26 +00:00
|
|
|
sleep_cpu = -EINVAL;
|
2016-04-27 16:47:12 +00:00
|
|
|
__cpu_suspend_exit();
|
2018-05-29 12:11:12 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Just in case the boot kernel did turn the SSBD
|
|
|
|
* mitigation off behind our back, let's set the state
|
|
|
|
* to what we expect it to be.
|
|
|
|
*/
|
2020-09-18 10:54:33 +00:00
|
|
|
spectre_v4_enable_mitigation(NULL);
|
2016-04-27 16:47:12 +00:00
|
|
|
}
|
|
|
|
|
2017-11-02 12:12:34 +00:00
|
|
|
local_daif_restore(flags);
|
2016-04-27 16:47:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup then Resume from the hibernate image using swsusp_arch_suspend_exit().
|
|
|
|
*
|
|
|
|
* Memory allocated by get_safe_page() will be dealt with by the hibernate code,
|
|
|
|
* we don't need to free it here.
|
|
|
|
*/
|
|
|
|
int swsusp_arch_resume(void)
|
|
|
|
{
|
2019-12-04 15:59:20 +00:00
|
|
|
int rc;
|
2016-04-27 16:47:12 +00:00
|
|
|
void *zero_page;
|
|
|
|
size_t exit_size;
|
|
|
|
pgd_t *tmp_pg_dir;
|
2021-09-30 14:31:00 +00:00
|
|
|
phys_addr_t el2_vectors;
|
2016-04-27 16:47:12 +00:00
|
|
|
void __noreturn (*hibernate_exit)(phys_addr_t, phys_addr_t, void *,
|
|
|
|
void *, phys_addr_t, phys_addr_t);
|
2021-01-25 19:19:10 +00:00
|
|
|
struct trans_pgd_info trans_info = {
|
|
|
|
.trans_alloc_page = hibernate_page_alloc,
|
|
|
|
.trans_alloc_arg = (void *)GFP_ATOMIC,
|
|
|
|
};
|
2016-04-27 16:47:12 +00:00
|
|
|
|
arm64: hibernate: handle allocation failures
In create_safe_exec_page(), we create a copy of the hibernate exit text,
along with some page tables to map this via TTBR0. We then install the
new tables in TTBR0.
In swsusp_arch_resume() we call create_safe_exec_page() before trying a
number of operations which may fail (e.g. copying the linear map page
tables). If these fail, we bail out of swsusp_arch_resume() and return
an error code, but leave TTBR0 as-is. Subsequently, the core hibernate
code will call free_basic_memory_bitmaps(), which will free all of the
memory allocations we made, including the page tables installed in
TTBR0.
Thus, we may have TTBR0 pointing at dangling freed memory for some
period of time. If the hibernate attempt was triggered by a user
requesting a hibernate test via the reboot syscall, we may return to
userspace with the clobbered TTBR0 value.
Avoid these issues by reorganising swsusp_arch_resume() such that we
have no failure paths after create_safe_exec_page(). We also add a check
that the zero page allocation succeeded, matching what we have for other
allocations.
Fixes: 82869ac57b5d ("arm64: kernel: Add support for hibernate/suspend-to-disk")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org> # 4.7+
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-08-11 13:11:06 +00:00
|
|
|
/*
|
|
|
|
* Restoring the memory image will overwrite the ttbr1 page tables.
|
|
|
|
* Create a second copy of just the linear map, and use this when
|
|
|
|
* restoring.
|
|
|
|
*/
|
2021-01-25 19:19:10 +00:00
|
|
|
rc = trans_pgd_create_copy(&trans_info, &tmp_pg_dir, PAGE_OFFSET,
|
|
|
|
PAGE_END);
|
arm64: hibernate: handle allocation failures
In create_safe_exec_page(), we create a copy of the hibernate exit text,
along with some page tables to map this via TTBR0. We then install the
new tables in TTBR0.
In swsusp_arch_resume() we call create_safe_exec_page() before trying a
number of operations which may fail (e.g. copying the linear map page
tables). If these fail, we bail out of swsusp_arch_resume() and return
an error code, but leave TTBR0 as-is. Subsequently, the core hibernate
code will call free_basic_memory_bitmaps(), which will free all of the
memory allocations we made, including the page tables installed in
TTBR0.
Thus, we may have TTBR0 pointing at dangling freed memory for some
period of time. If the hibernate attempt was triggered by a user
requesting a hibernate test via the reboot syscall, we may return to
userspace with the clobbered TTBR0 value.
Avoid these issues by reorganising swsusp_arch_resume() such that we
have no failure paths after create_safe_exec_page(). We also add a check
that the zero page allocation succeeded, matching what we have for other
allocations.
Fixes: 82869ac57b5d ("arm64: kernel: Add support for hibernate/suspend-to-disk")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org> # 4.7+
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-08-11 13:11:06 +00:00
|
|
|
if (rc)
|
2019-12-04 15:59:20 +00:00
|
|
|
return rc;
|
arm64: hibernate: handle allocation failures
In create_safe_exec_page(), we create a copy of the hibernate exit text,
along with some page tables to map this via TTBR0. We then install the
new tables in TTBR0.
In swsusp_arch_resume() we call create_safe_exec_page() before trying a
number of operations which may fail (e.g. copying the linear map page
tables). If these fail, we bail out of swsusp_arch_resume() and return
an error code, but leave TTBR0 as-is. Subsequently, the core hibernate
code will call free_basic_memory_bitmaps(), which will free all of the
memory allocations we made, including the page tables installed in
TTBR0.
Thus, we may have TTBR0 pointing at dangling freed memory for some
period of time. If the hibernate attempt was triggered by a user
requesting a hibernate test via the reboot syscall, we may return to
userspace with the clobbered TTBR0 value.
Avoid these issues by reorganising swsusp_arch_resume() such that we
have no failure paths after create_safe_exec_page(). We also add a check
that the zero page allocation succeeded, matching what we have for other
allocations.
Fixes: 82869ac57b5d ("arm64: kernel: Add support for hibernate/suspend-to-disk")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org> # 4.7+
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-08-11 13:11:06 +00:00
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/*
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* We need a zero page that is zero before & after resume in order to
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* to break before make on the ttbr1 page tables.
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*/
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zero_page = (void *)get_safe_page(GFP_ATOMIC);
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if (!zero_page) {
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2017-01-09 14:13:36 +00:00
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pr_err("Failed to allocate zero page.\n");
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2019-12-04 15:59:20 +00:00
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return -ENOMEM;
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arm64: hibernate: handle allocation failures
In create_safe_exec_page(), we create a copy of the hibernate exit text,
along with some page tables to map this via TTBR0. We then install the
new tables in TTBR0.
In swsusp_arch_resume() we call create_safe_exec_page() before trying a
number of operations which may fail (e.g. copying the linear map page
tables). If these fail, we bail out of swsusp_arch_resume() and return
an error code, but leave TTBR0 as-is. Subsequently, the core hibernate
code will call free_basic_memory_bitmaps(), which will free all of the
memory allocations we made, including the page tables installed in
TTBR0.
Thus, we may have TTBR0 pointing at dangling freed memory for some
period of time. If the hibernate attempt was triggered by a user
requesting a hibernate test via the reboot syscall, we may return to
userspace with the clobbered TTBR0 value.
Avoid these issues by reorganising swsusp_arch_resume() such that we
have no failure paths after create_safe_exec_page(). We also add a check
that the zero page allocation succeeded, matching what we have for other
allocations.
Fixes: 82869ac57b5d ("arm64: kernel: Add support for hibernate/suspend-to-disk")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org> # 4.7+
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-08-11 13:11:06 +00:00
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}
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2021-09-30 14:31:00 +00:00
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if (el2_reset_needed()) {
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rc = trans_pgd_copy_el2_vectors(&trans_info, &el2_vectors);
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if (rc) {
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pr_err("Failed to setup el2 vectors\n");
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return rc;
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}
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}
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2016-04-27 16:47:12 +00:00
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exit_size = __hibernate_exit_text_end - __hibernate_exit_text_start;
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/*
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* Copy swsusp_arch_suspend_exit() to a safe page. This will generate
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* a new set of ttbr0 page tables and load them.
|
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|
|
*/
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|
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rc = create_safe_exec_page(__hibernate_exit_text_start, exit_size,
|
2021-01-25 19:19:13 +00:00
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|
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(phys_addr_t *)&hibernate_exit);
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2016-04-27 16:47:12 +00:00
|
|
|
if (rc) {
|
2017-01-09 14:13:36 +00:00
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|
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pr_err("Failed to create safe executable page for hibernate_exit code.\n");
|
2019-12-04 15:59:20 +00:00
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|
|
return rc;
|
2016-04-27 16:47:12 +00:00
|
|
|
}
|
|
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|
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|
|
|
/*
|
|
|
|
* KASLR will cause the el2 vectors to be in a different location in
|
|
|
|
* the resumed kernel. Load hibernate's temporary copy into el2.
|
|
|
|
*
|
|
|
|
* We can skip this step if we booted at EL1, or are running with VHE.
|
|
|
|
*/
|
2021-09-30 14:31:00 +00:00
|
|
|
if (el2_reset_needed())
|
2016-04-27 16:47:12 +00:00
|
|
|
__hyp_set_vectors(el2_vectors);
|
|
|
|
|
|
|
|
hibernate_exit(virt_to_phys(tmp_pg_dir), resume_hdr.ttbr1_el1,
|
2017-01-10 21:35:49 +00:00
|
|
|
resume_hdr.reenter_kernel, restore_pblist,
|
2016-04-27 16:47:12 +00:00
|
|
|
resume_hdr.__hyp_stub_vectors, virt_to_phys(zero_page));
|
|
|
|
|
2019-12-04 15:59:20 +00:00
|
|
|
return 0;
|
2016-04-27 16:47:12 +00:00
|
|
|
}
|
2016-04-27 16:47:13 +00:00
|
|
|
|
2016-08-17 12:50:26 +00:00
|
|
|
int hibernate_resume_nonboot_cpu_disable(void)
|
|
|
|
{
|
|
|
|
if (sleep_cpu < 0) {
|
2016-09-17 14:44:17 +00:00
|
|
|
pr_err("Failing to resume from hibernate on an unknown CPU.\n");
|
2016-08-17 12:50:26 +00:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return freeze_secondary_cpus(sleep_cpu);
|
|
|
|
}
|