2021-07-18 11:40:48 +00:00
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare PCIe interface
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maintainers:
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- Jingoo Han <jingoohan1@gmail.com>
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- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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description: |
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Synopsys DesignWare PCIe host controller
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2022-11-13 19:12:48 +00:00
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# Please create a separate DT-schema for your DWC PCIe Root Port controller
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# and make sure it's assigned with the vendor-specific compatible string.
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select:
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properties:
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compatible:
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const: snps,dw-pcie
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required:
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- compatible
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2021-07-18 11:40:48 +00:00
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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dt-bindings: PCI: dwc: Detach common RP/EP DT bindings
Currently both DW PCIe Root Port and End-point DT bindings are defined as
separate schemas. Carefully looking at them, at the hardware reference
manuals and seeing there is a generic part of the driver used by the both
RP and EP drivers we can greatly simplify the DW PCIe controller bindings
by moving some of the properties into the common DT schema. It concerns
the PERST GPIO control, number of lanes, number of iATU windows and CDM
check properties. They will be defined in the snps,dw-pcie-common.yaml
schema which will be referenced in the DW PCIe Root Port and End-point DT
bindings in order to evaluate the common for both of these controllers
properties. The rest of properties like reg{,-names}, clock{s,-names},
reset{s,-names}, etc will be consolidate there in one of the next commits.
Link: https://lore.kernel.org/r/20221113191301.5526-4-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-13 19:12:44 +00:00
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- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
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2023-07-31 16:57:19 +00:00
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- if:
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not:
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required:
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- msi-map
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then:
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properties:
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interrupt-names:
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contains:
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const: msi
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2021-07-18 11:40:48 +00:00
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properties:
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reg:
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2022-11-13 19:12:51 +00:00
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description:
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At least DBI reg-space and peripheral devices CFG-space outbound window
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are required for the normal controller work. iATU memory IO region is
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also required if the space is unrolled (IP-core version >= 4.80a).
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2021-07-18 11:40:48 +00:00
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minItems: 2
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2023-10-18 08:56:25 +00:00
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maxItems: 7
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2021-07-18 11:40:48 +00:00
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reg-names:
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minItems: 2
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2023-10-18 08:56:25 +00:00
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maxItems: 7
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2021-07-18 11:40:48 +00:00
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items:
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2022-11-13 19:12:51 +00:00
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oneOf:
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- description:
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Basic DWC PCIe controller configuration-space accessible over
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the DBI interface. This memory space is either activated with
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CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
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with all spaces. Note iATU/eDMA CSRs are indirectly accessible
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via the PL viewports on the DWC PCIe controllers older than
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v4.80a.
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const: dbi
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- description:
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Shadow DWC PCIe config-space registers. This space is selected
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by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
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the PCI-SIG PCIe CFG-space with the shadow registers for some
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PCI Header space, PCI Standard and Extended Structures. It's
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mainly relevant for the end-point controller configuration,
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but still there are some shadow registers available for the
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Root Port mode too.
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const: dbi2
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- description:
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External Local Bus registers. It's an application-dependent
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registers normally defined by the platform engineers. The space
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can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
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be accessed over some platform-specific means (for instance
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as a part of a system controller).
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enum: [ elbi, app ]
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- description:
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iATU/eDMA registers common for all device functions. It's an
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unrolled memory space with the internal Address Translation
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Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
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and CS2 = 1. For IP-core releases prior v4.80a, these registers
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have been programmed via an indirect addressing scheme using a
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set of viewport CSRs mapped into the PL space. Note iATU is
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normally mapped to the 0x0 address of this region, while eDMA
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is available at 0x80000 base address.
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const: atu
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- description:
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Platform-specific eDMA registers. Some platforms may have eDMA
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CSRs mapped in a non-standard base address. The registers offset
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can be changed or the MS/LS-bits of the address can be attached
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in an additional RTL block before the MEM-IO transactions reach
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the DW PCIe slave interface.
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const: dma
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- description:
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PHY/PCS configuration registers. Some platforms can have the
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PCS and PHY CSRs accessible over a dedicated memory mapped
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region, but mainly these registers are indirectly accessible
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either by means of the embedded PHY viewport schema or by some
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platform-specific method.
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const: phy
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- description:
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Outbound iATU-capable memory-region which will be used to access
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the peripheral PCIe devices configuration space.
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const: config
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- description:
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Vendor-specific CSR names. Consider using the generic names above
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for new bindings.
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oneOf:
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- description: See native 'elbi/app' CSR region for details.
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enum: [ apb, mgmt, link, ulreg, appl ]
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- description: See native 'atu' CSR region for details.
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enum: [ atu_dma ]
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- description: Syscon-related CSR regions.
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enum: [ smu, mpu ]
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pci-v6.2-changes
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AmDIpg1Idxo8fEPPGH1I7RVU5+ilzmmPQQY7poQW+va4/dEd/QVp1+ZZTDnMC1qk
qi3ck22VdvPU2VU=
=KULr
-----END PGP SIGNATURE-----
Merge tag 'pci-v6.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Squash portdrv_{core,pci}.c into portdrv.c to ease maintenance and
make more things static.
- Make portdrv bind to Switch Ports that have AER. Previously, if
these Ports lacked MSI/MSI-X, portdrv failed to bind, which meant
the Ports couldn't be suspended to low-power states. AER on these
Ports doesn't use interrupts, and the AER driver doesn't need to
claim them.
- Assign PCI domain IDs using ida_alloc(), which makes host bridge
add/remove work better.
Resource management:
- To work better with recent BIOSes that use EfiMemoryMappedIO for
PCI host bridge apertures, remove those regions from the E820 map
(E820 entries normally prevent us from allocating BARs). In v5.19,
we added some quirks to disable E820 checking, but that's not very
maintainable. EfiMemoryMappedIO means the OS needs to map the
region for use by EFI runtime services; it shouldn't prevent OS
from using it.
PCIe native device hotplug:
- Build pciehp by default if USB4 is enabled, since Thunderbolt/USB4
PCIe tunneling depends on native PCIe hotplug.
- Enable Command Completed Interrupt only if supported to avoid user
confusion from lspci output that says this is enabled but not
supported.
- Prevent pciehp from binding to Switch Upstream Ports; this happened
because of interaction with acpiphp and caused devices below the
Upstream Port to disappear.
Power management:
- Convert AGP drivers to generic power management. We hope to remove
legacy power management from the PCI core eventually.
Virtualization:
- Fix pci_device_is_present(), which previously always returned
"false" for VFs, causing virtio hangs when unbinding the driver.
Miscellaneous:
- Convert drivers to gpiod API to prepare for dropping some legacy
code.
- Fix DOE fencepost error for the maximum data object length.
Baikal-T1 PCIe controller driver:
- Add driver and DT bindings.
Broadcom STB PCIe controller driver:
- Enable Multi-MSI.
- Delay 100ms after PERST# deassert to allow power and clocks to
stabilize.
- Configure Read Completion Boundary to 64 bytes.
Freescale i.MX6 PCIe controller driver:
- Initialize PHY before deasserting core reset to fix a regression in
v6.0 on boards where the PHY provides the reference.
- Fix imx6sx and imx8mq clock names in DT schema.
Intel VMD host bridge driver:
- Fix Secondary Bus Reset on VMD bridges, which allows reset of NVMe
SSDs in VT-d pass-through scenarios.
- Disable MSI remapping, which gets re-enabled by firmware during
suspend/resume.
MediaTek PCIe Gen3 controller driver:
- Add MT7986 and MT8195 support.
Qualcomm PCIe controller driver:
- Add SC8280XP/SA8540P basic interconnect support.
Rockchip DesignWare PCIe controller driver:
- Base DT schema on common Synopsys schema.
Synopsys DesignWare PCIe core:
- Collect DT items shared between Root Port and Endpoint (PERST GPIO,
PHY info, clocks, resets, link speed, number of lanes, number of
iATU windows, interrupt info, etc) to snps,dw-pcie-common.yaml.
- Add dma-ranges support for Root Ports and Endpoints.
- Consolidate DT resource retrieval for "dbi", "dbi2", "atu", etc. to
reduce code duplication.
- Add generic names for clocks and resets to encourage more
consistent naming across drivers using DesignWare IP.
- Stop advertising PTM Responder role for Endpoints, which aren't
allowed to be responders.
TI J721E PCIe driver:
- Add j721s2 host mode ID to DT schema.
- Add interrupt properties to DT schema.
Toshiba Visconti PCIe controller driver:
- Fix interrupts array max constraints in DT schema"
* tag 'pci-v6.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (95 commits)
x86/PCI: Use pr_info() when possible
x86/PCI: Fix log message typo
x86/PCI: Tidy E820 removal messages
PCI: Skip allocate_resource() if too little space available
efi/x86: Remove EfiMemoryMappedIO from E820 map
PCI/portdrv: Allow AER service only for Root Ports & RCECs
PCI: xilinx-nwl: Fix coding style violations
PCI: mvebu: Switch to using gpiod API
PCI: pciehp: Enable Command Completed Interrupt only if supported
PCI: aardvark: Switch to using devm_gpiod_get_optional()
dt-bindings: PCI: mediatek-gen3: add support for mt7986
dt-bindings: PCI: mediatek-gen3: add SoC based clock config
dt-bindings: PCI: qcom: Allow 'dma-coherent' property
PCI: mt7621: Add sentinel to quirks table
PCI: vmd: Fix secondary bus reset for Intel bridges
PCI: endpoint: pci-epf-vntb: Fix sparse ntb->reg build warning
PCI: endpoint: pci-epf-vntb: Fix sparse build warning for epf_db
PCI: endpoint: pci-epf-vntb: Replace hardcoded 4 with sizeof(u32)
PCI: endpoint: pci-epf-vntb: Remove unused epf_db_phy struct member
PCI: endpoint: pci-epf-vntb: Fix call pci_epc_mem_free_addr() in error path
...
2022-12-14 17:54:10 +00:00
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- description: Tegra234 aperture
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enum: [ ecam ]
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2022-11-13 19:12:51 +00:00
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allOf:
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- contains:
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const: dbi
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- contains:
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const: config
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2021-07-18 11:40:48 +00:00
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2022-11-13 19:12:50 +00:00
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interrupts:
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description:
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DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
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signal is supposed to be specified for the host controller.
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minItems: 1
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maxItems: 26
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interrupt-names:
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minItems: 1
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maxItems: 26
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items:
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oneOf:
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- description:
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Controller request to read or write virtual product data
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from/to the VPD capability registers.
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const: vpd
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- description:
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Link Equalization Request flag is set in the Link Status 2
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register (applicable if the corresponding IRQ is enabled in
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the Link Control 3 register).
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const: l_eq
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- description:
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Indicates that the eDMA Tx/Rx transfer is complete or that an
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error has occurred on the corresponding channel. eDMA can have
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eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
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to 16 IRQ signals all together. Write eDMA channels shall go
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first in the ordered row as per default edma_int[*] bus setup.
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pattern: '^dma([0-9]|1[0-5])?$'
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- description:
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PCIe protocol correctable error or a Data Path protection
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correctable error is detected by the automotive/safety
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feature.
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const: sft_ce
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- description:
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Indicates that the internal safety mechanism has detected an
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uncorrectable error.
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const: sft_ue
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- description:
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Application-specific IRQ raised depending on the vendor-specific
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events basis.
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const: app
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- description:
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DSP AXI MSI Interrupt detected. It gets de-asserted when there is
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no more MSI interrupt pending. The interrupt is relevant to the
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iMSI-RX - Integrated MSI Receiver (AXI bridge).
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const: msi
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- description:
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Legacy A/B/C/D interrupt signal. Basically it's triggered by
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receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message
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from the downstream device.
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pattern: "^int(a|b|c|d)$"
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- description:
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Error condition detected and a flag is set in the Root Error Status
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register of the AER capability. It's asserted when the RC
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internally generated an error or an error message is received by
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the RC.
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const: aer
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- description:
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PME message is received by the port. That means having the PME
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status bit set in the Root Status register (the event is
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supposed to be unmasked in the Root Control register).
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const: pme
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- description:
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Hot-plug event is detected. That is a bit has been set in the
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Slot Status register and the corresponding event is enabled in
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the Slot Control register.
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const: hp
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- description:
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Link Autonomous Bandwidth Status flag has been set in the Link
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Status register (the event is supposed to be unmasked in the
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Link Control register).
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const: bw_au
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- description:
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Bandwidth Management Status flag has been set in the Link
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Status register (the event is supposed to be unmasked in the
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Link Control register).
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const: bw_mg
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2023-07-31 16:57:21 +00:00
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- description:
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Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for
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details.
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const: legacy
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2022-11-13 19:12:50 +00:00
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- description:
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Vendor-specific IRQ names. Consider using the generic names above
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for new bindings.
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oneOf:
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- description: See native "app" IRQ for details
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2023-07-31 16:57:21 +00:00
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enum: [ intr, sys, pmc, msg, err ]
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2021-07-18 11:40:48 +00:00
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dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warnings
With 'unevaluatedProperties' support implemented, there's a number of
warnings from the Designware PCIe based bindings:
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dt.yaml: pcie@1ffc000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type', 'bus-range', 'ranges', '#interrupt-cells', 'interrupt-map-mask', 'interrupt-map' were unexpected)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dt.yaml: pcie@1ffc000: Unevaluated properties are not allowed ('clock-names' was unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: Unevaluated properties are not allowed ('bus-range', '#address-cells', '#size-cells', 'device_type', 'ranges', 'num-lanes', '#interrupt-cells', 'interrupts', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'clocks', 'clock-names' were unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: Unevaluated properties are not allowed ('clock-names' was unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: Unevaluated properties are not allowed ('bus-range', '#address-cells', '#size-cells', 'device_type', 'phys', 'ranges', 'num-lanes', '#interrupt-cells', 'interrupts', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'reset-gpios', 'pcie@0,0' were unexpected)
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: Unevaluated properties are not allowed ('phys', 'hisilicon,clken-gpios' were unexpected)
Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dt.yaml: pcie@d0e00000: Unevaluated properties are not allowed ('device_type', '#address-cells', '#size-cells', 'linux,pci-domain', 'bus-range', '#interrupt-cells', 'interrupt-map-mask', 'interrupt-map' were unexpected)
Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dt.yaml: pcie@d0e00000: Unevaluated properties are not allowed ('resets', 'phys', 'phy-names', 'reset-assert-ms' were unexpected)
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.example.dt.yaml: pcie@fe280000: Unevaluated properties are not allowed ('clock-names', 'msi-map', 'phys', 'phy-names', 'power-domains', 'resets', 'reset-names' were unexpected)
Documentation/devicetree/bindings/pci/samsung,exynos-pcie.example.dt.yaml: pcie@15700000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', '#interrupt-cells', 'device_type', 'bus-range', 'ranges', 'interrupt-map-mask', 'interrupt-map' were unexpected)
Documentation/devicetree/bindings/pci/samsung,exynos-pcie.example.dt.yaml: pcie@15700000: Unevaluated properties are not allowed ('clock-names', 'phys', 'vdd10-supply', 'vdd18-supply' were unexpected)
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml: pcie@e00000000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', '#interrupt-cells', 'device_type', 'dma-coherent', 'bus-range', 'ranges', 'interrupts', 'interrupt-parent', 'interrupt-map-mask', 'interrupt-map', 'clock-names', 'clocks' were unexpected)
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml: pcie@e00000000: Unevaluated properties are not allowed ('dma-coherent', 'clock-names', 'resets', 'pwren-gpios' were unexpected)
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.example.dt.yaml: pcie-ep@66000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'reset-names', 'resets', 'phy-names', 'phys' were unexpected)
Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.example.dt.yaml: pcie@28400000: Unevaluated properties are not allowed ('clock-names' was unexpected)
Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.example.dt.yaml: pcie@28400000: Unevaluated properties are not allowed ('device_type', 'bus-range', 'num-viewport', '#address-cells', '#size-cells', '#interrupt-cells', 'ranges', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'max-link-speed' were unexpected)
The main problem is that snps,dw-pcie.yaml and snps,dw-pcie-ep.yaml
shouldn't set 'unevaluatedProperties: false'. Otherwise, bindings that
reference them cannot add additional properties. With that addressed,
there's a handful of other undocumented properties to add.
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Greentime Hu <greentime.hu@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211206194426.2470080-1-robh@kernel.org
2021-12-06 19:44:25 +00:00
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additionalProperties: true
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required:
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- compatible
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- reg
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- reg-names
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examples:
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- |
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pcie@dfc00000 {
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compatible = "snps,dw-pcie";
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device_type = "pci";
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reg = <0xdfc00000 0x0001000>, /* IP registers */
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<0xd0000000 0x0002000>; /* Configuration space */
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
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<0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
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bus-range = <0x0 0xff>;
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interrupts = <25>, <24>;
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interrupt-names = "msi", "hp";
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#interrupt-cells = <1>;
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reset-gpios = <&port0 0 1>;
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phys = <&pcie_phy>;
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phy-names = "pcie";
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num-lanes = <1>;
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max-link-speed = <3>;
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};
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