2021-10-25 03:10:37 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Toshiba Visconti clock controller
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*
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* Copyright (c) 2021 TOSHIBA CORPORATION
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* Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#ifndef _VISCONTI_CLKC_H_
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#define _VISCONTI_CLKC_H_
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#include <linux/mfd/syscon.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include "reset.h"
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struct visconti_clk_provider {
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struct device *dev;
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struct regmap *regmap;
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struct clk_hw_onecell_data clk_data;
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};
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struct visconti_clk_gate_table {
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unsigned int id;
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const char *name;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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u8 flags;
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u32 ckon_offset;
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u32 ckoff_offset;
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u8 ck_idx;
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unsigned int div;
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u8 rs_id;
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};
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struct visconti_fixed_clk {
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unsigned int id;
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const char *name;
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const char *parent;
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unsigned long flag;
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unsigned int mult;
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unsigned int div;
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};
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struct visconti_clk_gate {
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struct clk_hw hw;
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struct regmap *regmap;
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u32 ckon_offset;
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u32 ckoff_offset;
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u8 ck_idx;
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u8 flags;
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u32 rson_offset;
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u32 rsoff_offset;
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u8 rs_idx;
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spinlock_t *lock;
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};
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struct visconti_clk_provider *visconti_init_clk(struct device *dev,
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struct regmap *regmap,
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unsigned long nr_clks);
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int visconti_clk_register_gates(struct visconti_clk_provider *data,
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const struct visconti_clk_gate_table *clks,
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int num_gate,
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const struct visconti_reset_data *reset,
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spinlock_t *lock);
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2022-03-16 08:35:33 +00:00
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#define NO_RESET 0xFF
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2021-10-25 03:10:37 +00:00
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#endif /* _VISCONTI_CLKC_H_ */
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