2019-05-28 17:10:04 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-09-11 21:17:20 +00:00
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/*
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* Copyright Intel Corporation (C) 2017.
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*
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* Based on the i2c-axxia.c driver.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#define ALTR_I2C_TFR_CMD 0x00 /* Transfer Command register */
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#define ALTR_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
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#define ALTR_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
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#define ALTR_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
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#define ALTR_I2C_RX_DATA 0x04 /* RX data FIFO register */
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#define ALTR_I2C_CTRL 0x08 /* Control register */
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#define ALTR_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */
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#define ALTR_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */
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#define ALTR_I2C_CTRL_BSPEED BIT(1) /* Bus Speed (1=Fast) */
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#define ALTR_I2C_CTRL_EN BIT(0) /* Enable Core (1=Enable) */
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#define ALTR_I2C_ISER 0x0C /* Interrupt Status Enable register */
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#define ALTR_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */
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#define ALTR_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */
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#define ALTR_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */
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#define ALTR_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */
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#define ALTR_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */
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#define ALTR_I2C_ISR 0x10 /* Interrupt Status register */
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#define ALTR_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW IRQ */
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#define ALTR_I2C_ISR_ARB BIT(3) /* ARB LOST IRQ */
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#define ALTR_I2C_ISR_NACK BIT(2) /* NACK DET IRQ */
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#define ALTR_I2C_ISR_RXRDY BIT(1) /* RX Ready IRQ */
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#define ALTR_I2C_ISR_TXRDY BIT(0) /* TX Ready IRQ */
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#define ALTR_I2C_STATUS 0x14 /* Status register */
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#define ALTR_I2C_STAT_CORE BIT(0) /* Core Status (0=idle) */
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#define ALTR_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */
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#define ALTR_I2C_RX_FIFO_LVL 0x1C /* Receive FIFO LVL register */
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#define ALTR_I2C_SCL_LOW 0x20 /* SCL low count register */
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#define ALTR_I2C_SCL_HIGH 0x24 /* SCL high count register */
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#define ALTR_I2C_SDA_HOLD 0x28 /* SDA hold count register */
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#define ALTR_I2C_ALL_IRQ (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
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ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
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ALTR_I2C_ISR_TXRDY)
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#define ALTR_I2C_THRESHOLD 0 /* IRQ Threshold at 1 element */
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#define ALTR_I2C_DFLT_FIFO_SZ 4
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#define ALTR_I2C_TIMEOUT 100000 /* 100ms */
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#define ALTR_I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
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/**
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2021-05-20 19:00:53 +00:00
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* struct altr_i2c_dev - I2C device context
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2017-09-11 21:17:20 +00:00
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* @base: pointer to register struct
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* @msg: pointer to current message
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* @msg_len: number of bytes transferred in msg
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* @msg_err: error code for completed message
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* @msg_complete: xfer completion object
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* @dev: device reference
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* @adapter: core i2c abstraction
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* @i2c_clk: clock reference for i2c input clock
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* @bus_clk_rate: current i2c bus clock rate
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* @buf: ptr to msg buffer for easier use.
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* @fifo_size: size of the FIFO passed in.
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* @isr_mask: cached copy of local ISR enables.
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* @isr_status: cached copy of local ISR status.
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2020-05-08 13:12:48 +00:00
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* @isr_mutex: mutex for IRQ thread.
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2017-09-11 21:17:20 +00:00
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*/
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struct altr_i2c_dev {
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void __iomem *base;
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struct i2c_msg *msg;
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size_t msg_len;
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int msg_err;
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struct completion msg_complete;
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struct device *dev;
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struct i2c_adapter adapter;
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struct clk *i2c_clk;
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u32 bus_clk_rate;
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u8 *buf;
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u32 fifo_size;
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u32 isr_mask;
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u32 isr_status;
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2020-05-08 13:12:48 +00:00
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struct mutex isr_mutex;
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2017-09-11 21:17:20 +00:00
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};
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static void
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altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
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{
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u32 int_en;
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int_en = readl(idev->base + ALTR_I2C_ISER);
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if (enable)
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idev->isr_mask = int_en | mask;
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else
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idev->isr_mask = int_en & ~mask;
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writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
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}
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static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
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{
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u32 int_en = readl(idev->base + ALTR_I2C_ISR);
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writel(int_en | mask, idev->base + ALTR_I2C_ISR);
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}
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static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
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{
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u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
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writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
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}
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static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
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{
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u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
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writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
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}
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static void altr_i2c_reset(struct altr_i2c_dev *idev)
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{
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altr_i2c_core_disable(idev);
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altr_i2c_core_enable(idev);
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}
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static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
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{
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writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
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}
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static void altr_i2c_init(struct altr_i2c_dev *idev)
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{
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u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
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u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
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u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
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(ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
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u32 t_high, t_low;
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2020-03-24 12:32:16 +00:00
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if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
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2017-09-11 21:17:20 +00:00
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tmp &= ~ALTR_I2C_CTRL_BSPEED;
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/* Standard mode SCL 50/50 */
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t_high = divisor * 1 / 2;
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t_low = divisor * 1 / 2;
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} else {
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tmp |= ALTR_I2C_CTRL_BSPEED;
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/* Fast mode SCL 33/66 */
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t_high = divisor * 1 / 3;
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t_low = divisor * 2 / 3;
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}
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writel(tmp, idev->base + ALTR_I2C_CTRL);
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dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
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idev->bus_clk_rate, clk_mhz, divisor);
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/* Reset controller */
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altr_i2c_reset(idev);
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/* SCL High Time */
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writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
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/* SCL Low Time */
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writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
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/* SDA Hold Time, 300ns */
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2020-02-11 14:47:04 +00:00
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writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD);
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2017-09-11 21:17:20 +00:00
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/* Mask all master interrupt bits */
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altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
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}
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2021-05-20 19:00:53 +00:00
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/*
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2017-09-11 21:17:20 +00:00
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* altr_i2c_transfer - On the last byte to be transmitted, send
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* a Stop bit on the last byte.
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*/
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static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
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{
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/* On the last byte to be transmitted, send STOP */
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if (idev->msg_len == 1)
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data |= ALTR_I2C_TFR_CMD_STO;
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if (idev->msg_len > 0)
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writel(data, idev->base + ALTR_I2C_TFR_CMD);
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}
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2021-05-20 19:00:53 +00:00
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/*
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2017-09-11 21:17:20 +00:00
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* altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
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* transfer. Send a Stop bit on the last byte.
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*/
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static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
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{
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size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
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int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
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while (bytes_to_transfer-- > 0) {
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*idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
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idev->msg_len--;
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altr_i2c_transfer(idev, 0);
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}
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}
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2021-05-20 19:00:53 +00:00
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/*
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2017-09-11 21:17:20 +00:00
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* altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
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*/
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static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
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{
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size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
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ALTR_I2C_TC_FIFO_LVL);
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int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
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int ret = idev->msg_len - bytes_to_transfer;
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while (bytes_to_transfer-- > 0) {
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altr_i2c_transfer(idev, *idev->buf++);
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idev->msg_len--;
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}
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return ret;
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}
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static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
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{
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struct altr_i2c_dev *idev = _dev;
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irqreturn_t ret = IRQ_HANDLED;
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/* Read IRQ status but only interested in Enabled IRQs. */
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idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
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if (idev->isr_status)
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ret = IRQ_WAKE_THREAD;
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return ret;
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}
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static irqreturn_t altr_i2c_isr(int irq, void *_dev)
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{
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int ret;
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bool read, finish = false;
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struct altr_i2c_dev *idev = _dev;
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u32 status = idev->isr_status;
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2020-05-08 13:12:48 +00:00
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mutex_lock(&idev->isr_mutex);
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2017-09-11 21:17:20 +00:00
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if (!idev->msg) {
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dev_warn(idev->dev, "unexpected interrupt\n");
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altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
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2020-05-08 13:12:48 +00:00
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goto out;
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2017-09-11 21:17:20 +00:00
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}
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read = (idev->msg->flags & I2C_M_RD) != 0;
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/* handle Lost Arbitration */
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if (unlikely(status & ALTR_I2C_ISR_ARB)) {
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altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
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idev->msg_err = -EAGAIN;
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finish = true;
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} else if (unlikely(status & ALTR_I2C_ISR_NACK)) {
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dev_dbg(idev->dev, "Could not get ACK\n");
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idev->msg_err = -ENXIO;
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altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK);
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altr_i2c_stop(idev);
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finish = true;
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} else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) {
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/* handle RX FIFO Overflow */
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altr_i2c_empty_rx_fifo(idev);
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altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
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altr_i2c_stop(idev);
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dev_err(idev->dev, "RX FIFO Overflow\n");
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finish = true;
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} else if (read && (status & ALTR_I2C_ISR_RXRDY)) {
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/* RX FIFO needs service? */
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altr_i2c_empty_rx_fifo(idev);
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altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
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if (!idev->msg_len)
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finish = true;
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} else if (!read && (status & ALTR_I2C_ISR_TXRDY)) {
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/* TX FIFO needs service? */
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altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY);
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if (idev->msg_len > 0)
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altr_i2c_fill_tx_fifo(idev);
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else
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finish = true;
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} else {
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dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status);
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altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
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}
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if (finish) {
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/* Wait for the Core to finish */
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ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS,
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status,
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!(status & ALTR_I2C_STAT_CORE),
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1, ALTR_I2C_TIMEOUT);
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if (ret)
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dev_err(idev->dev, "message timeout\n");
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altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
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altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
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complete(&idev->msg_complete);
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dev_dbg(idev->dev, "Message Complete\n");
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}
|
2020-05-08 13:12:48 +00:00
|
|
|
out:
|
|
|
|
mutex_unlock(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg)
|
|
|
|
{
|
|
|
|
u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK;
|
|
|
|
unsigned long time_left;
|
|
|
|
u32 value;
|
|
|
|
u8 addr = i2c_8bit_addr_from_msg(msg);
|
|
|
|
|
2020-05-08 13:12:48 +00:00
|
|
|
mutex_lock(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
idev->msg = msg;
|
|
|
|
idev->msg_len = msg->len;
|
|
|
|
idev->buf = msg->buf;
|
|
|
|
idev->msg_err = 0;
|
|
|
|
reinit_completion(&idev->msg_complete);
|
|
|
|
altr_i2c_core_enable(idev);
|
|
|
|
|
|
|
|
/* Make sure RX FIFO is empty */
|
|
|
|
do {
|
|
|
|
readl(idev->base + ALTR_I2C_RX_DATA);
|
|
|
|
} while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL));
|
|
|
|
|
|
|
|
writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
|
|
|
|
|
|
|
|
if ((msg->flags & I2C_M_RD) != 0) {
|
|
|
|
imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN;
|
|
|
|
altr_i2c_int_enable(idev, imask, true);
|
|
|
|
/* write the first byte to start the RX */
|
|
|
|
altr_i2c_transfer(idev, 0);
|
|
|
|
} else {
|
|
|
|
imask |= ALTR_I2C_ISR_TXRDY;
|
|
|
|
altr_i2c_int_enable(idev, imask, true);
|
|
|
|
altr_i2c_fill_tx_fifo(idev);
|
|
|
|
}
|
2020-05-08 13:12:48 +00:00
|
|
|
mutex_unlock(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
|
|
|
|
time_left = wait_for_completion_timeout(&idev->msg_complete,
|
|
|
|
ALTR_I2C_XFER_TIMEOUT);
|
2020-05-08 13:14:36 +00:00
|
|
|
mutex_lock(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
altr_i2c_int_enable(idev, imask, false);
|
|
|
|
|
|
|
|
value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
|
|
|
|
if (value)
|
|
|
|
dev_err(idev->dev, "Core Status not IDLE...\n");
|
|
|
|
|
|
|
|
if (time_left == 0) {
|
|
|
|
idev->msg_err = -ETIMEDOUT;
|
|
|
|
dev_dbg(idev->dev, "Transaction timed out.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
altr_i2c_core_disable(idev);
|
2020-05-08 13:14:36 +00:00
|
|
|
mutex_unlock(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
|
|
|
|
return idev->msg_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
|
|
{
|
|
|
|
struct altr_i2c_dev *idev = i2c_get_adapdata(adap);
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < num; i++) {
|
|
|
|
ret = altr_i2c_xfer_msg(idev, msgs++);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 altr_i2c_func(struct i2c_adapter *adap)
|
|
|
|
{
|
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_algorithm altr_i2c_algo = {
|
|
|
|
.master_xfer = altr_i2c_xfer,
|
|
|
|
.functionality = altr_i2c_func,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int altr_i2c_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct altr_i2c_dev *idev = NULL;
|
|
|
|
int irq, ret;
|
|
|
|
|
|
|
|
idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
|
|
|
|
if (!idev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2020-04-09 13:52:24 +00:00
|
|
|
idev->base = devm_platform_ioremap_resource(pdev, 0);
|
2017-09-11 21:17:20 +00:00
|
|
|
if (IS_ERR(idev->base))
|
|
|
|
return PTR_ERR(idev->base);
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2020-04-16 15:23:45 +00:00
|
|
|
if (irq < 0)
|
2017-09-11 21:17:20 +00:00
|
|
|
return irq;
|
|
|
|
|
|
|
|
idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(idev->i2c_clk)) {
|
|
|
|
dev_err(&pdev->dev, "missing clock\n");
|
|
|
|
return PTR_ERR(idev->i2c_clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
idev->dev = &pdev->dev;
|
|
|
|
init_completion(&idev->msg_complete);
|
2020-05-08 13:12:48 +00:00
|
|
|
mutex_init(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
|
2020-03-27 22:28:26 +00:00
|
|
|
ret = device_property_read_u32(idev->dev, "fifo-size",
|
2017-09-11 21:17:20 +00:00
|
|
|
&idev->fifo_size);
|
2020-03-27 22:28:26 +00:00
|
|
|
if (ret) {
|
2017-09-11 21:17:20 +00:00
|
|
|
dev_err(&pdev->dev, "FIFO size set to default of %d\n",
|
|
|
|
ALTR_I2C_DFLT_FIFO_SZ);
|
|
|
|
idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ;
|
|
|
|
}
|
|
|
|
|
2020-03-27 22:28:26 +00:00
|
|
|
ret = device_property_read_u32(idev->dev, "clock-frequency",
|
2017-09-11 21:17:20 +00:00
|
|
|
&idev->bus_clk_rate);
|
2020-03-27 22:28:26 +00:00
|
|
|
if (ret) {
|
2017-09-11 21:17:20 +00:00
|
|
|
dev_err(&pdev->dev, "Default to 100kHz\n");
|
2020-03-24 12:32:16 +00:00
|
|
|
idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
|
2017-09-11 21:17:20 +00:00
|
|
|
}
|
|
|
|
|
2020-03-24 12:32:16 +00:00
|
|
|
if (idev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) {
|
2017-09-11 21:17:20 +00:00
|
|
|
dev_err(&pdev->dev, "invalid clock-frequency %d\n",
|
|
|
|
idev->bus_clk_rate);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick,
|
|
|
|
altr_i2c_isr, IRQF_ONESHOT,
|
|
|
|
pdev->name, idev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(idev->i2c_clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to enable clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-05-08 13:14:36 +00:00
|
|
|
mutex_lock(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
altr_i2c_init(idev);
|
2020-05-08 13:14:36 +00:00
|
|
|
mutex_unlock(&idev->isr_mutex);
|
2017-09-11 21:17:20 +00:00
|
|
|
|
|
|
|
i2c_set_adapdata(&idev->adapter, idev);
|
|
|
|
strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
|
|
|
|
idev->adapter.owner = THIS_MODULE;
|
|
|
|
idev->adapter.algo = &altr_i2c_algo;
|
|
|
|
idev->adapter.dev.parent = &pdev->dev;
|
|
|
|
idev->adapter.dev.of_node = pdev->dev.of_node;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, idev);
|
|
|
|
|
|
|
|
ret = i2c_add_adapter(&idev->adapter);
|
|
|
|
if (ret) {
|
|
|
|
clk_disable_unprepare(idev->i2c_clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int altr_i2c_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct altr_i2c_dev *idev = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
clk_disable_unprepare(idev->i2c_clk);
|
|
|
|
i2c_del_adapter(&idev->adapter);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Match table for of_platform binding */
|
|
|
|
static const struct of_device_id altr_i2c_of_match[] = {
|
|
|
|
{ .compatible = "altr,softip-i2c-v1.0" },
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, altr_i2c_of_match);
|
|
|
|
|
|
|
|
static struct platform_driver altr_i2c_driver = {
|
|
|
|
.probe = altr_i2c_probe,
|
|
|
|
.remove = altr_i2c_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "altera-i2c",
|
|
|
|
.of_match_table = altr_i2c_of_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(altr_i2c_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Altera Soft IP I2C bus driver");
|
|
|
|
MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|