2019-05-27 06:55:21 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-05-21 08:53:28 +00:00
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Xudong Chen <xudong.chen@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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2021-10-10 07:05:12 +00:00
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#include <linux/iopoll.h>
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2015-05-21 08:53:28 +00:00
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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2018-04-16 02:32:52 +00:00
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#include <linux/of_device.h>
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2015-05-21 08:53:28 +00:00
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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2015-05-21 08:53:30 +00:00
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#define I2C_RS_TRANSFER (1 << 4)
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2019-04-02 12:35:57 +00:00
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#define I2C_ARB_LOST (1 << 3)
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2015-05-21 08:53:28 +00:00
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#define I2C_HS_NACKERR (1 << 2)
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#define I2C_ACKERR (1 << 1)
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#define I2C_TRANSAC_COMP (1 << 0)
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#define I2C_TRANSAC_START (1 << 0)
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2015-05-21 08:53:30 +00:00
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#define I2C_RS_MUL_CNFG (1 << 15)
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#define I2C_RS_MUL_TRIG (1 << 14)
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2015-05-21 08:53:28 +00:00
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#define I2C_DCM_DISABLE 0x0000
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#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
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#define I2C_IO_CONFIG_PUSH_PULL 0x0000
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#define I2C_SOFT_RST 0x0001
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2020-12-24 12:26:07 +00:00
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#define I2C_HANDSHAKE_RST 0x0020
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2015-05-21 08:53:28 +00:00
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#define I2C_FIFO_ADDR_CLR 0x0001
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#define I2C_DELAY_LEN 0x0002
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2021-09-17 10:14:14 +00:00
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#define I2C_ST_START_CON 0x8001
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#define I2C_FS_START_CON 0x1800
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2015-05-21 08:53:28 +00:00
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#define I2C_TIME_CLR_VALUE 0x0000
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#define I2C_TIME_DEFAULT_VALUE 0x0003
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#define I2C_WRRD_TRANAC_VALUE 0x0002
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#define I2C_RD_TRANAC_VALUE 0x0001
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2020-05-14 13:09:05 +00:00
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#define I2C_SCL_MIS_COMP_VALUE 0x0000
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2020-12-24 12:26:07 +00:00
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#define I2C_CHN_CLR_FLAG 0x0000
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2021-10-10 07:05:12 +00:00
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#define I2C_RELIABILITY 0x0010
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#define I2C_DMAACK_ENABLE 0x0008
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2015-05-21 08:53:28 +00:00
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#define I2C_DMA_CON_TX 0x0000
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#define I2C_DMA_CON_RX 0x0001
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2020-08-05 10:52:19 +00:00
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#define I2C_DMA_ASYNC_MODE 0x0004
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#define I2C_DMA_SKIP_CONFIG 0x0010
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#define I2C_DMA_DIR_CHANGE 0x0200
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2015-05-21 08:53:28 +00:00
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#define I2C_DMA_START_EN 0x0001
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#define I2C_DMA_INT_FLAG_NONE 0x0000
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#define I2C_DMA_CLR_FLAG 0x0000
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2020-12-24 12:26:07 +00:00
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#define I2C_DMA_WARM_RST 0x0001
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2015-08-06 07:22:10 +00:00
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#define I2C_DMA_HARD_RST 0x0002
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2020-12-24 12:26:07 +00:00
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#define I2C_DMA_HANDSHAKE_RST 0x0004
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2015-05-21 08:53:28 +00:00
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#define MAX_SAMPLE_CNT_DIV 8
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#define MAX_STEP_CNT_DIV 64
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2022-02-17 12:22:43 +00:00
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#define MAX_CLOCK_DIV_8BITS 256
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#define MAX_CLOCK_DIV_5BITS 32
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2015-05-21 08:53:28 +00:00
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#define MAX_HS_STEP_CNT_DIV 8
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2022-02-17 12:22:43 +00:00
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#define I2C_STANDARD_MODE_BUFFER (1000 / 3)
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#define I2C_FAST_MODE_BUFFER (300 / 3)
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#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3)
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2015-05-21 08:53:28 +00:00
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#define I2C_CONTROL_RS (0x1 << 1)
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#define I2C_CONTROL_DMA_EN (0x1 << 2)
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#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
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#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
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#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
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#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
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2019-04-02 12:35:58 +00:00
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#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
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#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
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2015-05-21 08:53:28 +00:00
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#define I2C_CONTROL_WRAPPER (0x1 << 0)
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#define I2C_DRV_NAME "i2c-mt65xx"
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2022-03-03 09:15:47 +00:00
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/**
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* enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
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*
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* @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
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* @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
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* @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
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* @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
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* @I2C_MT65XX_CLK_MAX: Number of supported clocks
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*/
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enum i2c_mt65xx_clks {
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I2C_MT65XX_CLK_MAIN = 0,
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I2C_MT65XX_CLK_DMA,
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I2C_MT65XX_CLK_PMIC,
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I2C_MT65XX_CLK_ARB,
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I2C_MT65XX_CLK_MAX
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};
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static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
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"main", "dma", "pmic", "arb"
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};
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2015-05-21 08:53:28 +00:00
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enum DMA_REGS_OFFSET {
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OFFSET_INT_FLAG = 0x0,
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OFFSET_INT_EN = 0x04,
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OFFSET_EN = 0x08,
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2015-08-06 07:22:10 +00:00
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OFFSET_RST = 0x0c,
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2015-05-21 08:53:28 +00:00
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OFFSET_CON = 0x18,
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OFFSET_TX_MEM_ADDR = 0x1c,
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OFFSET_RX_MEM_ADDR = 0x20,
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OFFSET_TX_LEN = 0x24,
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OFFSET_RX_LEN = 0x28,
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2016-02-01 17:19:03 +00:00
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OFFSET_TX_4G_MODE = 0x54,
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OFFSET_RX_4G_MODE = 0x58,
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2015-05-21 08:53:28 +00:00
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};
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enum i2c_trans_st_rs {
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I2C_TRANS_STOP = 0,
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I2C_TRANS_REPEATED_START,
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};
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enum mtk_trans_op {
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I2C_MASTER_WR = 1,
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I2C_MASTER_RD,
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I2C_MASTER_WRRD,
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};
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enum I2C_REGS_OFFSET {
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2019-04-02 12:35:55 +00:00
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OFFSET_DATA_PORT,
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OFFSET_SLAVE_ADDR,
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OFFSET_INTR_MASK,
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OFFSET_INTR_STAT,
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OFFSET_CONTROL,
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OFFSET_TRANSFER_LEN,
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OFFSET_TRANSAC_LEN,
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OFFSET_DELAY_LEN,
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OFFSET_TIMING,
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OFFSET_START,
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OFFSET_EXT_CONF,
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OFFSET_FIFO_STAT,
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OFFSET_FIFO_THRESH,
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OFFSET_FIFO_ADDR_CLR,
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OFFSET_IO_CONFIG,
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OFFSET_RSV_DEBUG,
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OFFSET_HS,
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OFFSET_SOFTRESET,
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OFFSET_DCM_EN,
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2021-10-10 07:05:13 +00:00
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OFFSET_MULTI_DMA,
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2019-04-02 12:35:55 +00:00
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OFFSET_PATH_DIR,
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OFFSET_DEBUGSTAT,
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OFFSET_DEBUGCTRL,
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OFFSET_TRANSFER_LEN_AUX,
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OFFSET_CLOCK_DIV,
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2019-04-02 12:35:59 +00:00
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OFFSET_LTIMING,
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2020-05-14 13:09:05 +00:00
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OFFSET_SCL_HIGH_LOW_RATIO,
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OFFSET_HS_SCL_HIGH_LOW_RATIO,
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OFFSET_SCL_MIS_COMP_POINT,
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OFFSET_STA_STO_AC_TIMING,
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OFFSET_HS_STA_STO_AC_TIMING,
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OFFSET_SDA_TIMING,
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2019-04-02 12:35:55 +00:00
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};
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static const u16 mt_i2c_regs_v1[] = {
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[OFFSET_DATA_PORT] = 0x0,
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[OFFSET_SLAVE_ADDR] = 0x4,
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[OFFSET_INTR_MASK] = 0x8,
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[OFFSET_INTR_STAT] = 0xc,
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[OFFSET_CONTROL] = 0x10,
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[OFFSET_TRANSFER_LEN] = 0x14,
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[OFFSET_TRANSAC_LEN] = 0x18,
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[OFFSET_DELAY_LEN] = 0x1c,
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[OFFSET_TIMING] = 0x20,
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[OFFSET_START] = 0x24,
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[OFFSET_EXT_CONF] = 0x28,
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[OFFSET_FIFO_STAT] = 0x30,
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[OFFSET_FIFO_THRESH] = 0x34,
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[OFFSET_FIFO_ADDR_CLR] = 0x38,
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[OFFSET_IO_CONFIG] = 0x40,
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[OFFSET_RSV_DEBUG] = 0x44,
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[OFFSET_HS] = 0x48,
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[OFFSET_SOFTRESET] = 0x50,
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[OFFSET_DCM_EN] = 0x54,
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[OFFSET_PATH_DIR] = 0x60,
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[OFFSET_DEBUGSTAT] = 0x64,
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[OFFSET_DEBUGCTRL] = 0x68,
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[OFFSET_TRANSFER_LEN_AUX] = 0x6c,
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[OFFSET_CLOCK_DIV] = 0x70,
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2020-05-14 13:09:05 +00:00
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[OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
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[OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
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[OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
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[OFFSET_STA_STO_AC_TIMING] = 0x80,
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[OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
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[OFFSET_SDA_TIMING] = 0x88,
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2015-05-21 08:53:28 +00:00
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};
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2019-04-02 12:35:59 +00:00
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static const u16 mt_i2c_regs_v2[] = {
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[OFFSET_DATA_PORT] = 0x0,
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[OFFSET_SLAVE_ADDR] = 0x4,
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[OFFSET_INTR_MASK] = 0x8,
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[OFFSET_INTR_STAT] = 0xc,
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[OFFSET_CONTROL] = 0x10,
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[OFFSET_TRANSFER_LEN] = 0x14,
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[OFFSET_TRANSAC_LEN] = 0x18,
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[OFFSET_DELAY_LEN] = 0x1c,
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[OFFSET_TIMING] = 0x20,
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[OFFSET_START] = 0x24,
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[OFFSET_EXT_CONF] = 0x28,
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[OFFSET_LTIMING] = 0x2c,
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[OFFSET_HS] = 0x30,
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[OFFSET_IO_CONFIG] = 0x34,
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[OFFSET_FIFO_ADDR_CLR] = 0x38,
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2020-05-14 13:09:05 +00:00
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[OFFSET_SDA_TIMING] = 0x3c,
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2019-04-02 12:35:59 +00:00
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[OFFSET_TRANSFER_LEN_AUX] = 0x44,
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[OFFSET_CLOCK_DIV] = 0x48,
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[OFFSET_SOFTRESET] = 0x50,
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2021-10-10 07:05:13 +00:00
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[OFFSET_MULTI_DMA] = 0x8c,
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2020-05-14 13:09:05 +00:00
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[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
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2021-09-17 10:14:10 +00:00
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[OFFSET_DEBUGSTAT] = 0xe4,
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2019-04-02 12:35:59 +00:00
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[OFFSET_DEBUGCTRL] = 0xe8,
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[OFFSET_FIFO_STAT] = 0xf4,
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[OFFSET_FIFO_THRESH] = 0xf8,
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[OFFSET_DCM_EN] = 0xf88,
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};
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2015-05-21 08:53:28 +00:00
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struct mtk_i2c_compatible {
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const struct i2c_adapter_quirks *quirks;
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2019-04-02 12:35:55 +00:00
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const u16 *regs;
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2015-05-21 08:53:28 +00:00
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unsigned char pmic_i2c: 1;
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unsigned char dcm: 1;
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2015-05-21 08:53:30 +00:00
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unsigned char auto_restart: 1;
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2015-11-09 05:43:58 +00:00
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unsigned char aux_len_reg: 1;
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2017-12-19 06:51:02 +00:00
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unsigned char timing_adjust: 1;
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2019-04-02 12:35:58 +00:00
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unsigned char dma_sync: 1;
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2019-04-02 12:35:59 +00:00
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unsigned char ltiming_adjust: 1;
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2020-08-05 10:52:19 +00:00
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unsigned char apdma_sync: 1;
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2020-08-05 10:52:20 +00:00
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unsigned char max_dma_support;
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2015-05-21 08:53:28 +00:00
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};
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2020-05-14 13:09:05 +00:00
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struct mtk_i2c_ac_timing {
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u16 htiming;
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u16 ltiming;
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u16 hs;
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u16 ext;
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u16 inter_clk_div;
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u16 scl_hl_ratio;
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u16 hs_scl_hl_ratio;
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u16 sta_stop;
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u16 hs_sta_stop;
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u16 sda_timing;
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};
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2015-05-21 08:53:28 +00:00
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struct mtk_i2c {
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struct i2c_adapter adap; /* i2c host adapter */
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struct device *dev;
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struct completion msg_complete;
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2021-04-17 06:46:52 +00:00
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struct i2c_timings timing_info;
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2015-05-21 08:53:28 +00:00
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/* set in i2c probe */
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void __iomem *base; /* i2c base addr */
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void __iomem *pdmabase; /* dma base address*/
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2022-03-03 09:15:47 +00:00
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struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
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2015-05-21 08:53:28 +00:00
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bool have_pmic; /* can use i2c pins from PMIC */
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bool use_push_pull; /* IO config push-pull mode */
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u16 irq_stat; /* interrupt status */
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2017-07-17 11:02:10 +00:00
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unsigned int clk_src_div;
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2015-05-21 08:53:28 +00:00
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unsigned int speed_hz; /* The speed in transfer */
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enum mtk_trans_op op;
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u16 timing_reg;
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u16 high_speed_reg;
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2019-04-02 12:35:59 +00:00
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u16 ltiming_reg;
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2015-11-09 05:43:58 +00:00
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unsigned char auto_restart;
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2015-12-15 07:22:26 +00:00
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bool ignore_restart_irq;
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2020-05-14 13:09:05 +00:00
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struct mtk_i2c_ac_timing ac_timing;
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2015-05-21 08:53:28 +00:00
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const struct mtk_i2c_compatible *dev_comp;
|
|
|
|
};
|
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
/**
|
|
|
|
* struct i2c_spec_values:
|
2020-08-07 13:19:04 +00:00
|
|
|
* @min_low_ns: min LOW period of the SCL clock
|
|
|
|
* @min_su_sta_ns: min set-up time for a repeated START condition
|
|
|
|
* @max_hd_dat_ns: max data hold time
|
|
|
|
* @min_su_dat_ns: min data set-up time
|
2020-05-14 13:09:05 +00:00
|
|
|
*/
|
|
|
|
struct i2c_spec_values {
|
|
|
|
unsigned int min_low_ns;
|
|
|
|
unsigned int min_su_sta_ns;
|
|
|
|
unsigned int max_hd_dat_ns;
|
|
|
|
unsigned int min_su_dat_ns;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i2c_spec_values standard_mode_spec = {
|
|
|
|
.min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
|
|
|
|
.min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
|
|
|
|
.max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
|
|
|
|
.min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i2c_spec_values fast_mode_spec = {
|
|
|
|
.min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
|
|
|
|
.min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
|
|
|
|
.max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
|
|
|
|
.min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i2c_spec_values fast_mode_plus_spec = {
|
|
|
|
.min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
|
|
|
|
.min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
|
|
|
|
.max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
|
|
|
|
.min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
|
|
|
|
};
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
|
|
|
|
.flags = I2C_AQ_COMB_WRITE_THEN_READ,
|
|
|
|
.max_num_msgs = 1,
|
|
|
|
.max_write_len = 255,
|
|
|
|
.max_read_len = 255,
|
|
|
|
.max_comb_1st_msg_len = 255,
|
|
|
|
.max_comb_2nd_msg_len = 31,
|
|
|
|
};
|
|
|
|
|
2017-08-21 03:36:54 +00:00
|
|
|
static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
|
|
|
|
.max_num_msgs = 255,
|
|
|
|
};
|
|
|
|
|
2019-08-22 09:45:17 +00:00
|
|
|
static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
|
|
|
|
.flags = I2C_AQ_NO_ZERO_LEN,
|
|
|
|
};
|
|
|
|
|
2017-12-19 06:51:02 +00:00
|
|
|
static const struct mtk_i2c_compatible mt2712_compat = {
|
2019-04-02 12:35:55 +00:00
|
|
|
.regs = mt_i2c_regs_v1,
|
2017-12-19 06:51:02 +00:00
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 1,
|
|
|
|
.auto_restart = 1,
|
|
|
|
.aux_len_reg = 1,
|
|
|
|
.timing_adjust = 1,
|
2019-04-02 12:35:58 +00:00
|
|
|
.dma_sync = 0,
|
2019-04-02 12:35:59 +00:00
|
|
|
.ltiming_adjust = 0,
|
2020-08-05 10:52:19 +00:00
|
|
|
.apdma_sync = 0,
|
2020-08-05 10:52:20 +00:00
|
|
|
.max_dma_support = 33,
|
2017-12-19 06:51:02 +00:00
|
|
|
};
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
static const struct mtk_i2c_compatible mt6577_compat = {
|
|
|
|
.quirks = &mt6577_i2c_quirks,
|
2019-04-02 12:35:55 +00:00
|
|
|
.regs = mt_i2c_regs_v1,
|
2015-05-21 08:53:28 +00:00
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 1,
|
2015-05-21 08:53:30 +00:00
|
|
|
.auto_restart = 0,
|
2015-11-09 05:43:58 +00:00
|
|
|
.aux_len_reg = 0,
|
2017-12-19 06:51:02 +00:00
|
|
|
.timing_adjust = 0,
|
2019-04-02 12:35:58 +00:00
|
|
|
.dma_sync = 0,
|
2019-04-02 12:35:59 +00:00
|
|
|
.ltiming_adjust = 0,
|
2020-08-05 10:52:19 +00:00
|
|
|
.apdma_sync = 0,
|
2020-08-05 10:52:20 +00:00
|
|
|
.max_dma_support = 32,
|
2015-05-21 08:53:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct mtk_i2c_compatible mt6589_compat = {
|
|
|
|
.quirks = &mt6577_i2c_quirks,
|
2019-04-02 12:35:55 +00:00
|
|
|
.regs = mt_i2c_regs_v1,
|
2015-05-21 08:53:28 +00:00
|
|
|
.pmic_i2c = 1,
|
|
|
|
.dcm = 0,
|
2015-05-21 08:53:30 +00:00
|
|
|
.auto_restart = 0,
|
2015-11-09 05:43:58 +00:00
|
|
|
.aux_len_reg = 0,
|
2017-12-19 06:51:02 +00:00
|
|
|
.timing_adjust = 0,
|
2019-04-02 12:35:58 +00:00
|
|
|
.dma_sync = 0,
|
2019-04-02 12:35:59 +00:00
|
|
|
.ltiming_adjust = 0,
|
2020-08-05 10:52:19 +00:00
|
|
|
.apdma_sync = 0,
|
2020-08-05 10:52:20 +00:00
|
|
|
.max_dma_support = 32,
|
2015-05-21 08:53:30 +00:00
|
|
|
};
|
|
|
|
|
2017-08-21 03:36:54 +00:00
|
|
|
static const struct mtk_i2c_compatible mt7622_compat = {
|
|
|
|
.quirks = &mt7622_i2c_quirks,
|
2019-04-02 12:35:55 +00:00
|
|
|
.regs = mt_i2c_regs_v1,
|
2017-08-21 03:36:54 +00:00
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 1,
|
|
|
|
.auto_restart = 1,
|
|
|
|
.aux_len_reg = 1,
|
2017-12-19 06:51:02 +00:00
|
|
|
.timing_adjust = 0,
|
2019-04-02 12:35:58 +00:00
|
|
|
.dma_sync = 0,
|
2019-04-02 12:35:59 +00:00
|
|
|
.ltiming_adjust = 0,
|
2020-08-05 10:52:19 +00:00
|
|
|
.apdma_sync = 0,
|
2020-08-05 10:52:20 +00:00
|
|
|
.max_dma_support = 32,
|
2017-08-21 03:36:54 +00:00
|
|
|
};
|
|
|
|
|
2022-03-07 03:36:49 +00:00
|
|
|
static const struct mtk_i2c_compatible mt8168_compat = {
|
|
|
|
.regs = mt_i2c_regs_v1,
|
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 1,
|
|
|
|
.auto_restart = 1,
|
|
|
|
.aux_len_reg = 1,
|
|
|
|
.timing_adjust = 1,
|
|
|
|
.dma_sync = 1,
|
|
|
|
.ltiming_adjust = 0,
|
|
|
|
.apdma_sync = 0,
|
|
|
|
.max_dma_support = 33,
|
|
|
|
};
|
|
|
|
|
2015-05-21 08:53:30 +00:00
|
|
|
static const struct mtk_i2c_compatible mt8173_compat = {
|
2019-04-02 12:35:55 +00:00
|
|
|
.regs = mt_i2c_regs_v1,
|
2015-05-21 08:53:30 +00:00
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 1,
|
|
|
|
.auto_restart = 1,
|
2015-11-09 05:43:58 +00:00
|
|
|
.aux_len_reg = 1,
|
2017-12-19 06:51:02 +00:00
|
|
|
.timing_adjust = 0,
|
2019-04-02 12:35:58 +00:00
|
|
|
.dma_sync = 0,
|
2019-04-02 12:35:59 +00:00
|
|
|
.ltiming_adjust = 0,
|
2020-08-05 10:52:19 +00:00
|
|
|
.apdma_sync = 0,
|
2020-08-05 10:52:20 +00:00
|
|
|
.max_dma_support = 33,
|
2019-04-02 12:35:59 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct mtk_i2c_compatible mt8183_compat = {
|
2019-08-22 09:45:17 +00:00
|
|
|
.quirks = &mt8183_i2c_quirks,
|
2019-04-02 12:35:59 +00:00
|
|
|
.regs = mt_i2c_regs_v2,
|
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 0,
|
|
|
|
.auto_restart = 1,
|
|
|
|
.aux_len_reg = 1,
|
|
|
|
.timing_adjust = 1,
|
|
|
|
.dma_sync = 1,
|
|
|
|
.ltiming_adjust = 1,
|
2020-08-05 10:52:19 +00:00
|
|
|
.apdma_sync = 0,
|
2020-08-05 10:52:20 +00:00
|
|
|
.max_dma_support = 33,
|
2015-05-21 08:53:28 +00:00
|
|
|
};
|
|
|
|
|
2022-01-25 11:04:13 +00:00
|
|
|
static const struct mtk_i2c_compatible mt8186_compat = {
|
|
|
|
.regs = mt_i2c_regs_v2,
|
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 0,
|
|
|
|
.auto_restart = 1,
|
|
|
|
.aux_len_reg = 1,
|
|
|
|
.timing_adjust = 1,
|
|
|
|
.dma_sync = 0,
|
|
|
|
.ltiming_adjust = 1,
|
|
|
|
.apdma_sync = 0,
|
|
|
|
.max_dma_support = 36,
|
|
|
|
};
|
|
|
|
|
2020-08-05 10:52:22 +00:00
|
|
|
static const struct mtk_i2c_compatible mt8192_compat = {
|
|
|
|
.quirks = &mt8183_i2c_quirks,
|
|
|
|
.regs = mt_i2c_regs_v2,
|
|
|
|
.pmic_i2c = 0,
|
|
|
|
.dcm = 0,
|
|
|
|
.auto_restart = 1,
|
|
|
|
.aux_len_reg = 1,
|
|
|
|
.timing_adjust = 1,
|
|
|
|
.dma_sync = 1,
|
|
|
|
.ltiming_adjust = 1,
|
|
|
|
.apdma_sync = 1,
|
|
|
|
.max_dma_support = 36,
|
|
|
|
};
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
static const struct of_device_id mtk_i2c_of_match[] = {
|
2017-12-19 06:51:02 +00:00
|
|
|
{ .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
|
2015-05-21 08:53:28 +00:00
|
|
|
{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
|
|
|
|
{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
|
2017-08-21 03:36:54 +00:00
|
|
|
{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
|
2022-03-07 03:36:49 +00:00
|
|
|
{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
|
2015-05-21 08:53:30 +00:00
|
|
|
{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
|
2019-04-02 12:35:59 +00:00
|
|
|
{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
|
2022-01-25 11:04:13 +00:00
|
|
|
{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
|
2020-08-05 10:52:22 +00:00
|
|
|
{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
|
2015-05-21 08:53:28 +00:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
|
|
|
|
|
2019-04-02 12:35:55 +00:00
|
|
|
static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
|
|
|
|
{
|
|
|
|
return readw(i2c->base + i2c->dev_comp->regs[reg]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
|
|
|
|
enum I2C_REGS_OFFSET reg)
|
|
|
|
{
|
|
|
|
writew(val, i2c->base + i2c->dev_comp->regs[reg]);
|
|
|
|
}
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
|
|
|
|
{
|
|
|
|
u16 control_reg;
|
2021-05-27 12:04:04 +00:00
|
|
|
u16 intr_stat_reg;
|
2021-09-17 10:14:14 +00:00
|
|
|
u16 ext_conf_val;
|
2021-05-27 12:04:04 +00:00
|
|
|
|
|
|
|
mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
|
|
|
|
intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
|
|
|
|
mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2021-04-17 06:46:51 +00:00
|
|
|
if (i2c->dev_comp->apdma_sync) {
|
2020-12-24 12:26:07 +00:00
|
|
|
writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
|
|
|
|
udelay(10);
|
|
|
|
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
|
|
|
|
udelay(10);
|
|
|
|
writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
|
|
|
|
i2c->pdmabase + OFFSET_RST);
|
|
|
|
mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
|
|
|
|
OFFSET_SOFTRESET);
|
|
|
|
udelay(10);
|
|
|
|
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
|
|
|
|
mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
|
|
|
|
} else {
|
|
|
|
writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
|
|
|
|
udelay(50);
|
|
|
|
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
|
|
|
|
mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
|
|
|
|
}
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
/* Set ioconfig */
|
|
|
|
if (i2c->use_push_pull)
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
|
2015-05-21 08:53:28 +00:00
|
|
|
else
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
if (i2c->dev_comp->dcm)
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
|
|
|
|
mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
|
2019-04-02 12:35:59 +00:00
|
|
|
if (i2c->dev_comp->ltiming_adjust)
|
|
|
|
mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2021-09-17 10:14:14 +00:00
|
|
|
if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
|
|
|
|
ext_conf_val = I2C_ST_START_CON;
|
|
|
|
else
|
|
|
|
ext_conf_val = I2C_FS_START_CON;
|
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
if (i2c->dev_comp->timing_adjust) {
|
2021-09-17 10:14:14 +00:00
|
|
|
ext_conf_val = i2c->ac_timing.ext;
|
2020-05-14 13:09:05 +00:00
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
|
|
|
|
OFFSET_CLOCK_DIV);
|
|
|
|
mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
|
|
|
|
OFFSET_SCL_MIS_COMP_POINT);
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
|
|
|
|
OFFSET_SDA_TIMING);
|
|
|
|
|
|
|
|
if (i2c->dev_comp->ltiming_adjust) {
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
|
|
|
|
OFFSET_TIMING);
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
|
|
|
|
OFFSET_LTIMING);
|
|
|
|
} else {
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
|
|
|
|
OFFSET_SCL_HIGH_LOW_RATIO);
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
|
|
|
|
OFFSET_HS_SCL_HIGH_LOW_RATIO);
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
|
|
|
|
OFFSET_STA_STO_AC_TIMING);
|
|
|
|
mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
|
|
|
|
OFFSET_HS_STA_STO_AC_TIMING);
|
|
|
|
}
|
|
|
|
}
|
2021-09-17 10:14:14 +00:00
|
|
|
mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
|
2020-05-14 13:09:05 +00:00
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
|
|
|
|
if (i2c->have_pmic)
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
control_reg = I2C_CONTROL_ACKERR_DET_EN |
|
|
|
|
I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
|
2019-04-02 12:35:58 +00:00
|
|
|
if (i2c->dev_comp->dma_sync)
|
|
|
|
control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
|
|
|
|
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
|
|
|
|
mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
|
|
|
|
{
|
|
|
|
if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
|
|
|
|
return &standard_mode_spec;
|
|
|
|
else if (speed <= I2C_MAX_FAST_MODE_FREQ)
|
|
|
|
return &fast_mode_spec;
|
|
|
|
else
|
|
|
|
return &fast_mode_plus_spec;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_i2c_max_step_cnt(unsigned int target_speed)
|
|
|
|
{
|
2021-04-17 06:46:50 +00:00
|
|
|
if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
|
2020-05-14 13:09:05 +00:00
|
|
|
return MAX_HS_STEP_CNT_DIV;
|
|
|
|
else
|
|
|
|
return MAX_STEP_CNT_DIV;
|
|
|
|
}
|
|
|
|
|
2022-02-17 12:22:43 +00:00
|
|
|
static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
|
|
|
|
unsigned int sample_cnt)
|
|
|
|
{
|
|
|
|
int clk_div_restri = 0;
|
|
|
|
|
|
|
|
if (i2c->dev_comp->ltiming_adjust == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (sample_cnt == 1) {
|
|
|
|
if (i2c->ac_timing.inter_clk_div == 0)
|
|
|
|
clk_div_restri = 0;
|
|
|
|
else
|
|
|
|
clk_div_restri = 1;
|
|
|
|
} else {
|
|
|
|
if (i2c->ac_timing.inter_clk_div == 0)
|
|
|
|
clk_div_restri = -1;
|
|
|
|
else if (i2c->ac_timing.inter_clk_div == 1)
|
|
|
|
clk_div_restri = 0;
|
|
|
|
else
|
|
|
|
clk_div_restri = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return clk_div_restri;
|
|
|
|
}
|
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
/*
|
|
|
|
* Check and Calculate i2c ac-timing
|
|
|
|
*
|
|
|
|
* Hardware design:
|
|
|
|
* sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
|
|
|
|
* xxx_cnt_div = spec->min_xxx_ns / sample_ns
|
|
|
|
*
|
|
|
|
* Sample_ns is rounded down for xxx_cnt_div would be greater
|
|
|
|
* than the smallest spec.
|
|
|
|
* The sda_timing is chosen as the middle value between
|
|
|
|
* the largest and smallest.
|
|
|
|
*/
|
|
|
|
static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
|
|
|
|
unsigned int clk_src,
|
|
|
|
unsigned int check_speed,
|
|
|
|
unsigned int step_cnt,
|
|
|
|
unsigned int sample_cnt)
|
|
|
|
{
|
|
|
|
const struct i2c_spec_values *spec;
|
|
|
|
unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
|
|
|
|
unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
|
|
|
|
unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
|
|
|
|
clk_src);
|
|
|
|
|
|
|
|
if (!i2c->dev_comp->timing_adjust)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (i2c->dev_comp->ltiming_adjust)
|
|
|
|
max_sta_cnt = 0x100;
|
|
|
|
|
|
|
|
spec = mtk_i2c_get_spec(check_speed);
|
|
|
|
|
|
|
|
if (i2c->dev_comp->ltiming_adjust)
|
|
|
|
clk_ns = 1000000000 / clk_src;
|
|
|
|
else
|
|
|
|
clk_ns = sample_ns / 2;
|
|
|
|
|
2021-04-17 06:46:52 +00:00
|
|
|
su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns +
|
|
|
|
i2c->timing_info.scl_int_delay_ns, clk_ns);
|
2020-05-14 13:09:05 +00:00
|
|
|
if (su_sta_cnt > max_sta_cnt)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
|
|
|
|
max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
|
|
|
|
if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
|
|
|
|
if (low_cnt > step_cnt) {
|
|
|
|
high_cnt = 2 * step_cnt - low_cnt;
|
|
|
|
} else {
|
|
|
|
high_cnt = step_cnt;
|
|
|
|
low_cnt = step_cnt;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
return -2;
|
|
|
|
}
|
|
|
|
|
|
|
|
sda_max = spec->max_hd_dat_ns / sample_ns;
|
|
|
|
if (sda_max > low_cnt)
|
|
|
|
sda_max = 0;
|
|
|
|
|
|
|
|
sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
|
|
|
|
if (sda_min < low_cnt)
|
|
|
|
sda_min = 0;
|
|
|
|
|
|
|
|
if (sda_min > sda_max)
|
|
|
|
return -3;
|
|
|
|
|
2021-04-17 06:46:50 +00:00
|
|
|
if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
|
2020-05-14 13:09:05 +00:00
|
|
|
if (i2c->dev_comp->ltiming_adjust) {
|
|
|
|
i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
|
|
|
|
(sample_cnt << 12) | (high_cnt << 8);
|
|
|
|
i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
|
|
|
|
i2c->ac_timing.ltiming |= (sample_cnt << 12) |
|
|
|
|
(low_cnt << 9);
|
|
|
|
i2c->ac_timing.ext &= ~GENMASK(7, 1);
|
|
|
|
i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
|
|
|
|
} else {
|
|
|
|
i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
|
|
|
|
(high_cnt << 6) | low_cnt;
|
|
|
|
i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
|
|
|
|
su_sta_cnt;
|
|
|
|
}
|
|
|
|
i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
|
|
|
|
i2c->ac_timing.sda_timing |= (1 << 12) |
|
|
|
|
((sda_max + sda_min) / 2) << 6;
|
|
|
|
} else {
|
|
|
|
if (i2c->dev_comp->ltiming_adjust) {
|
|
|
|
i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
|
|
|
|
i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
|
|
|
|
i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
|
|
|
|
} else {
|
|
|
|
i2c->ac_timing.scl_hl_ratio = (1 << 12) |
|
|
|
|
(high_cnt << 6) | low_cnt;
|
|
|
|
i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
|
|
|
|
su_sta_cnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c->ac_timing.sda_timing = (1 << 12) |
|
|
|
|
(sda_max + sda_min) / 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
/*
|
|
|
|
* Calculate i2c port speed
|
|
|
|
*
|
|
|
|
* Hardware design:
|
|
|
|
* i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
|
|
|
|
* clock_div: fixed in hardware, but may be various in different SoCs
|
|
|
|
*
|
|
|
|
* The calculation want to pick the highest bus frequency that is still
|
|
|
|
* less than or equal to i2c->speed_hz. The calculation try to get
|
|
|
|
* sample_cnt and step_cn
|
|
|
|
*/
|
2017-07-17 11:02:10 +00:00
|
|
|
static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
|
|
|
|
unsigned int target_speed,
|
|
|
|
unsigned int *timing_step_cnt,
|
|
|
|
unsigned int *timing_sample_cnt)
|
2015-05-21 08:53:28 +00:00
|
|
|
{
|
|
|
|
unsigned int step_cnt;
|
|
|
|
unsigned int sample_cnt;
|
|
|
|
unsigned int max_step_cnt;
|
|
|
|
unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
|
|
|
|
unsigned int base_step_cnt;
|
|
|
|
unsigned int opt_div;
|
|
|
|
unsigned int best_mul;
|
|
|
|
unsigned int cnt_mul;
|
2020-05-14 13:09:05 +00:00
|
|
|
int ret = -EINVAL;
|
2022-02-17 12:22:43 +00:00
|
|
|
int clk_div_restri = 0;
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2020-09-17 11:55:41 +00:00
|
|
|
if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
|
|
|
|
target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
|
2015-05-21 08:53:28 +00:00
|
|
|
base_step_cnt = max_step_cnt;
|
|
|
|
/* Find the best combination */
|
|
|
|
opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
|
|
|
|
best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
|
|
|
|
|
|
|
|
/* Search for the best pair (sample_cnt, step_cnt) with
|
|
|
|
* 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
|
|
|
|
* 0 < step_cnt < max_step_cnt
|
|
|
|
* sample_cnt * step_cnt >= opt_div
|
|
|
|
* optimizing for sample_cnt * step_cnt being minimal
|
|
|
|
*/
|
|
|
|
for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
|
2022-02-17 12:22:43 +00:00
|
|
|
clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
|
|
|
|
step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt);
|
2015-05-21 08:53:28 +00:00
|
|
|
cnt_mul = step_cnt * sample_cnt;
|
|
|
|
if (step_cnt > max_step_cnt)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (cnt_mul < best_mul) {
|
2020-05-14 13:09:05 +00:00
|
|
|
ret = mtk_i2c_check_ac_timing(i2c, clk_src,
|
|
|
|
target_speed, step_cnt - 1, sample_cnt - 1);
|
|
|
|
if (ret)
|
|
|
|
continue;
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
best_mul = cnt_mul;
|
|
|
|
base_sample_cnt = sample_cnt;
|
|
|
|
base_step_cnt = step_cnt;
|
2022-02-17 12:22:43 +00:00
|
|
|
if (best_mul == (opt_div + clk_div_restri))
|
2015-05-21 08:53:28 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
sample_cnt = base_sample_cnt;
|
|
|
|
step_cnt = base_step_cnt;
|
|
|
|
|
2022-02-17 12:22:43 +00:00
|
|
|
if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) >
|
|
|
|
target_speed) {
|
2015-05-21 08:53:28 +00:00
|
|
|
/* In this case, hardware can't support such
|
|
|
|
* low i2c_bus_freq
|
|
|
|
*/
|
|
|
|
dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2017-07-17 11:02:10 +00:00
|
|
|
*timing_step_cnt = step_cnt - 1;
|
|
|
|
*timing_sample_cnt = sample_cnt - 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
|
|
|
|
{
|
|
|
|
unsigned int clk_src;
|
|
|
|
unsigned int step_cnt;
|
|
|
|
unsigned int sample_cnt;
|
2019-04-02 12:35:59 +00:00
|
|
|
unsigned int l_step_cnt;
|
|
|
|
unsigned int l_sample_cnt;
|
2017-07-17 11:02:10 +00:00
|
|
|
unsigned int target_speed;
|
2020-05-14 13:09:05 +00:00
|
|
|
unsigned int clk_div;
|
|
|
|
unsigned int max_clk_div;
|
2017-07-17 11:02:10 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
target_speed = i2c->speed_hz;
|
2020-05-14 13:09:05 +00:00
|
|
|
parent_clk /= i2c->clk_src_div;
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2022-02-17 12:22:43 +00:00
|
|
|
if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
|
|
|
|
max_clk_div = MAX_CLOCK_DIV_5BITS;
|
|
|
|
else if (i2c->dev_comp->timing_adjust)
|
|
|
|
max_clk_div = MAX_CLOCK_DIV_8BITS;
|
2020-05-14 13:09:05 +00:00
|
|
|
else
|
|
|
|
max_clk_div = 1;
|
|
|
|
|
|
|
|
for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
|
|
|
|
clk_src = parent_clk / clk_div;
|
2022-02-17 12:22:43 +00:00
|
|
|
i2c->ac_timing.inter_clk_div = clk_div - 1;
|
2020-05-14 13:09:05 +00:00
|
|
|
|
2020-09-17 11:55:42 +00:00
|
|
|
if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
|
2020-05-14 13:09:05 +00:00
|
|
|
/* Set master code speed register */
|
|
|
|
ret = mtk_i2c_calculate_speed(i2c, clk_src,
|
|
|
|
I2C_MAX_FAST_MODE_FREQ,
|
|
|
|
&l_step_cnt,
|
|
|
|
&l_sample_cnt);
|
|
|
|
if (ret < 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
|
|
|
|
|
|
|
|
/* Set the high speed mode register */
|
|
|
|
ret = mtk_i2c_calculate_speed(i2c, clk_src,
|
|
|
|
target_speed, &step_cnt,
|
|
|
|
&sample_cnt);
|
|
|
|
if (ret < 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
|
|
|
|
(sample_cnt << 12) | (step_cnt << 8);
|
|
|
|
|
|
|
|
if (i2c->dev_comp->ltiming_adjust)
|
|
|
|
i2c->ltiming_reg =
|
|
|
|
(l_sample_cnt << 6) | l_step_cnt |
|
|
|
|
(sample_cnt << 12) | (step_cnt << 9);
|
|
|
|
} else {
|
|
|
|
ret = mtk_i2c_calculate_speed(i2c, clk_src,
|
|
|
|
target_speed, &l_step_cnt,
|
|
|
|
&l_sample_cnt);
|
|
|
|
if (ret < 0)
|
|
|
|
continue;
|
2019-04-02 12:35:59 +00:00
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
|
2017-07-17 11:02:10 +00:00
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
/* Disable the high speed transaction */
|
|
|
|
i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
|
2017-07-17 11:02:10 +00:00
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
if (i2c->dev_comp->ltiming_adjust)
|
|
|
|
i2c->ltiming_reg =
|
|
|
|
(l_sample_cnt << 6) | l_step_cnt;
|
|
|
|
}
|
2019-04-02 12:35:59 +00:00
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
break;
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
2020-05-14 13:09:05 +00:00
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-10-10 07:05:13 +00:00
|
|
|
static void i2c_dump_register(struct mtk_i2c *i2c)
|
|
|
|
{
|
|
|
|
dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
|
|
|
|
dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_CONTROL));
|
|
|
|
dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
|
|
|
|
dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_TIMING));
|
|
|
|
dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_START),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
|
|
|
|
dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_HS),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
|
|
|
|
dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_DCM_EN),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
|
|
|
|
dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
|
|
|
|
dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
|
|
|
|
if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
|
|
|
|
dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_LTIMING),
|
|
|
|
mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
|
|
|
|
}
|
|
|
|
dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
|
|
|
|
readl(i2c->pdmabase + OFFSET_INT_FLAG),
|
|
|
|
readl(i2c->pdmabase + OFFSET_INT_EN));
|
|
|
|
dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
|
|
|
|
readl(i2c->pdmabase + OFFSET_EN),
|
|
|
|
readl(i2c->pdmabase + OFFSET_CON));
|
|
|
|
dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
|
|
|
|
readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
|
|
|
|
readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
|
|
|
|
dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
|
|
|
|
readl(i2c->pdmabase + OFFSET_TX_LEN),
|
|
|
|
readl(i2c->pdmabase + OFFSET_RX_LEN));
|
|
|
|
dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
|
|
|
|
readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
|
|
|
|
readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
|
|
|
|
}
|
|
|
|
|
2015-05-21 08:53:30 +00:00
|
|
|
static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
|
|
|
|
int num, int left_num)
|
2015-05-21 08:53:28 +00:00
|
|
|
{
|
|
|
|
u16 addr_reg;
|
2015-05-21 08:53:30 +00:00
|
|
|
u16 start_reg;
|
2015-05-21 08:53:28 +00:00
|
|
|
u16 control_reg;
|
2015-05-21 08:53:30 +00:00
|
|
|
u16 restart_flag = 0;
|
2020-08-05 10:52:19 +00:00
|
|
|
u16 dma_sync = 0;
|
2016-02-01 17:19:03 +00:00
|
|
|
u32 reg_4g_mode;
|
2021-10-10 07:05:12 +00:00
|
|
|
u32 reg_dma_reset;
|
2018-09-06 13:15:29 +00:00
|
|
|
u8 *dma_rd_buf = NULL;
|
|
|
|
u8 *dma_wr_buf = NULL;
|
2015-05-21 08:53:28 +00:00
|
|
|
dma_addr_t rpaddr = 0;
|
|
|
|
dma_addr_t wpaddr = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
i2c->irq_stat = 0;
|
|
|
|
|
2015-11-09 05:43:58 +00:00
|
|
|
if (i2c->auto_restart)
|
2015-05-21 08:53:30 +00:00
|
|
|
restart_flag = I2C_RS_TRANSFER;
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
reinit_completion(&i2c->msg_complete);
|
|
|
|
|
2021-10-10 07:05:12 +00:00
|
|
|
if (i2c->dev_comp->apdma_sync &&
|
|
|
|
i2c->op != I2C_MASTER_WRRD && num > 1) {
|
|
|
|
mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
|
|
|
|
writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
|
|
|
|
i2c->pdmabase + OFFSET_RST);
|
|
|
|
|
|
|
|
ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
|
|
|
|
reg_dma_reset,
|
|
|
|
!(reg_dma_reset & I2C_DMA_WARM_RST),
|
|
|
|
0, 100);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(i2c->dev, "DMA warm reset timeout\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
|
|
|
|
mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
|
|
|
|
mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
|
|
|
|
mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
|
|
|
|
OFFSET_DEBUGCTRL);
|
|
|
|
}
|
|
|
|
|
2019-04-02 12:35:55 +00:00
|
|
|
control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
|
2015-05-21 08:53:28 +00:00
|
|
|
~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
|
2021-04-17 06:46:50 +00:00
|
|
|
if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
|
2015-05-21 08:53:28 +00:00
|
|
|
control_reg |= I2C_CONTROL_RS;
|
|
|
|
|
|
|
|
if (i2c->op == I2C_MASTER_WRRD)
|
|
|
|
control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
|
|
|
|
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2016-04-03 18:44:55 +00:00
|
|
|
addr_reg = i2c_8bit_addr_from_msg(msgs);
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
/* Clear interrupt status */
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
|
2019-04-02 12:35:57 +00:00
|
|
|
I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
|
2019-04-02 12:35:55 +00:00
|
|
|
|
|
|
|
mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
/* Enable interrupt */
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
|
2019-04-02 12:35:57 +00:00
|
|
|
I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
/* Set transfer and transaction len */
|
|
|
|
if (i2c->op == I2C_MASTER_WRRD) {
|
2015-11-09 05:43:58 +00:00
|
|
|
if (i2c->dev_comp->aux_len_reg) {
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
|
|
|
|
mtk_i2c_writew(i2c, (msgs + 1)->len,
|
|
|
|
OFFSET_TRANSFER_LEN_AUX);
|
2015-11-09 05:43:58 +00:00
|
|
|
} else {
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
|
|
|
|
OFFSET_TRANSFER_LEN);
|
2015-11-09 05:43:58 +00:00
|
|
|
}
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
|
2015-05-21 08:53:28 +00:00
|
|
|
} else {
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
|
|
|
|
mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
2020-08-05 10:52:19 +00:00
|
|
|
if (i2c->dev_comp->apdma_sync) {
|
|
|
|
dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
|
|
|
|
if (i2c->op == I2C_MASTER_WRRD)
|
|
|
|
dma_sync |= I2C_DMA_DIR_CHANGE;
|
|
|
|
}
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
/* Prepare buffer data to start transfer */
|
|
|
|
if (i2c->op == I2C_MASTER_RD) {
|
|
|
|
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
|
2020-08-05 10:52:19 +00:00
|
|
|
writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
|
2018-09-06 13:15:29 +00:00
|
|
|
|
2019-02-15 09:02:02 +00:00
|
|
|
dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
|
2018-09-06 13:15:29 +00:00
|
|
|
if (!dma_rd_buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
|
2015-05-21 08:53:28 +00:00
|
|
|
msgs->len, DMA_FROM_DEVICE);
|
2018-09-06 13:15:29 +00:00
|
|
|
if (dma_mapping_error(i2c->dev, rpaddr)) {
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
return -ENOMEM;
|
2018-09-06 13:15:29 +00:00
|
|
|
}
|
2016-02-01 17:19:03 +00:00
|
|
|
|
2020-08-05 10:52:20 +00:00
|
|
|
if (i2c->dev_comp->max_dma_support > 32) {
|
|
|
|
reg_4g_mode = upper_32_bits(rpaddr);
|
2016-02-01 17:19:03 +00:00
|
|
|
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
|
|
|
|
}
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
|
|
|
|
writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
|
|
|
|
} else if (i2c->op == I2C_MASTER_WR) {
|
|
|
|
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
|
2020-08-05 10:52:19 +00:00
|
|
|
writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
|
2018-09-06 13:15:29 +00:00
|
|
|
|
2019-02-15 09:02:02 +00:00
|
|
|
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
|
2018-09-06 13:15:29 +00:00
|
|
|
if (!dma_wr_buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
|
2015-05-21 08:53:28 +00:00
|
|
|
msgs->len, DMA_TO_DEVICE);
|
2018-09-06 13:15:29 +00:00
|
|
|
if (dma_mapping_error(i2c->dev, wpaddr)) {
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
return -ENOMEM;
|
2018-09-06 13:15:29 +00:00
|
|
|
}
|
2016-02-01 17:19:03 +00:00
|
|
|
|
2020-08-05 10:52:20 +00:00
|
|
|
if (i2c->dev_comp->max_dma_support > 32) {
|
|
|
|
reg_4g_mode = upper_32_bits(wpaddr);
|
2016-02-01 17:19:03 +00:00
|
|
|
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
|
|
|
|
}
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
|
|
|
|
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
|
|
|
|
} else {
|
|
|
|
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
|
2020-08-05 10:52:19 +00:00
|
|
|
writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
|
2018-09-06 13:15:29 +00:00
|
|
|
|
2019-02-15 09:02:02 +00:00
|
|
|
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
|
2018-09-06 13:15:29 +00:00
|
|
|
if (!dma_wr_buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
|
2015-05-21 08:53:28 +00:00
|
|
|
msgs->len, DMA_TO_DEVICE);
|
2018-09-06 13:15:29 +00:00
|
|
|
if (dma_mapping_error(i2c->dev, wpaddr)) {
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
return -ENOMEM;
|
2018-09-06 13:15:29 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 09:02:02 +00:00
|
|
|
dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
|
2018-09-06 13:15:29 +00:00
|
|
|
if (!dma_rd_buf) {
|
|
|
|
dma_unmap_single(i2c->dev, wpaddr,
|
|
|
|
msgs->len, DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
|
|
|
|
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
|
2015-05-21 08:53:28 +00:00
|
|
|
(msgs + 1)->len,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
if (dma_mapping_error(i2c->dev, rpaddr)) {
|
|
|
|
dma_unmap_single(i2c->dev, wpaddr,
|
|
|
|
msgs->len, DMA_TO_DEVICE);
|
2018-09-06 13:15:29 +00:00
|
|
|
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2016-02-01 17:19:03 +00:00
|
|
|
|
2020-08-05 10:52:20 +00:00
|
|
|
if (i2c->dev_comp->max_dma_support > 32) {
|
|
|
|
reg_4g_mode = upper_32_bits(wpaddr);
|
2016-02-01 17:19:03 +00:00
|
|
|
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
|
|
|
|
|
2020-08-05 10:52:20 +00:00
|
|
|
reg_4g_mode = upper_32_bits(rpaddr);
|
2016-02-01 17:19:03 +00:00
|
|
|
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
|
|
|
|
}
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
|
|
|
|
writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
|
|
|
|
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
|
|
|
|
writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
|
2015-05-21 08:53:30 +00:00
|
|
|
|
2015-11-09 05:43:58 +00:00
|
|
|
if (!i2c->auto_restart) {
|
2015-05-21 08:53:30 +00:00
|
|
|
start_reg = I2C_TRANSAC_START;
|
|
|
|
} else {
|
|
|
|
start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
|
|
|
|
if (left_num >= 1)
|
|
|
|
start_reg |= I2C_RS_MUL_CNFG;
|
|
|
|
}
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, start_reg, OFFSET_START);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
ret = wait_for_completion_timeout(&i2c->msg_complete,
|
|
|
|
i2c->adap.timeout);
|
|
|
|
|
|
|
|
/* Clear interrupt mask */
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
|
2019-04-02 12:35:57 +00:00
|
|
|
I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
if (i2c->op == I2C_MASTER_WR) {
|
|
|
|
dma_unmap_single(i2c->dev, wpaddr,
|
|
|
|
msgs->len, DMA_TO_DEVICE);
|
2018-09-06 13:15:29 +00:00
|
|
|
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
|
2015-05-21 08:53:28 +00:00
|
|
|
} else if (i2c->op == I2C_MASTER_RD) {
|
|
|
|
dma_unmap_single(i2c->dev, rpaddr,
|
|
|
|
msgs->len, DMA_FROM_DEVICE);
|
2018-09-06 13:15:29 +00:00
|
|
|
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
|
2015-05-21 08:53:28 +00:00
|
|
|
} else {
|
|
|
|
dma_unmap_single(i2c->dev, wpaddr, msgs->len,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
|
|
|
|
DMA_FROM_DEVICE);
|
2018-09-06 13:15:29 +00:00
|
|
|
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
|
|
|
|
i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ret == 0) {
|
|
|
|
dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
|
2021-10-10 07:05:13 +00:00
|
|
|
i2c_dump_register(i2c);
|
2015-05-21 08:53:28 +00:00
|
|
|
mtk_i2c_init_hw(i2c);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
|
|
|
|
dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
|
|
|
|
mtk_i2c_init_hw(i2c);
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_i2c_transfer(struct i2c_adapter *adap,
|
|
|
|
struct i2c_msg msgs[], int num)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int left_num = num;
|
|
|
|
struct mtk_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
|
2015-05-21 08:53:28 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-11-09 05:43:58 +00:00
|
|
|
i2c->auto_restart = i2c->dev_comp->auto_restart;
|
|
|
|
|
|
|
|
/* checking if we can skip restart and optimize using WRRD mode */
|
|
|
|
if (i2c->auto_restart && num == 2) {
|
|
|
|
if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
|
|
|
|
msgs[0].addr == msgs[1].addr) {
|
|
|
|
i2c->auto_restart = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-17 06:46:50 +00:00
|
|
|
if (i2c->auto_restart && num >= 2 &&
|
|
|
|
i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
|
2015-12-15 07:22:26 +00:00
|
|
|
/* ignore the first restart irq after the master code,
|
|
|
|
* otherwise the first transfer will be discarded.
|
|
|
|
*/
|
|
|
|
i2c->ignore_restart_irq = true;
|
|
|
|
else
|
|
|
|
i2c->ignore_restart_irq = false;
|
|
|
|
|
2015-05-21 08:53:30 +00:00
|
|
|
while (left_num--) {
|
|
|
|
if (!msgs->buf) {
|
|
|
|
dev_dbg(i2c->dev, "data buffer is NULL.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_exit;
|
|
|
|
}
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2015-05-21 08:53:30 +00:00
|
|
|
if (msgs->flags & I2C_M_RD)
|
|
|
|
i2c->op = I2C_MASTER_RD;
|
|
|
|
else
|
|
|
|
i2c->op = I2C_MASTER_WR;
|
|
|
|
|
2015-11-09 05:43:58 +00:00
|
|
|
if (!i2c->auto_restart) {
|
2015-05-21 08:53:30 +00:00
|
|
|
if (num > 1) {
|
|
|
|
/* combined two messages into one transaction */
|
|
|
|
i2c->op = I2C_MASTER_WRRD;
|
|
|
|
left_num--;
|
|
|
|
}
|
|
|
|
}
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2015-05-21 08:53:30 +00:00
|
|
|
/* always use DMA mode. */
|
|
|
|
ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_exit;
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2015-05-21 08:53:30 +00:00
|
|
|
msgs++;
|
|
|
|
}
|
2015-05-21 08:53:28 +00:00
|
|
|
/* the return value is number of executed messages */
|
|
|
|
ret = num;
|
|
|
|
|
|
|
|
err_exit:
|
2022-03-03 09:15:47 +00:00
|
|
|
clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
|
2015-05-21 08:53:28 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
|
|
|
|
{
|
|
|
|
struct mtk_i2c *i2c = dev_id;
|
2015-05-21 08:53:30 +00:00
|
|
|
u16 restart_flag = 0;
|
2015-08-06 07:22:11 +00:00
|
|
|
u16 intr_stat;
|
2015-05-21 08:53:30 +00:00
|
|
|
|
2015-11-09 05:43:58 +00:00
|
|
|
if (i2c->auto_restart)
|
2015-05-21 08:53:30 +00:00
|
|
|
restart_flag = I2C_RS_TRANSFER;
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2019-04-02 12:35:55 +00:00
|
|
|
intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
|
|
|
|
mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2015-08-06 07:22:11 +00:00
|
|
|
/*
|
|
|
|
* when occurs ack error, i2c controller generate two interrupts
|
|
|
|
* first is the ack error interrupt, then the complete interrupt
|
|
|
|
* i2c->irq_stat need keep the two interrupt value.
|
|
|
|
*/
|
|
|
|
i2c->irq_stat |= intr_stat;
|
2015-12-15 07:22:26 +00:00
|
|
|
|
|
|
|
if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
|
|
|
|
i2c->ignore_restart_irq = false;
|
|
|
|
i2c->irq_stat = 0;
|
2019-04-02 12:35:55 +00:00
|
|
|
mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
|
|
|
|
I2C_TRANSAC_START, OFFSET_START);
|
2015-12-15 07:22:26 +00:00
|
|
|
} else {
|
|
|
|
if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
|
|
|
|
complete(&i2c->msg_complete);
|
|
|
|
}
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
|
|
|
|
{
|
2019-10-18 17:32:13 +00:00
|
|
|
if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
|
2019-08-22 09:45:17 +00:00
|
|
|
return I2C_FUNC_I2C |
|
|
|
|
(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
|
|
|
else
|
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_algorithm mtk_i2c_algorithm = {
|
|
|
|
.master_xfer = mtk_i2c_transfer,
|
|
|
|
.functionality = mtk_i2c_functionality,
|
|
|
|
};
|
|
|
|
|
2017-07-17 11:02:10 +00:00
|
|
|
static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
|
2015-05-21 08:53:28 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
|
|
|
|
if (ret < 0)
|
2020-03-24 12:32:16 +00:00
|
|
|
i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2017-07-17 11:02:10 +00:00
|
|
|
ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
|
2015-05-21 08:53:28 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2017-07-17 11:02:10 +00:00
|
|
|
if (i2c->clk_src_div == 0)
|
2015-05-21 08:53:28 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
|
|
|
|
i2c->use_push_pull =
|
|
|
|
of_property_read_bool(np, "mediatek,use-push-pull");
|
|
|
|
|
2021-04-17 06:46:52 +00:00
|
|
|
i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_i2c_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct mtk_i2c *i2c;
|
|
|
|
struct resource *res;
|
2022-03-03 09:15:47 +00:00
|
|
|
int i, irq, speed_clk;
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
|
|
|
|
if (!i2c)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
i2c->base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(i2c->base))
|
|
|
|
return PTR_ERR(i2c->base);
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
|
|
i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(i2c->pdmabase))
|
|
|
|
return PTR_ERR(i2c->pdmabase);
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2021-07-04 14:38:45 +00:00
|
|
|
if (irq < 0)
|
2015-05-21 08:53:28 +00:00
|
|
|
return irq;
|
|
|
|
|
|
|
|
init_completion(&i2c->msg_complete);
|
|
|
|
|
2018-04-16 02:32:52 +00:00
|
|
|
i2c->dev_comp = of_device_get_match_data(&pdev->dev);
|
2015-05-21 08:53:28 +00:00
|
|
|
i2c->adap.dev.of_node = pdev->dev.of_node;
|
|
|
|
i2c->dev = &pdev->dev;
|
|
|
|
i2c->adap.dev.parent = &pdev->dev;
|
|
|
|
i2c->adap.owner = THIS_MODULE;
|
|
|
|
i2c->adap.algo = &mtk_i2c_algorithm;
|
|
|
|
i2c->adap.quirks = i2c->dev_comp->quirks;
|
|
|
|
i2c->adap.timeout = 2 * HZ;
|
|
|
|
i2c->adap.retries = 1;
|
2021-05-27 07:55:55 +00:00
|
|
|
i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus");
|
|
|
|
if (IS_ERR(i2c->adap.bus_regulator)) {
|
|
|
|
if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV)
|
|
|
|
i2c->adap.bus_regulator = NULL;
|
|
|
|
else
|
|
|
|
return PTR_ERR(i2c->adap.bus_regulator);
|
|
|
|
}
|
2015-05-21 08:53:28 +00:00
|
|
|
|
2017-12-19 06:51:02 +00:00
|
|
|
ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
/* Fill in clk-bulk IDs */
|
|
|
|
for (i = 0; i < I2C_MT65XX_CLK_MAX; i++)
|
|
|
|
i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
|
|
|
|
|
|
|
|
/* Get clocks one by one, some may be optional */
|
|
|
|
i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
|
|
|
|
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
|
2015-05-21 08:53:28 +00:00
|
|
|
dev_err(&pdev->dev, "cannot get main clock\n");
|
2022-03-03 09:15:47 +00:00
|
|
|
return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
|
|
|
|
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
|
2015-05-21 08:53:28 +00:00
|
|
|
dev_err(&pdev->dev, "cannot get dma clock\n");
|
2022-03-03 09:15:47 +00:00
|
|
|
return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
|
|
|
|
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
|
|
|
|
return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
|
2019-04-02 12:35:57 +00:00
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
if (i2c->have_pmic) {
|
2022-03-03 09:15:47 +00:00
|
|
|
i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
|
|
|
|
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
|
2015-05-21 08:53:28 +00:00
|
|
|
dev_err(&pdev->dev, "cannot get pmic clock\n");
|
2022-03-03 09:15:47 +00:00
|
|
|
return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
2022-03-03 09:15:47 +00:00
|
|
|
speed_clk = I2C_MT65XX_CLK_PMIC;
|
|
|
|
} else {
|
|
|
|
i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
|
|
|
|
speed_clk = I2C_MT65XX_CLK_MAIN;
|
2015-05-21 08:53:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
|
2015-05-21 08:53:28 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Failed to set the speed.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-08-05 10:52:20 +00:00
|
|
|
if (i2c->dev_comp->max_dma_support > 32) {
|
|
|
|
ret = dma_set_mask(&pdev->dev,
|
|
|
|
DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
|
2016-02-01 17:19:03 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "dma_set_mask return error.\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
|
2015-05-21 08:53:28 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "clock enable failed!\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
mtk_i2c_init_hw(i2c);
|
2022-03-03 09:15:47 +00:00
|
|
|
clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
|
2015-05-21 08:53:28 +00:00
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
|
2021-01-09 08:29:50 +00:00
|
|
|
IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
|
2021-05-27 11:31:50 +00:00
|
|
|
dev_name(&pdev->dev), i2c);
|
2015-05-21 08:53:28 +00:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Request I2C IRQ %d fail\n", irq);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
|
|
|
ret = i2c_add_adapter(&i2c->adap);
|
2016-08-09 11:36:17 +00:00
|
|
|
if (ret)
|
2015-05-21 08:53:28 +00:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_i2c_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct mtk_i2c *i2c = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-10-06 09:22:56 +00:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2021-01-09 08:29:50 +00:00
|
|
|
static int mtk_i2c_suspend_noirq(struct device *dev)
|
|
|
|
{
|
|
|
|
struct mtk_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
i2c_mark_adapter_suspended(&i2c->adap);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_i2c_resume_noirq(struct device *dev)
|
2015-10-06 09:22:56 +00:00
|
|
|
{
|
2017-12-19 06:51:03 +00:00
|
|
|
int ret;
|
2015-10-06 09:22:56 +00:00
|
|
|
struct mtk_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
|
2017-12-19 06:51:03 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "clock enable failed!\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-10-06 09:22:56 +00:00
|
|
|
mtk_i2c_init_hw(i2c);
|
|
|
|
|
2022-03-03 09:15:47 +00:00
|
|
|
clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
|
2017-12-19 06:51:03 +00:00
|
|
|
|
2021-01-09 08:29:50 +00:00
|
|
|
i2c_mark_adapter_resumed(&i2c->adap);
|
|
|
|
|
2015-10-06 09:22:56 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct dev_pm_ops mtk_i2c_pm = {
|
2021-01-09 08:29:50 +00:00
|
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
|
|
|
|
mtk_i2c_resume_noirq)
|
2015-10-06 09:22:56 +00:00
|
|
|
};
|
|
|
|
|
2015-05-21 08:53:28 +00:00
|
|
|
static struct platform_driver mtk_i2c_driver = {
|
|
|
|
.probe = mtk_i2c_probe,
|
|
|
|
.remove = mtk_i2c_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = I2C_DRV_NAME,
|
2015-10-06 09:22:56 +00:00
|
|
|
.pm = &mtk_i2c_pm,
|
2015-05-21 08:53:28 +00:00
|
|
|
.of_match_table = of_match_ptr(mtk_i2c_of_match),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(mtk_i2c_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
|
|
|
|
MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
|