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linux-stable/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-...

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ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an i.MX6UL or i.MX6ULL SOM and various add-on boards. The following adds support for the "Full Featured" version of the Segin, which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation module. Its hardware specifications are: * 512MB DDR3 memory * 512MB NAND flash * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-21 09:57:05 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 PHYTEC Messtechnik GmbH
* Author: Christian Hemp <c.hemp@phytec.de>
*/
/dts-v1/;
ARM: dts: imx6ul: phyboard-segin: Rename dts to PHYTEC name scheme Use the same name scheme for the phyBOARD-Segin and the phyCORE-i.MX 6UL as is used for the PHYTEC phyBOARD-Mira and phyCORE-i.MX 6. This is only a cosmetic change and there is no functional change intended. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-09 07:19:18 +00:00
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an i.MX6UL or i.MX6ULL SOM and various add-on boards. The following adds support for the "Full Featured" version of the Segin, which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation module. Its hardware specifications are: * 512MB DDR3 memory * 512MB NAND flash * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-21 09:57:05 +00:00
/ {
ARM: dts: imx6ul: segin: Add boot media to dts filename There is now a PHYTEC phyCORE-i.MX 6UL with eMMC instead of NAND flash available. The dts filename needs to reflect that to differentiate both. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-09 07:19:19 +00:00
model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
"phytec,imx6ul-pcl063", "fsl,imx6ul";
ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an i.MX6UL or i.MX6ULL SOM and various add-on boards. The following adds support for the "Full Featured" version of the Segin, which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation module. Its hardware specifications are: * 512MB DDR3 memory * 512MB NAND flash * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-21 09:57:05 +00:00
};
&adc1 {
status = "okay";
};
&can1 {
status = "okay";
};
&tlv320 {
status = "okay";
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec2 {
status = "okay";
};
&i2c_rtc {
status = "okay";
};
&reg_can1_en {
status = "okay";
};
&reg_sound_1v8 {
status = "okay";
};
&reg_sound_3v3 {
status = "okay";
};
&sai2 {
status = "okay";
};
&sound {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbotg1 {
status = "okay";
};
&usbotg2 {
status = "okay";
};
&usdhc1 {
status = "okay";
};
&iomuxc {
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
>;
};
};