License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-16 22:20:36 +00:00
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/*
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* linux/arch/alpha/kernel/core_t2.c
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*
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* Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
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* December 1996.
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*
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* based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
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*
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* Code common to all T2 core logic chips.
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*/
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#define __EXTERN_INLINE
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#include <asm/io.h>
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#include <asm/core_t2.h>
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#undef __EXTERN_INLINE
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/delay.h>
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2012-03-28 17:11:12 +00:00
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#include <asm/mce.h>
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2005-04-16 22:20:36 +00:00
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#include "proto.h"
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#include "pci_impl.h"
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/* For dumping initial DMA window settings. */
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#define DEBUG_PRINT_INITIAL_SETTINGS 0
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/* For dumping final DMA window settings. */
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#define DEBUG_PRINT_FINAL_SETTINGS 0
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/*
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* By default, we direct-map starting at 2GB, in order to allow the
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* maximum size direct-map window (2GB) to match the maximum amount of
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* memory (2GB) that can be present on SABLEs. But that limits the
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* floppy to DMA only via the scatter/gather window set up for 8MB
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* ISA DMA, since the maximum ISA DMA address is 2GB-1.
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*
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* For now, this seems a reasonable trade-off: even though most SABLEs
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* have less than 1GB of memory, floppy usage/performance will not
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* really be affected by forcing it to go via scatter/gather...
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*/
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#define T2_DIRECTMAP_2G 1
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#if T2_DIRECTMAP_2G
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# define T2_DIRECTMAP_START 0x80000000UL
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# define T2_DIRECTMAP_LENGTH 0x80000000UL
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#else
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# define T2_DIRECTMAP_START 0x40000000UL
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# define T2_DIRECTMAP_LENGTH 0x40000000UL
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#endif
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/* The ISA scatter/gather window settings. */
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#define T2_ISA_SG_START 0x00800000UL
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#define T2_ISA_SG_LENGTH 0x00800000UL
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/*
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* NOTE: Herein lie back-to-back mb instructions. They are magic.
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* One plausible explanation is that the i/o controller does not properly
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* handle the system transaction. Another involves timing. Ho hum.
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*/
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/*
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* BIOS32-style PCI interface:
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*/
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#define DEBUG_CONFIG 0
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#if DEBUG_CONFIG
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# define DBG(args) printk args
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#else
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# define DBG(args)
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#endif
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static volatile unsigned int t2_mcheck_any_expected;
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static volatile unsigned int t2_mcheck_last_taken;
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/* Place to save the DMA Window registers as set up by SRM
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for restoration during shutdown. */
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static struct
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{
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struct {
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unsigned long wbase;
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unsigned long wmask;
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unsigned long tbase;
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} window[2];
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unsigned long hae_1;
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unsigned long hae_2;
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unsigned long hae_3;
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unsigned long hae_4;
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unsigned long hbase;
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} t2_saved_config __attribute((common));
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/*
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* Given a bus, device, and function number, compute resulting
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* configuration space address and setup the T2_HAXR2 register
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* accordingly. It is therefore not safe to have concurrent
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* invocations to configuration space access routines, but there
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* really shouldn't be any need for this.
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*
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* Type 0:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:11 Device select bit.
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* 10:8 Function number
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* 7:2 Register number
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*
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* Type 1:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:24 reserved
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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* Notes:
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* The function number selects which function of a multi-function device
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* (e.g., SCSI and Ethernet).
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*
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* The register selects a DWORD (32 bit) register offset. Hence it
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two
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* bits.
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*/
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static int
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr, unsigned char *type1)
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{
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unsigned long addr;
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u8 bus = pbus->number;
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DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
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" addr=0x%lx, type1=0x%x)\n",
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bus, device_fn, where, pci_addr, type1));
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if (bus == 0) {
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int device = device_fn >> 3;
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/* Type 0 configuration cycle. */
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if (device > 8) {
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DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
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device));
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return -1;
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}
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*type1 = 0;
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addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where);
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} else {
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/* Type 1 configuration cycle. */
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*type1 = 1;
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addr = (bus << 16) | (device_fn << 8) | (where);
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}
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*pci_addr = addr;
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DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
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return 0;
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}
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/*
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* NOTE: both conf_read() and conf_write() may set HAE_3 when needing
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* to do type1 access. This is protected by the use of spinlock IRQ
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* primitives in the wrapper functions pci_{read,write}_config_*()
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* defined in drivers/pci/pci.c.
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*/
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static unsigned int
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conf_read(unsigned long addr, unsigned char type1)
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{
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unsigned int value, cpu, taken;
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unsigned long t2_cfg = 0;
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cpu = smp_processor_id();
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DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
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/* If Type1 access, must set T2 CFG. */
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if (type1) {
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t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
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*(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
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mb();
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}
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mb();
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draina();
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mcheck_expected(cpu) = 1;
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mcheck_taken(cpu) = 0;
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t2_mcheck_any_expected |= (1 << cpu);
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mb();
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/* Access configuration space. */
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value = *(vuip)addr;
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mb();
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mb(); /* magic */
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/* Wait for possible mcheck. Also, this lets other CPUs clear
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their mchecks as well, as they can reliably tell when
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another CPU is in the midst of handling a real mcheck via
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the "taken" function. */
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udelay(100);
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if ((taken = mcheck_taken(cpu))) {
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mcheck_taken(cpu) = 0;
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t2_mcheck_last_taken |= (1 << cpu);
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value = 0xffffffffU;
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mb();
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}
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mcheck_expected(cpu) = 0;
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t2_mcheck_any_expected = 0;
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|
|
|
mb();
|
|
|
|
|
|
|
|
|
|
|
|
/* If Type1 access, must reset T2 CFG so normal IO space ops work. */
|
|
|
|
|
|
if (type1) {
|
|
|
|
|
|
*(vulp)T2_HAE_3 = t2_cfg;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return value;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
conf_write(unsigned long addr, unsigned int value, unsigned char type1)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned int cpu, taken;
|
|
|
|
|
|
unsigned long t2_cfg = 0;
|
|
|
|
|
|
|
|
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
|
|
|
|
|
|
|
|
/* If Type1 access, must set T2 CFG. */
|
|
|
|
|
|
if (type1) {
|
|
|
|
|
|
t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
|
|
|
|
|
|
*(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
}
|
|
|
|
|
|
mb();
|
|
|
|
|
|
draina();
|
|
|
|
|
|
|
|
|
|
|
|
mcheck_expected(cpu) = 1;
|
|
|
|
|
|
mcheck_taken(cpu) = 0;
|
|
|
|
|
|
t2_mcheck_any_expected |= (1 << cpu);
|
|
|
|
|
|
mb();
|
|
|
|
|
|
|
|
|
|
|
|
/* Access configuration space. */
|
|
|
|
|
|
*(vuip)addr = value;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
mb(); /* magic */
|
|
|
|
|
|
|
|
|
|
|
|
/* Wait for possible mcheck. Also, this lets other CPUs clear
|
|
|
|
|
|
their mchecks as well, as they can reliably tell when
|
|
|
|
|
|
this CPU is in the midst of handling a real mcheck via
|
|
|
|
|
|
the "taken" function. */
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
|
|
|
|
|
|
|
if ((taken = mcheck_taken(cpu))) {
|
|
|
|
|
|
mcheck_taken(cpu) = 0;
|
|
|
|
|
|
t2_mcheck_last_taken |= (1 << cpu);
|
|
|
|
|
|
mb();
|
|
|
|
|
|
}
|
|
|
|
|
|
mcheck_expected(cpu) = 0;
|
|
|
|
|
|
t2_mcheck_any_expected = 0;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
|
|
|
|
|
|
/* If Type1 access, must reset T2 CFG so normal IO space ops work. */
|
|
|
|
|
|
if (type1) {
|
|
|
|
|
|
*(vulp)T2_HAE_3 = t2_cfg;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
|
t2_read_config(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
|
|
|
int size, u32 *value)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned long addr, pci_addr;
|
|
|
|
|
|
unsigned char type1;
|
|
|
|
|
|
int shift;
|
|
|
|
|
|
long mask;
|
|
|
|
|
|
|
|
|
|
|
|
if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
|
|
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
|
|
|
|
|
|
|
mask = (size - 1) * 8;
|
|
|
|
|
|
shift = (where & 3) * 8;
|
|
|
|
|
|
addr = (pci_addr << 5) + mask + T2_CONF;
|
|
|
|
|
|
*value = conf_read(addr, type1) >> (shift);
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
|
t2_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
|
|
|
|
|
|
u32 value)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned long addr, pci_addr;
|
|
|
|
|
|
unsigned char type1;
|
|
|
|
|
|
long mask;
|
|
|
|
|
|
|
|
|
|
|
|
if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
|
|
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
|
|
|
|
|
|
|
mask = (size - 1) * 8;
|
|
|
|
|
|
addr = (pci_addr << 5) + mask + T2_CONF;
|
|
|
|
|
|
conf_write(addr, value << ((where & 3) * 8), type1);
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
struct pci_ops t2_pci_ops =
|
|
|
|
|
|
{
|
|
|
|
|
|
.read = t2_read_config,
|
|
|
|
|
|
.write = t2_write_config,
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
|
t2_direct_map_window1(unsigned long base, unsigned long length)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned long temp;
|
|
|
|
|
|
|
|
|
|
|
|
__direct_map_base = base;
|
|
|
|
|
|
__direct_map_size = length;
|
|
|
|
|
|
|
|
|
|
|
|
temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
|
|
|
|
|
|
*(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
|
|
|
|
|
|
temp = (length - 1) & 0xfff00000UL;
|
|
|
|
|
|
*(vulp)T2_WMASK1 = temp;
|
|
|
|
|
|
*(vulp)T2_TBASE1 = 0;
|
|
|
|
|
|
|
|
|
|
|
|
#if DEBUG_PRINT_FINAL_SETTINGS
|
|
|
|
|
|
printk("%s: setting WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",
|
2008-04-28 09:13:46 +00:00
|
|
|
|
__func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
#endif
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
|
t2_sg_map_window2(struct pci_controller *hose,
|
|
|
|
|
|
unsigned long base,
|
|
|
|
|
|
unsigned long length)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned long temp;
|
|
|
|
|
|
|
|
|
|
|
|
/* Note we can only do 1 SG window, as the other is for direct, so
|
|
|
|
|
|
do an ISA SG area, especially for the floppy. */
|
memblock: stop using implicit alignment to SMP_CACHE_BYTES
When a memblock allocation APIs are called with align = 0, the alignment
is implicitly set to SMP_CACHE_BYTES.
Implicit alignment is done deep in the memblock allocator and it can
come as a surprise. Not that such an alignment would be wrong even
when used incorrectly but it is better to be explicit for the sake of
clarity and the prinicple of the least surprise.
Replace all such uses of memblock APIs with the 'align' parameter
explicitly set to SMP_CACHE_BYTES and stop implicit alignment assignment
in the memblock internal allocation functions.
For the case when memblock APIs are used via helper functions, e.g. like
iommu_arena_new_node() in Alpha, the helper functions were detected with
Coccinelle's help and then manually examined and updated where
appropriate.
The direct memblock APIs users were updated using the semantic patch below:
@@
expression size, min_addr, max_addr, nid;
@@
(
|
- memblock_alloc_try_nid_raw(size, 0, min_addr, max_addr, nid)
+ memblock_alloc_try_nid_raw(size, SMP_CACHE_BYTES, min_addr, max_addr,
nid)
|
- memblock_alloc_try_nid_nopanic(size, 0, min_addr, max_addr, nid)
+ memblock_alloc_try_nid_nopanic(size, SMP_CACHE_BYTES, min_addr, max_addr,
nid)
|
- memblock_alloc_try_nid(size, 0, min_addr, max_addr, nid)
+ memblock_alloc_try_nid(size, SMP_CACHE_BYTES, min_addr, max_addr, nid)
|
- memblock_alloc(size, 0)
+ memblock_alloc(size, SMP_CACHE_BYTES)
|
- memblock_alloc_raw(size, 0)
+ memblock_alloc_raw(size, SMP_CACHE_BYTES)
|
- memblock_alloc_from(size, 0, min_addr)
+ memblock_alloc_from(size, SMP_CACHE_BYTES, min_addr)
|
- memblock_alloc_nopanic(size, 0)
+ memblock_alloc_nopanic(size, SMP_CACHE_BYTES)
|
- memblock_alloc_low(size, 0)
+ memblock_alloc_low(size, SMP_CACHE_BYTES)
|
- memblock_alloc_low_nopanic(size, 0)
+ memblock_alloc_low_nopanic(size, SMP_CACHE_BYTES)
|
- memblock_alloc_from_nopanic(size, 0, min_addr)
+ memblock_alloc_from_nopanic(size, SMP_CACHE_BYTES, min_addr)
|
- memblock_alloc_node(size, 0, nid)
+ memblock_alloc_node(size, SMP_CACHE_BYTES, nid)
)
[mhocko@suse.com: changelog update]
[akpm@linux-foundation.org: coding-style fixes]
[rppt@linux.ibm.com: fix missed uses of implicit alignment]
Link: http://lkml.kernel.org/r/20181016133656.GA10925@rapoport-lnx
Link: http://lkml.kernel.org/r/1538687224-17535-1-git-send-email-rppt@linux.vnet.ibm.com
Signed-off-by: Mike Rapoport <rppt@linux.vnet.ibm.com>
Suggested-by: Michal Hocko <mhocko@suse.com>
Acked-by: Paul Burton <paul.burton@mips.com> [MIPS]
Acked-by: Michael Ellerman <mpe@ellerman.id.au> [powerpc]
Acked-by: Michal Hocko <mhocko@suse.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Richard Weinberger <richard@nod.at>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2018-10-30 22:09:57 +00:00
|
|
|
|
hose->sg_isa = iommu_arena_new(hose, base, length, SMP_CACHE_BYTES);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
hose->sg_pci = NULL;
|
|
|
|
|
|
|
|
|
|
|
|
temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
|
|
|
|
|
|
*(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */
|
|
|
|
|
|
temp = (length - 1) & 0xfff00000UL;
|
|
|
|
|
|
*(vulp)T2_WMASK2 = temp;
|
|
|
|
|
|
*(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
|
|
|
|
|
|
t2_pci_tbi(hose, 0, -1); /* flush TLB all */
|
|
|
|
|
|
|
|
|
|
|
|
#if DEBUG_PRINT_FINAL_SETTINGS
|
|
|
|
|
|
printk("%s: setting WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",
|
2008-04-28 09:13:46 +00:00
|
|
|
|
__func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
#endif
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
|
t2_save_configuration(void)
|
|
|
|
|
|
{
|
|
|
|
|
|
#if DEBUG_PRINT_INITIAL_SETTINGS
|
2008-04-28 09:13:46 +00:00
|
|
|
|
printk("%s: HAE_1 was 0x%lx\n", __func__, srm_hae); /* HW is 0 */
|
|
|
|
|
|
printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2);
|
|
|
|
|
|
printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3);
|
|
|
|
|
|
printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4);
|
|
|
|
|
|
printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
2008-04-28 09:13:46 +00:00
|
|
|
|
printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __func__,
|
2005-04-16 22:20:36 +00:00
|
|
|
|
*(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
|
2008-04-28 09:13:46 +00:00
|
|
|
|
printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __func__,
|
2005-04-16 22:20:36 +00:00
|
|
|
|
*(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Save the DMA Window registers.
|
|
|
|
|
|
*/
|
|
|
|
|
|
t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;
|
|
|
|
|
|
t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;
|
|
|
|
|
|
t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;
|
|
|
|
|
|
t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;
|
|
|
|
|
|
t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;
|
|
|
|
|
|
t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;
|
|
|
|
|
|
|
|
|
|
|
|
t2_saved_config.hae_1 = srm_hae; /* HW is already set to 0 */
|
|
|
|
|
|
t2_saved_config.hae_2 = *(vulp)T2_HAE_2;
|
|
|
|
|
|
t2_saved_config.hae_3 = *(vulp)T2_HAE_3;
|
|
|
|
|
|
t2_saved_config.hae_4 = *(vulp)T2_HAE_4;
|
|
|
|
|
|
t2_saved_config.hbase = *(vulp)T2_HBASE;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void __init
|
|
|
|
|
|
t2_init_arch(void)
|
|
|
|
|
|
{
|
|
|
|
|
|
struct pci_controller *hose;
|
2010-10-26 21:22:17 +00:00
|
|
|
|
struct resource *hae_mem;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < NR_CPUS; i++) {
|
|
|
|
|
|
mcheck_expected(i) = 0;
|
|
|
|
|
|
mcheck_taken(i) = 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
t2_mcheck_any_expected = 0;
|
|
|
|
|
|
t2_mcheck_last_taken = 0;
|
|
|
|
|
|
|
|
|
|
|
|
/* Enable scatter/gather TLB use. */
|
|
|
|
|
|
temp = *(vulp)T2_IOCSR;
|
|
|
|
|
|
if (!(temp & (0x1UL << 26))) {
|
|
|
|
|
|
printk("t2_init_arch: enabling SG TLB, IOCSR was 0x%lx\n",
|
|
|
|
|
|
temp);
|
|
|
|
|
|
*(vulp)T2_IOCSR = temp | (0x1UL << 26);
|
|
|
|
|
|
mb();
|
|
|
|
|
|
*(vulp)T2_IOCSR; /* read it back to make sure */
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
t2_save_configuration();
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Create our single hose.
|
|
|
|
|
|
*/
|
|
|
|
|
|
pci_isa_hose = hose = alloc_pci_controller();
|
|
|
|
|
|
hose->io_space = &ioport_resource;
|
2010-10-26 21:22:17 +00:00
|
|
|
|
hae_mem = alloc_resource();
|
|
|
|
|
|
hae_mem->start = 0;
|
|
|
|
|
|
hae_mem->end = T2_MEM_R1_MASK;
|
|
|
|
|
|
hae_mem->name = pci_hae0_name;
|
|
|
|
|
|
if (request_resource(&iomem_resource, hae_mem) < 0)
|
|
|
|
|
|
printk(KERN_ERR "Failed to request HAE_MEM\n");
|
|
|
|
|
|
hose->mem_space = hae_mem;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
hose->index = 0;
|
|
|
|
|
|
|
|
|
|
|
|
hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR;
|
|
|
|
|
|
hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR;
|
|
|
|
|
|
hose->sparse_io_base = T2_IO - IDENT_ADDR;
|
|
|
|
|
|
hose->dense_io_base = 0;
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Set up the PCI->physical memory translation windows.
|
|
|
|
|
|
*
|
|
|
|
|
|
* Window 1 is direct mapped.
|
|
|
|
|
|
* Window 2 is scatter/gather (for ISA).
|
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
|
|
t2_direct_map_window1(T2_DIRECTMAP_START, T2_DIRECTMAP_LENGTH);
|
|
|
|
|
|
|
|
|
|
|
|
/* Always make an ISA DMA window. */
|
|
|
|
|
|
t2_sg_map_window2(hose, T2_ISA_SG_START, T2_ISA_SG_LENGTH);
|
|
|
|
|
|
|
|
|
|
|
|
*(vulp)T2_HBASE = 0x0; /* Disable HOLES. */
|
|
|
|
|
|
|
|
|
|
|
|
/* Zero HAE. */
|
|
|
|
|
|
*(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */
|
|
|
|
|
|
*(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */
|
|
|
|
|
|
*(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* We also now zero out HAE_4, the dense memory HAE, so that
|
|
|
|
|
|
* we need not account for its "offset" when accessing dense
|
|
|
|
|
|
* memory resources which we allocated in our normal way. This
|
|
|
|
|
|
* HAE would need to stay untouched were we to keep the SRM
|
|
|
|
|
|
* resource settings.
|
|
|
|
|
|
*
|
|
|
|
|
|
* Thus we can now run standard X servers on SABLE/LYNX. :-)
|
|
|
|
|
|
*/
|
|
|
|
|
|
*(vulp)T2_HAE_4 = 0; mb();
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
|
t2_kill_arch(int mode)
|
|
|
|
|
|
{
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Restore the DMA Window registers.
|
|
|
|
|
|
*/
|
|
|
|
|
|
*(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;
|
|
|
|
|
|
*(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;
|
|
|
|
|
|
*(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;
|
|
|
|
|
|
*(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;
|
|
|
|
|
|
*(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;
|
|
|
|
|
|
*(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
|
|
|
|
|
|
*(vulp)T2_HAE_1 = srm_hae;
|
|
|
|
|
|
*(vulp)T2_HAE_2 = t2_saved_config.hae_2;
|
|
|
|
|
|
*(vulp)T2_HAE_3 = t2_saved_config.hae_3;
|
|
|
|
|
|
*(vulp)T2_HAE_4 = t2_saved_config.hae_4;
|
|
|
|
|
|
*(vulp)T2_HBASE = t2_saved_config.hbase;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
*(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
|
t2_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned long t2_iocsr;
|
|
|
|
|
|
|
|
|
|
|
|
t2_iocsr = *(vulp)T2_IOCSR;
|
|
|
|
|
|
|
|
|
|
|
|
/* set the TLB Clear bit */
|
|
|
|
|
|
*(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);
|
|
|
|
|
|
mb();
|
|
|
|
|
|
*(vulp)T2_IOCSR; /* read it back to make sure */
|
|
|
|
|
|
|
|
|
|
|
|
/* clear the TLB Clear bit */
|
|
|
|
|
|
*(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);
|
|
|
|
|
|
mb();
|
|
|
|
|
|
*(vulp)T2_IOCSR; /* read it back to make sure */
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#define SIC_SEIC (1UL << 33) /* System Event Clear */
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
t2_clear_errors(int cpu)
|
|
|
|
|
|
{
|
|
|
|
|
|
struct sable_cpu_csr *cpu_regs;
|
|
|
|
|
|
|
|
|
|
|
|
cpu_regs = (struct sable_cpu_csr *)T2_CPUn_BASE(cpu);
|
|
|
|
|
|
|
|
|
|
|
|
cpu_regs->sic &= ~SIC_SEIC;
|
|
|
|
|
|
|
|
|
|
|
|
/* Clear CPU errors. */
|
|
|
|
|
|
cpu_regs->bcce |= cpu_regs->bcce;
|
|
|
|
|
|
cpu_regs->cbe |= cpu_regs->cbe;
|
|
|
|
|
|
cpu_regs->bcue |= cpu_regs->bcue;
|
|
|
|
|
|
cpu_regs->dter |= cpu_regs->dter;
|
|
|
|
|
|
|
|
|
|
|
|
*(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
|
|
|
|
|
|
*(vulp)T2_PERR1 |= *(vulp)T2_PERR1;
|
|
|
|
|
|
|
|
|
|
|
|
mb();
|
|
|
|
|
|
mb(); /* magic */
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* SABLE seems to have a "broadcast" style machine check, in that all
|
|
|
|
|
|
* CPUs receive it. And, the issuing CPU, in the case of PCI Config
|
|
|
|
|
|
* space read/write faults, will also receive a second mcheck, upon
|
|
|
|
|
|
* lowering IPL during completion processing in pci_read_config_byte()
|
|
|
|
|
|
* et al.
|
|
|
|
|
|
*
|
|
|
|
|
|
* Hence all the taken/expected/any_expected/last_taken stuff...
|
|
|
|
|
|
*/
|
|
|
|
|
|
void
|
2006-10-08 13:44:38 +00:00
|
|
|
|
t2_machine_check(unsigned long vector, unsigned long la_ptr)
|
2005-04-16 22:20:36 +00:00
|
|
|
|
{
|
|
|
|
|
|
int cpu = smp_processor_id();
|
|
|
|
|
|
#ifdef CONFIG_VERBOSE_MCHECK
|
|
|
|
|
|
struct el_common *mchk_header = (struct el_common *)la_ptr;
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
/* Clear the error before any reporting. */
|
|
|
|
|
|
mb();
|
|
|
|
|
|
mb(); /* magic */
|
|
|
|
|
|
draina();
|
|
|
|
|
|
t2_clear_errors(cpu);
|
|
|
|
|
|
|
|
|
|
|
|
/* This should not actually be done until the logout frame is
|
|
|
|
|
|
examined, but, since we don't do that, go on and do this... */
|
|
|
|
|
|
wrmces(0x7);
|
|
|
|
|
|
mb();
|
|
|
|
|
|
|
|
|
|
|
|
/* Now, do testing for the anomalous conditions. */
|
|
|
|
|
|
if (!mcheck_expected(cpu) && t2_mcheck_any_expected) {
|
|
|
|
|
|
/*
|
|
|
|
|
|
* FUNKY: Received mcheck on a CPU and not
|
|
|
|
|
|
* expecting it, but another CPU is expecting one.
|
|
|
|
|
|
*
|
|
|
|
|
|
* Just dismiss it for now on this CPU...
|
|
|
|
|
|
*/
|
|
|
|
|
|
#ifdef CONFIG_VERBOSE_MCHECK
|
|
|
|
|
|
if (alpha_verbose_mcheck > 1) {
|
|
|
|
|
|
printk("t2_machine_check(cpu%d): any_expected 0x%x -"
|
|
|
|
|
|
" (assumed) spurious -"
|
|
|
|
|
|
" code 0x%x\n", cpu, t2_mcheck_any_expected,
|
|
|
|
|
|
(unsigned int)mchk_header->code);
|
|
|
|
|
|
}
|
|
|
|
|
|
#endif
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (!mcheck_expected(cpu) && !t2_mcheck_any_expected) {
|
|
|
|
|
|
if (t2_mcheck_last_taken & (1 << cpu)) {
|
|
|
|
|
|
#ifdef CONFIG_VERBOSE_MCHECK
|
|
|
|
|
|
if (alpha_verbose_mcheck > 1) {
|
|
|
|
|
|
printk("t2_machine_check(cpu%d): last_taken 0x%x - "
|
|
|
|
|
|
"unexpected mcheck - code 0x%x\n",
|
|
|
|
|
|
cpu, t2_mcheck_last_taken,
|
|
|
|
|
|
(unsigned int)mchk_header->code);
|
|
|
|
|
|
}
|
|
|
|
|
|
#endif
|
|
|
|
|
|
t2_mcheck_last_taken = 0;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
return;
|
|
|
|
|
|
} else {
|
|
|
|
|
|
t2_mcheck_last_taken = 0;
|
|
|
|
|
|
mb();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_VERBOSE_MCHECK
|
|
|
|
|
|
if (alpha_verbose_mcheck > 1) {
|
|
|
|
|
|
printk("%s t2_mcheck(cpu%d): last_taken 0x%x - "
|
|
|
|
|
|
"any_expected 0x%x - code 0x%x\n",
|
|
|
|
|
|
(mcheck_expected(cpu) ? "EX" : "UN"), cpu,
|
|
|
|
|
|
t2_mcheck_last_taken, t2_mcheck_any_expected,
|
|
|
|
|
|
(unsigned int)mchk_header->code);
|
|
|
|
|
|
}
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
2006-10-08 13:44:38 +00:00
|
|
|
|
process_mcheck_info(vector, la_ptr, "T2", mcheck_expected(cpu));
|
2005-04-16 22:20:36 +00:00
|
|
|
|
}
|