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118 lines
2.6 KiB
C
118 lines
2.6 KiB
C
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/*
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* ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
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*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <asm/mcip.h>
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static char smp_cpuinfo_buf[128];
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static DEFINE_RAW_SPINLOCK(mcip_lock);
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/*
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* Any SMP specific init any CPU does when it comes up.
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* Here we setup the CPU to enable Inter-Processor-Interrupts
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* Called for each CPU
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* -Master : init_IRQ()
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* -Other(s) : start_kernel_secondary()
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*/
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void mcip_init_smp(unsigned int cpu)
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{
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smp_ipi_irq_setup(cpu, IPI_IRQ);
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}
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static void mcip_ipi_send(int cpu)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void mcip_ipi_clear(int irq)
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{
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unsigned int cpu;
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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/* Who sent the IPI */
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__mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
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cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
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__mcip_cmd(CMD_INTRPT_GENERATE_ACK, __ffs(cpu)); /* 0,1,2,3... */
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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volatile int wake_flag;
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static void mcip_wakeup_cpu(int cpu, unsigned long pc)
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{
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BUG_ON(cpu == 0);
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wake_flag = cpu;
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}
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void arc_platform_smp_wait_to_boot(int cpu)
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{
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while (wake_flag != cpu)
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;
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wake_flag = 0;
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__asm__ __volatile__("j @first_lines_of_secondary \n");
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}
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struct plat_smp_ops plat_smp_ops = {
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.info = smp_cpuinfo_buf,
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.cpu_kick = mcip_wakeup_cpu,
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.ipi_send = mcip_ipi_send,
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.ipi_clear = mcip_ipi_clear,
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};
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void mcip_init_early_smp(void)
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{
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#define IS_AVAIL1(var, str) ((var) ? str : "")
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struct mcip_bcr {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:8,
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idu:1, llm:1, num_cores:6,
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iocoh:1, grtc:1, dbg:1, pad2:1,
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msg:1, sem:1, ipi:1, pad:1,
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ver:8;
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#else
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unsigned int ver:8,
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pad:1, ipi:1, sem:1, msg:1,
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pad2:1, dbg:1, grtc:1, iocoh:1,
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num_cores:6, llm:1, idu:1,
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pad3:8;
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#endif
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} mp;
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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sprintf(smp_cpuinfo_buf,
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"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
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mp.ver, mp.num_cores,
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IS_AVAIL1(mp.ipi, "IPI "),
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IS_AVAIL1(mp.idu, "IDU "),
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IS_AVAIL1(mp.dbg, "DEBUG "),
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IS_AVAIL1(mp.grtc, "GRTC"));
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if (mp.dbg) {
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__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
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__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
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}
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}
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