2011-06-14 07:13:24 +00:00
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/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
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#include <linux/interrupt.h>
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2011-08-26 06:10:50 +00:00
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#include <linux/debugfs.h>
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2011-08-26 06:11:06 +00:00
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#include <linux/bitops.h>
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#include <linux/gfp.h>
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iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
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2011-06-21 11:25:45 +00:00
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#include "iwl-dev.h"
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2011-06-14 07:13:24 +00:00
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#include "iwl-trans.h"
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2011-06-28 15:58:41 +00:00
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#include "iwl-core.h"
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#include "iwl-helpers.h"
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2011-07-11 14:35:34 +00:00
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#include "iwl-trans-int-pcie.h"
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2011-06-28 15:58:41 +00:00
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/*TODO remove uneeded includes when the transport layer tx_free will be here */
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#include "iwl-agn.h"
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2011-08-26 06:10:36 +00:00
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#include "iwl-shared.h"
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2011-06-14 07:13:24 +00:00
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2011-08-26 06:10:51 +00:00
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static int iwl_trans_rx_alloc(struct iwl_trans *trans)
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2011-06-14 07:13:24 +00:00
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{
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2011-08-26 06:10:51 +00:00
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_rx_queue *rxq = &trans_pcie->rxq;
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struct device *dev = bus(trans)->dev;
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2011-06-14 07:13:24 +00:00
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2011-08-26 06:10:51 +00:00
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memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
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2011-06-14 07:13:24 +00:00
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spin_lock_init(&rxq->lock);
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INIT_LIST_HEAD(&rxq->rx_free);
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INIT_LIST_HEAD(&rxq->rx_used);
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if (WARN_ON(rxq->bd || rxq->rb_stts))
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return -EINVAL;
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/* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
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2011-06-21 11:25:45 +00:00
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rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
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&rxq->bd_dma, GFP_KERNEL);
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2011-06-14 07:13:24 +00:00
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if (!rxq->bd)
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goto err_bd;
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2011-06-21 11:25:45 +00:00
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memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
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2011-06-14 07:13:24 +00:00
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/*Allocate the driver's pointer to receive buffer status */
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rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
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&rxq->rb_stts_dma, GFP_KERNEL);
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if (!rxq->rb_stts)
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goto err_rb_stts;
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memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
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return 0;
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err_rb_stts:
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2011-06-21 11:25:45 +00:00
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dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
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rxq->bd, rxq->bd_dma);
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2011-06-14 07:13:24 +00:00
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memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
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rxq->bd = NULL;
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err_bd:
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return -ENOMEM;
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}
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2011-08-26 06:10:51 +00:00
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static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
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2011-06-14 07:13:24 +00:00
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{
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2011-08-26 06:10:51 +00:00
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_rx_queue *rxq = &trans_pcie->rxq;
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2011-06-21 11:25:45 +00:00
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int i;
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2011-06-14 07:13:24 +00:00
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/* Fill the rx_used queue with _all_ of the Rx buffers */
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for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
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/* In the reset function, these buffers may have been allocated
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* to an SKB, so we need to unmap and free potential storage */
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if (rxq->pool[i].page != NULL) {
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2011-08-26 06:10:51 +00:00
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dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
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PAGE_SIZE << hw_params(trans).rx_page_order,
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2011-06-14 07:13:24 +00:00
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DMA_FROM_DEVICE);
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2011-08-26 06:11:05 +00:00
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__free_pages(rxq->pool[i].page,
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hw_params(trans).rx_page_order);
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2011-06-14 07:13:24 +00:00
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rxq->pool[i].page = NULL;
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}
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list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
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}
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2011-06-21 11:25:45 +00:00
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}
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2011-07-11 14:35:34 +00:00
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static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
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struct iwl_rx_queue *rxq)
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{
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u32 rb_size;
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const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
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2011-08-26 06:11:14 +00:00
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struct iwl_trans *trans = trans(priv);
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2011-07-11 14:35:34 +00:00
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rb_timeout = RX_RB_TIMEOUT;
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if (iwlagn_mod_params.amsdu_size_8K)
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
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else
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
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/* Stop Rx DMA */
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2011-08-26 06:11:14 +00:00
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iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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2011-07-11 14:35:34 +00:00
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/* Reset driver's Rx queue write index */
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2011-08-26 06:11:14 +00:00
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iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
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2011-07-11 14:35:34 +00:00
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/* Tell device where to find RBD circular buffer in DRAM */
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2011-08-26 06:11:14 +00:00
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iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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2011-07-11 14:35:34 +00:00
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(u32)(rxq->bd_dma >> 8));
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/* Tell device where in DRAM to update its Rx status */
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2011-08-26 06:11:14 +00:00
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iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
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2011-07-11 14:35:34 +00:00
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rxq->rb_stts_dma >> 4);
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/* Enable Rx DMA
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* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
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* the credit mechanism in 5000 HW RX FIFO
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* Direct rx interrupts to hosts
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* Rx buffer size 4 or 8k
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* RB timeout 0x10
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* 256 RBDs
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*/
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2011-08-26 06:11:14 +00:00
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iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
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2011-07-11 14:35:34 +00:00
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FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
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FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
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rb_size|
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(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
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(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
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/* Set interrupt coalescing timer to default (2048 usecs) */
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2011-08-26 06:11:14 +00:00
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iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
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2011-07-11 14:35:34 +00:00
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}
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2011-08-26 06:10:51 +00:00
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static int iwl_rx_init(struct iwl_trans *trans)
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2011-06-21 11:25:45 +00:00
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{
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2011-08-26 06:10:51 +00:00
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_rx_queue *rxq = &trans_pcie->rxq;
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2011-06-21 11:25:45 +00:00
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int i, err;
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unsigned long flags;
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if (!rxq->bd) {
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2011-08-26 06:10:51 +00:00
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err = iwl_trans_rx_alloc(trans);
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2011-06-21 11:25:45 +00:00
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if (err)
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return err;
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}
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spin_lock_irqsave(&rxq->lock, flags);
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INIT_LIST_HEAD(&rxq->rx_free);
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INIT_LIST_HEAD(&rxq->rx_used);
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2011-08-26 06:10:51 +00:00
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iwl_trans_rxq_free_rx_bufs(trans);
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2011-06-14 07:13:24 +00:00
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for (i = 0; i < RX_QUEUE_SIZE; i++)
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rxq->queue[i] = NULL;
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/* Set us so that we have processed and used all buffers, but have
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* not restocked the Rx queue with fresh buffers */
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rxq->read = rxq->write = 0;
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rxq->write_actual = 0;
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rxq->free_count = 0;
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spin_unlock_irqrestore(&rxq->lock, flags);
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2011-08-26 06:10:51 +00:00
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iwlagn_rx_replenish(trans);
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2011-07-11 14:35:34 +00:00
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2011-08-26 06:10:51 +00:00
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iwl_trans_rx_hw_init(priv(trans), rxq);
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2011-07-11 14:35:34 +00:00
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2011-08-26 06:10:51 +00:00
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spin_lock_irqsave(&trans->shrd->lock, flags);
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2011-07-11 14:35:34 +00:00
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rxq->need_update = 1;
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2011-08-26 06:10:51 +00:00
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iwl_rx_queue_update_write_ptr(trans, rxq);
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spin_unlock_irqrestore(&trans->shrd->lock, flags);
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2011-07-11 14:35:34 +00:00
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2011-06-14 07:13:24 +00:00
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return 0;
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}
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2011-08-26 06:10:51 +00:00
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static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
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2011-06-21 11:25:45 +00:00
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{
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2011-08-26 06:10:51 +00:00
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_rx_queue *rxq = &trans_pcie->rxq;
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2011-06-21 11:25:45 +00:00
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unsigned long flags;
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/*if rxq->bd is NULL, it means that nothing has been allocated,
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* exit now */
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if (!rxq->bd) {
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2011-08-26 06:10:51 +00:00
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IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
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2011-06-21 11:25:45 +00:00
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return;
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}
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spin_lock_irqsave(&rxq->lock, flags);
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2011-08-26 06:10:51 +00:00
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iwl_trans_rxq_free_rx_bufs(trans);
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2011-06-21 11:25:45 +00:00
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spin_unlock_irqrestore(&rxq->lock, flags);
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2011-08-26 06:10:51 +00:00
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dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
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2011-06-21 11:25:45 +00:00
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rxq->bd, rxq->bd_dma);
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memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
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rxq->bd = NULL;
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if (rxq->rb_stts)
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2011-08-26 06:10:51 +00:00
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dma_free_coherent(bus(trans)->dev,
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2011-06-21 11:25:45 +00:00
|
|
|
sizeof(struct iwl_rb_status),
|
|
|
|
rxq->rb_stts, rxq->rb_stts_dma);
|
|
|
|
else
|
2011-08-26 06:10:51 +00:00
|
|
|
IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
|
2011-06-21 11:25:45 +00:00
|
|
|
memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
|
|
|
|
rxq->rb_stts = NULL;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_trans_rx_stop(struct iwl_trans *trans)
|
2011-07-08 15:46:11 +00:00
|
|
|
{
|
|
|
|
|
|
|
|
/* stop Rx DMA */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
|
|
|
|
return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
|
2011-07-08 15:46:11 +00:00
|
|
|
FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
|
2011-06-28 15:58:41 +00:00
|
|
|
struct iwl_dma_ptr *ptr, size_t size)
|
|
|
|
{
|
|
|
|
if (WARN_ON(ptr->addr))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
|
2011-06-28 15:58:41 +00:00
|
|
|
&ptr->dma, GFP_KERNEL);
|
|
|
|
if (!ptr->addr)
|
|
|
|
return -ENOMEM;
|
|
|
|
ptr->size = size;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
|
2011-07-08 15:46:10 +00:00
|
|
|
struct iwl_dma_ptr *ptr)
|
|
|
|
{
|
|
|
|
if (unlikely(!ptr->addr))
|
|
|
|
return;
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
|
2011-07-08 15:46:10 +00:00
|
|
|
memset(ptr, 0, sizeof(*ptr));
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_trans_txq_alloc(struct iwl_trans *trans,
|
|
|
|
struct iwl_tx_queue *txq, int slots_num,
|
|
|
|
u32 txq_id)
|
2011-06-28 15:58:41 +00:00
|
|
|
{
|
2011-08-26 06:11:10 +00:00
|
|
|
size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
|
2011-06-28 15:58:41 +00:00
|
|
|
int i;
|
|
|
|
|
|
|
|
if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-07-08 15:46:10 +00:00
|
|
|
txq->q.n_window = slots_num;
|
|
|
|
|
2011-06-28 15:58:41 +00:00
|
|
|
txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
|
|
|
|
GFP_KERNEL);
|
|
|
|
txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!txq->meta || !txq->cmd)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
for (i = 0; i < slots_num; i++) {
|
|
|
|
txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!txq->cmd[i])
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Alloc driver data array and TFD circular buffer */
|
|
|
|
/* Driver private data, only for Tx (not command) queues,
|
|
|
|
* not shared with device. */
|
2011-08-26 06:11:06 +00:00
|
|
|
if (txq_id != trans->shrd->cmd_queue) {
|
2011-06-28 15:58:41 +00:00
|
|
|
txq->txb = kzalloc(sizeof(txq->txb[0]) *
|
|
|
|
TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
|
|
|
|
if (!txq->txb) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "kmalloc for auxiliary BD "
|
2011-06-28 15:58:41 +00:00
|
|
|
"structures failed\n");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
txq->txb = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Circular buffer of transmit frame descriptors (TFDs),
|
|
|
|
* shared with device */
|
2011-08-26 06:11:06 +00:00
|
|
|
txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
|
|
|
|
&txq->q.dma_addr, GFP_KERNEL);
|
2011-06-28 15:58:41 +00:00
|
|
|
if (!txq->tfds) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
|
2011-06-28 15:58:41 +00:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
txq->q.id = txq_id;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
error:
|
|
|
|
kfree(txq->txb);
|
|
|
|
txq->txb = NULL;
|
|
|
|
/* since txq->cmd has been zeroed,
|
|
|
|
* all non allocated cmd[i] will be NULL */
|
|
|
|
if (txq->cmd)
|
|
|
|
for (i = 0; i < slots_num; i++)
|
|
|
|
kfree(txq->cmd[i]);
|
|
|
|
kfree(txq->meta);
|
|
|
|
kfree(txq->cmd);
|
|
|
|
txq->meta = NULL;
|
|
|
|
txq->cmd = NULL;
|
|
|
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
|
2011-06-28 15:58:41 +00:00
|
|
|
int slots_num, u32 txq_id)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
txq->need_update = 0;
|
|
|
|
memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For the default queues 0-3, set up the swq_id
|
|
|
|
* already -- all others need to get one later
|
|
|
|
* (if they need one at all).
|
|
|
|
*/
|
|
|
|
if (txq_id < 4)
|
|
|
|
iwl_set_swq_id(txq, txq_id, txq_id);
|
|
|
|
|
|
|
|
/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
|
|
|
|
* iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
|
|
|
|
BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
|
|
|
|
|
|
|
|
/* Initialize queue's high/low-water marks, and head/tail indexes */
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
|
2011-06-28 15:58:41 +00:00
|
|
|
txq_id);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Tell nic where to find circular buffer of Tx Frame Descriptors for
|
|
|
|
* given Tx queue, and enable the DMA channel used for that queue.
|
|
|
|
* Circular buffer (TFD queue in DRAM) physical base address */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
|
2011-06-28 15:58:41 +00:00
|
|
|
txq->q.dma_addr >> 8);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-07-08 15:46:12 +00:00
|
|
|
/**
|
|
|
|
* iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
|
|
|
|
*/
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
|
2011-07-08 15:46:12 +00:00
|
|
|
{
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-07-08 15:46:12 +00:00
|
|
|
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
|
|
struct iwl_queue *q = &txq->q;
|
|
|
|
|
|
|
|
if (!q->n_bd)
|
|
|
|
return;
|
|
|
|
|
|
|
|
while (q->write_ptr != q->read_ptr) {
|
|
|
|
/* The read_ptr needs to bound by q->n_window */
|
2011-08-26 06:11:06 +00:00
|
|
|
iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr));
|
2011-07-08 15:46:12 +00:00
|
|
|
q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-08 15:46:10 +00:00
|
|
|
/**
|
|
|
|
* iwl_tx_queue_free - Deallocate DMA queue.
|
|
|
|
* @txq: Transmit queue to deallocate.
|
|
|
|
*
|
|
|
|
* Empty queue by removing and destroying all BD's.
|
|
|
|
* Free all buffers.
|
|
|
|
* 0-fill, but do not free "txq" descriptor structure.
|
|
|
|
*/
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
|
2011-07-08 15:46:10 +00:00
|
|
|
{
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-07-08 15:46:10 +00:00
|
|
|
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
2011-08-26 06:11:06 +00:00
|
|
|
struct device *dev = bus(trans)->dev;
|
2011-07-08 15:46:10 +00:00
|
|
|
int i;
|
|
|
|
if (WARN_ON(!txq))
|
|
|
|
return;
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_tx_queue_unmap(trans, txq_id);
|
2011-07-08 15:46:10 +00:00
|
|
|
|
|
|
|
/* De-alloc array of command/tx buffers */
|
|
|
|
for (i = 0; i < txq->q.n_window; i++)
|
|
|
|
kfree(txq->cmd[i]);
|
|
|
|
|
|
|
|
/* De-alloc circular buffer of TFDs */
|
|
|
|
if (txq->q.n_bd) {
|
2011-08-26 06:11:10 +00:00
|
|
|
dma_free_coherent(dev, sizeof(struct iwl_tfd) *
|
2011-07-08 15:46:10 +00:00
|
|
|
txq->q.n_bd, txq->tfds, txq->q.dma_addr);
|
|
|
|
memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* De-alloc array of per-TFD driver data */
|
|
|
|
kfree(txq->txb);
|
|
|
|
txq->txb = NULL;
|
|
|
|
|
|
|
|
/* deallocate arrays */
|
|
|
|
kfree(txq->cmd);
|
|
|
|
kfree(txq->meta);
|
|
|
|
txq->cmd = NULL;
|
|
|
|
txq->meta = NULL;
|
|
|
|
|
|
|
|
/* 0-fill queue descriptor structure */
|
|
|
|
memset(txq, 0, sizeof(*txq));
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* iwl_trans_tx_free - Free TXQ Context
|
|
|
|
*
|
|
|
|
* Destroy all TX DMA queues and structures
|
|
|
|
*/
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
|
2011-07-08 15:46:10 +00:00
|
|
|
{
|
|
|
|
int txq_id;
|
2011-08-26 06:11:02 +00:00
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-07-08 15:46:10 +00:00
|
|
|
|
|
|
|
/* Tx queues */
|
|
|
|
if (priv->txq) {
|
2011-08-26 06:10:39 +00:00
|
|
|
for (txq_id = 0;
|
2011-08-26 06:11:06 +00:00
|
|
|
txq_id < hw_params(trans).max_txq_num; txq_id++)
|
|
|
|
iwl_tx_queue_free(trans, txq_id);
|
2011-07-08 15:46:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
kfree(priv->txq);
|
|
|
|
priv->txq = NULL;
|
|
|
|
|
2011-08-26 06:11:12 +00:00
|
|
|
iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
|
2011-07-08 15:46:10 +00:00
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
|
2011-07-08 15:46:10 +00:00
|
|
|
}
|
|
|
|
|
2011-06-28 15:58:41 +00:00
|
|
|
/**
|
|
|
|
* iwl_trans_tx_alloc - allocate TX context
|
|
|
|
* Allocate all Tx DMA structures and initialize them
|
|
|
|
*
|
|
|
|
* @param priv
|
|
|
|
* @return error code
|
|
|
|
*/
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_trans_tx_alloc(struct iwl_trans *trans)
|
2011-06-28 15:58:41 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int txq_id, slots_num;
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-08-26 06:11:02 +00:00
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
2011-06-28 15:58:41 +00:00
|
|
|
|
2011-08-26 06:11:10 +00:00
|
|
|
u16 scd_bc_tbls_size = priv->cfg->base_params->num_of_queues *
|
|
|
|
sizeof(struct iwlagn_scd_bc_tbl);
|
|
|
|
|
2011-06-28 15:58:41 +00:00
|
|
|
/*It is not allowed to alloc twice, so warn when this happens.
|
|
|
|
* We cannot rely on the previous allocation, so free and fail */
|
|
|
|
if (WARN_ON(priv->txq)) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
|
2011-08-26 06:11:10 +00:00
|
|
|
scd_bc_tbls_size);
|
2011-06-28 15:58:41 +00:00
|
|
|
if (ret) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
|
2011-06-28 15:58:41 +00:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Alloc keep-warm buffer */
|
2011-08-26 06:11:12 +00:00
|
|
|
ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
|
2011-06-28 15:58:41 +00:00
|
|
|
if (ret) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "Keep Warm allocation failed\n");
|
2011-06-28 15:58:41 +00:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
|
|
|
|
priv->cfg->base_params->num_of_queues, GFP_KERNEL);
|
|
|
|
if (!priv->txq) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "Not enough memory for txq\n");
|
2011-06-28 15:58:41 +00:00
|
|
|
ret = ENOMEM;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
|
2011-08-26 06:11:06 +00:00
|
|
|
for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
|
|
|
|
slots_num = (txq_id == trans->shrd->cmd_queue) ?
|
2011-06-28 15:58:41 +00:00
|
|
|
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwl_trans_txq_alloc(trans, &priv->txq[txq_id], slots_num,
|
2011-06-28 15:58:41 +00:00
|
|
|
txq_id);
|
|
|
|
if (ret) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
|
2011-06-28 15:58:41 +00:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_tx_free(trans);
|
2011-06-28 15:58:41 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_tx_init(struct iwl_trans *trans)
|
2011-06-28 15:58:41 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int txq_id, slots_num;
|
|
|
|
unsigned long flags;
|
|
|
|
bool alloc = false;
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-08-26 06:11:12 +00:00
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
2011-06-28 15:58:41 +00:00
|
|
|
|
|
|
|
if (!priv->txq) {
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwl_trans_tx_alloc(trans);
|
2011-06-28 15:58:41 +00:00
|
|
|
if (ret)
|
|
|
|
goto error;
|
|
|
|
alloc = true;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
spin_lock_irqsave(&trans->shrd->lock, flags);
|
2011-06-28 15:58:41 +00:00
|
|
|
|
|
|
|
/* Turn off all Tx DMA fifos */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), SCD_TXFACT, 0);
|
2011-06-28 15:58:41 +00:00
|
|
|
|
|
|
|
/* Tell NIC where to find the "keep warm" buffer */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
|
|
|
|
trans_pcie->kw.dma >> 4);
|
2011-06-28 15:58:41 +00:00
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
spin_unlock_irqrestore(&trans->shrd->lock, flags);
|
2011-06-28 15:58:41 +00:00
|
|
|
|
|
|
|
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
|
2011-08-26 06:11:06 +00:00
|
|
|
for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
|
|
|
|
slots_num = (txq_id == trans->shrd->cmd_queue) ?
|
2011-06-28 15:58:41 +00:00
|
|
|
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwl_trans_txq_init(trans, &priv->txq[txq_id], slots_num,
|
2011-06-28 15:58:41 +00:00
|
|
|
txq_id);
|
|
|
|
if (ret) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
|
2011-06-28 15:58:41 +00:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
error:
|
|
|
|
/*Upon error, free only if we allocated something */
|
|
|
|
if (alloc)
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_tx_free(trans);
|
2011-06-28 15:58:41 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-07-10 12:30:15 +00:00
|
|
|
static void iwl_set_pwr_vmain(struct iwl_priv *priv)
|
|
|
|
{
|
2011-08-26 06:11:14 +00:00
|
|
|
struct iwl_trans *trans = trans(priv);
|
2011-07-10 12:30:15 +00:00
|
|
|
/*
|
|
|
|
* (for documentation purposes)
|
|
|
|
* to set power to V_AUX, do:
|
|
|
|
|
|
|
|
if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
|
2011-07-10 12:30:15 +00:00
|
|
|
APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
|
|
|
|
~APMG_PS_CTRL_MSK_PWR_SRC);
|
|
|
|
*/
|
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
|
2011-07-10 12:30:15 +00:00
|
|
|
APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
|
|
|
|
~APMG_PS_CTRL_MSK_PWR_SRC);
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_nic_init(struct iwl_trans *trans)
|
2011-07-10 12:30:15 +00:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
|
|
|
/* nic_init */
|
2011-08-26 06:11:06 +00:00
|
|
|
spin_lock_irqsave(&trans->shrd->lock, flags);
|
2011-07-10 12:30:15 +00:00
|
|
|
iwl_apm_init(priv);
|
|
|
|
|
|
|
|
/* Set interrupt coalescing calibration timer to default (512 usecs) */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write8(bus(trans), CSR_INT_COALESCING,
|
|
|
|
IWL_HOST_INT_CALIB_TIMEOUT_DEF);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
spin_unlock_irqrestore(&trans->shrd->lock, flags);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
|
|
|
iwl_set_pwr_vmain(priv);
|
|
|
|
|
|
|
|
priv->cfg->lib->nic_config(priv);
|
|
|
|
|
|
|
|
/* Allocate the RX queue, or reset if it is already allocated */
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_rx_init(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
|
|
|
/* Allocate or reset and init all Tx and Command queues */
|
2011-08-26 06:11:06 +00:00
|
|
|
if (iwl_tx_init(trans))
|
2011-07-10 12:30:15 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (priv->cfg->base_params->shadow_reg_enable) {
|
|
|
|
/* enable shadow regs in HW */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
|
2011-07-10 12:30:15 +00:00
|
|
|
0x800FFFFF);
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
set_bit(STATUS_INIT, &trans->shrd->status);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define HW_READY_TIMEOUT (50)
|
|
|
|
|
|
|
|
/* Note: returns poll_bit return value, which is >= 0 if success */
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_set_hw_ready(struct iwl_trans *trans)
|
2011-07-10 12:30:15 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
|
2011-07-10 12:30:15 +00:00
|
|
|
CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
|
|
|
|
|
|
|
|
/* See if we got it */
|
2011-08-26 06:11:14 +00:00
|
|
|
ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
|
2011-07-10 12:30:15 +00:00
|
|
|
CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
|
|
|
|
CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
|
|
|
|
HW_READY_TIMEOUT);
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
|
2011-07-10 12:30:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Note: returns standard 0/-ERROR code */
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
|
2011-07-10 12:30:15 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
|
2011-07-10 12:30:15 +00:00
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwl_set_hw_ready(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
if (ret >= 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* If HW is not ready, prepare the conditions to check again */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
|
2011-07-10 12:30:15 +00:00
|
|
|
CSR_HW_IF_CONFIG_REG_PREPARE);
|
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
|
2011-07-10 12:30:15 +00:00
|
|
|
~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
|
|
|
|
CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
|
|
|
|
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* HW should be ready by now, check again. */
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwl_set_hw_ready(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
if (ret >= 0)
|
|
|
|
return 0;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
|
2011-07-10 12:30:15 +00:00
|
|
|
{
|
|
|
|
int ret;
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
|
|
|
priv->ucode_owner = IWL_OWNERSHIP_DRIVER;
|
|
|
|
|
|
|
|
if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_pcie_prepare_card_hw(trans)) {
|
|
|
|
IWL_WARN(trans, "Exit HW not ready\n");
|
2011-07-10 12:30:15 +00:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If platform's RF_KILL switch is NOT set to KILL */
|
2011-08-26 06:11:14 +00:00
|
|
|
if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
|
2011-07-10 12:30:15 +00:00
|
|
|
CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
|
2011-08-26 06:11:06 +00:00
|
|
|
clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
|
2011-07-10 12:30:15 +00:00
|
|
|
else
|
2011-08-26 06:11:06 +00:00
|
|
|
set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
if (iwl_is_rfkill(trans->shrd)) {
|
2011-07-10 12:30:15 +00:00
|
|
|
wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_enable_interrupts(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
return -ERFKILL;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
ret = iwl_nic_init(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
if (ret) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "Unable to init nic\n");
|
2011-07-10 12:30:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* make sure rfkill handshake bits are cleared */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
|
|
|
|
iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
|
2011-07-10 12:30:15 +00:00
|
|
|
CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
|
|
|
|
|
|
|
|
/* clear (again), then enable host interrupts */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_enable_interrupts(trans);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
|
|
|
/* really make sure rfkill handshake bits are cleared */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
|
|
|
|
iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
|
2011-07-10 12:30:15 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-07-07 12:50:10 +00:00
|
|
|
/*
|
|
|
|
* Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
|
2011-08-26 06:10:43 +00:00
|
|
|
* must be called under priv->shrd->lock and mac access
|
2011-07-07 12:50:10 +00:00
|
|
|
*/
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
|
2011-07-07 12:50:10 +00:00
|
|
|
{
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), SCD_TXFACT, mask);
|
2011-07-07 12:50:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define IWL_AC_UNSET -1
|
|
|
|
|
|
|
|
struct queue_to_fifo_ac {
|
|
|
|
s8 fifo, ac;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
|
|
|
|
{ IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
|
|
|
|
{ IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
|
|
|
|
{ IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
|
|
|
|
{ IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
|
|
|
|
{ IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
|
|
|
|
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
|
|
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
|
|
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
|
|
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
|
|
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
2011-07-23 17:24:40 +00:00
|
|
|
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
2011-07-07 12:50:10 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
|
|
|
|
{ IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
|
|
|
|
{ IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
|
|
|
|
{ IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
|
|
|
|
{ IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
|
|
|
|
{ IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
|
|
|
|
{ IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
|
|
|
|
{ IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
|
|
|
|
{ IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
|
|
|
|
{ IWL_TX_FIFO_BE_IPAN, 2, },
|
|
|
|
{ IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
|
2011-07-23 17:24:40 +00:00
|
|
|
{ IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
|
2011-07-07 12:50:10 +00:00
|
|
|
};
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
|
2011-07-07 12:50:10 +00:00
|
|
|
{
|
|
|
|
const struct queue_to_fifo_ac *queue_to_fifo;
|
|
|
|
struct iwl_rxon_context *ctx;
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-08-26 06:11:02 +00:00
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
2011-07-07 12:50:10 +00:00
|
|
|
u32 a;
|
|
|
|
unsigned long flags;
|
|
|
|
int i, chan;
|
|
|
|
u32 reg_val;
|
|
|
|
|
2011-08-26 06:11:02 +00:00
|
|
|
spin_lock_irqsave(&trans->shrd->lock, flags);
|
2011-07-07 12:50:10 +00:00
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
trans_pcie->scd_base_addr =
|
|
|
|
iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
|
2011-08-26 06:11:02 +00:00
|
|
|
a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
|
2011-07-07 12:50:10 +00:00
|
|
|
/* reset conext data memory */
|
2011-08-26 06:11:02 +00:00
|
|
|
for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
|
2011-07-07 12:50:10 +00:00
|
|
|
a += 4)
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_targ_mem(bus(trans), a, 0);
|
2011-07-07 12:50:10 +00:00
|
|
|
/* reset tx status memory */
|
2011-08-26 06:11:02 +00:00
|
|
|
for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
|
2011-07-07 12:50:10 +00:00
|
|
|
a += 4)
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_targ_mem(bus(trans), a, 0);
|
2011-08-26 06:11:02 +00:00
|
|
|
for (; a < trans_pcie->scd_base_addr +
|
2011-08-26 06:10:39 +00:00
|
|
|
SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
|
|
|
|
a += 4)
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_targ_mem(bus(trans), a, 0);
|
2011-07-07 12:50:10 +00:00
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
|
2011-08-26 06:11:02 +00:00
|
|
|
trans_pcie->scd_bc_tbls.dma >> 10);
|
2011-07-07 12:50:10 +00:00
|
|
|
|
|
|
|
/* Enable DMA channel */
|
|
|
|
for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
|
2011-07-07 12:50:10 +00:00
|
|
|
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
|
|
|
|
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
|
|
|
|
|
|
|
|
/* Update FH chicken bits */
|
2011-08-26 06:11:14 +00:00
|
|
|
reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
|
|
|
|
iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
|
2011-07-07 12:50:10 +00:00
|
|
|
reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
|
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
|
2011-07-07 12:50:10 +00:00
|
|
|
SCD_QUEUECHAIN_SEL_ALL(priv));
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
|
2011-07-07 12:50:10 +00:00
|
|
|
|
|
|
|
/* initiate the queues */
|
2011-08-26 06:10:39 +00:00
|
|
|
for (i = 0; i < hw_params(priv).max_txq_num; i++) {
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
|
|
|
|
iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
|
|
|
|
iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
|
2011-07-07 12:50:10 +00:00
|
|
|
SCD_CONTEXT_QUEUE_OFFSET(i), 0);
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
|
2011-07-07 12:50:10 +00:00
|
|
|
SCD_CONTEXT_QUEUE_OFFSET(i) +
|
|
|
|
sizeof(u32),
|
|
|
|
((SCD_WIN_SIZE <<
|
|
|
|
SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
|
|
|
|
SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
|
|
|
|
((SCD_FRAME_LIMIT <<
|
|
|
|
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
|
|
|
|
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
|
2011-08-26 06:11:02 +00:00
|
|
|
IWL_MASK(0, hw_params(trans).max_txq_num));
|
2011-07-07 12:50:10 +00:00
|
|
|
|
|
|
|
/* Activate all Tx DMA/FIFO channels */
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
|
2011-07-07 12:50:10 +00:00
|
|
|
|
|
|
|
/* map queues to FIFOs */
|
|
|
|
if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
|
|
|
|
queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
|
|
|
|
else
|
|
|
|
queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
|
2011-07-07 12:50:10 +00:00
|
|
|
|
|
|
|
/* make sure all queue are not stopped */
|
|
|
|
memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
atomic_set(&priv->queue_stop_count[i], 0);
|
|
|
|
for_each_context(priv, ctx)
|
|
|
|
ctx->last_tx_rejected = false;
|
|
|
|
|
|
|
|
/* reset to 0 to enable all the queue first */
|
|
|
|
priv->txq_ctx_active_msk = 0;
|
|
|
|
|
2011-08-26 06:11:03 +00:00
|
|
|
BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
|
2011-07-23 17:24:40 +00:00
|
|
|
IWLAGN_FIRST_AMPDU_QUEUE);
|
2011-08-26 06:11:03 +00:00
|
|
|
BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
|
2011-07-23 17:24:40 +00:00
|
|
|
IWLAGN_FIRST_AMPDU_QUEUE);
|
2011-07-07 12:50:10 +00:00
|
|
|
|
2011-07-23 17:24:40 +00:00
|
|
|
for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
|
2011-07-07 12:50:10 +00:00
|
|
|
int fifo = queue_to_fifo[i].fifo;
|
|
|
|
int ac = queue_to_fifo[i].ac;
|
|
|
|
|
|
|
|
iwl_txq_ctx_activate(priv, i);
|
|
|
|
|
|
|
|
if (fifo == IWL_TX_FIFO_UNUSED)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (ac != IWL_AC_UNSET)
|
|
|
|
iwl_set_swq_id(&priv->txq[i], ac, i);
|
2011-07-10 07:47:01 +00:00
|
|
|
iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
|
2011-07-07 12:50:10 +00:00
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
spin_unlock_irqrestore(&trans->shrd->lock, flags);
|
2011-07-07 12:50:10 +00:00
|
|
|
|
|
|
|
/* Enable L1-Active */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
|
2011-07-07 12:50:10 +00:00
|
|
|
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
|
|
|
|
}
|
|
|
|
|
2011-07-08 15:46:12 +00:00
|
|
|
/**
|
|
|
|
* iwlagn_txq_ctx_stop - Stop all Tx DMA channels
|
|
|
|
*/
|
2011-08-26 06:11:06 +00:00
|
|
|
static int iwl_trans_tx_stop(struct iwl_trans *trans)
|
2011-07-08 15:46:12 +00:00
|
|
|
{
|
|
|
|
int ch, txq_id;
|
|
|
|
unsigned long flags;
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-07-08 15:46:12 +00:00
|
|
|
|
|
|
|
/* Turn off all Tx DMA fifos */
|
2011-08-26 06:11:06 +00:00
|
|
|
spin_lock_irqsave(&trans->shrd->lock, flags);
|
2011-07-08 15:46:12 +00:00
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_txq_set_sched(trans, 0);
|
2011-07-08 15:46:12 +00:00
|
|
|
|
|
|
|
/* Stop each Tx DMA channel, and wait for it to be idle */
|
2011-07-08 15:46:15 +00:00
|
|
|
for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_direct32(bus(trans),
|
2011-08-26 06:11:06 +00:00
|
|
|
FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
|
2011-08-26 06:11:14 +00:00
|
|
|
if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
|
2011-07-08 15:46:12 +00:00
|
|
|
FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
|
|
|
|
1000))
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_ERR(trans, "Failing on timeout while stopping"
|
2011-07-08 15:46:12 +00:00
|
|
|
" DMA channel %d [0x%08x]", ch,
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_read_direct32(bus(trans),
|
2011-08-26 06:11:06 +00:00
|
|
|
FH_TSSR_TX_STATUS_REG));
|
2011-07-08 15:46:12 +00:00
|
|
|
}
|
2011-08-26 06:11:06 +00:00
|
|
|
spin_unlock_irqrestore(&trans->shrd->lock, flags);
|
2011-07-08 15:46:12 +00:00
|
|
|
|
|
|
|
if (!priv->txq) {
|
2011-08-26 06:11:06 +00:00
|
|
|
IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
|
2011-07-08 15:46:12 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Unmap DMA from host system and free skb's */
|
2011-08-26 06:11:06 +00:00
|
|
|
for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
|
|
|
|
iwl_tx_queue_unmap(trans, txq_id);
|
2011-07-08 15:46:12 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
|
2011-07-07 11:37:26 +00:00
|
|
|
{
|
|
|
|
/* stop and reset the on-board processor */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
|
2011-07-07 11:37:26 +00:00
|
|
|
|
|
|
|
/* tell the device to stop sending interrupts */
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_disable_sync_irq(trans);
|
2011-07-07 11:37:26 +00:00
|
|
|
|
|
|
|
/* device going down, Stop using ICT table */
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_disable_ict(trans);
|
2011-07-07 11:37:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If a HW restart happens during firmware loading,
|
|
|
|
* then the firmware loading might call this function
|
|
|
|
* and later it might be called again due to the
|
|
|
|
* restart. So don't process again if the device is
|
|
|
|
* already dead.
|
|
|
|
*/
|
2011-08-26 06:11:06 +00:00
|
|
|
if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
|
|
|
|
iwl_trans_tx_stop(trans);
|
|
|
|
iwl_trans_rx_stop(trans);
|
2011-07-07 11:37:26 +00:00
|
|
|
|
|
|
|
/* Power-down device's busmaster DMA clocks */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
|
2011-07-07 11:37:26 +00:00
|
|
|
APMG_CLK_VAL_DMA_CLK_RQT);
|
|
|
|
udelay(5);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure (redundant) we've released our request to stay awake */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
|
2011-08-26 06:11:06 +00:00
|
|
|
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
2011-07-07 11:37:26 +00:00
|
|
|
|
|
|
|
/* Stop the device, and put it in low power state */
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_apm_stop(priv(trans));
|
2011-07-07 11:37:26 +00:00
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_trans *trans,
|
2011-07-03 08:22:15 +00:00
|
|
|
int txq_id)
|
|
|
|
{
|
2011-08-26 06:11:06 +00:00
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-07-03 08:22:15 +00:00
|
|
|
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
|
|
struct iwl_queue *q = &txq->q;
|
|
|
|
struct iwl_device_cmd *dev_cmd;
|
|
|
|
|
|
|
|
if (unlikely(iwl_queue_space(q) < q->high_mark))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up the Tx-command (not MAC!) header.
|
|
|
|
* Store the chosen Tx queue and TFD index within the sequence field;
|
|
|
|
* after Tx, uCode's Tx response will return this value so driver can
|
|
|
|
* locate the frame within the tx queue and do post-tx processing.
|
|
|
|
*/
|
|
|
|
dev_cmd = txq->cmd[q->write_ptr];
|
|
|
|
memset(dev_cmd, 0, sizeof(*dev_cmd));
|
|
|
|
dev_cmd->hdr.cmd = REPLY_TX;
|
|
|
|
dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
|
|
|
|
INDEX_TO_SEQ(q->write_ptr)));
|
|
|
|
return &dev_cmd->cmd.tx;
|
|
|
|
}
|
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
2011-07-03 08:22:15 +00:00
|
|
|
struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
|
|
|
|
struct iwl_rxon_context *ctx)
|
|
|
|
{
|
|
|
|
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
|
|
struct iwl_queue *q = &txq->q;
|
|
|
|
struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr];
|
|
|
|
struct iwl_cmd_meta *out_meta;
|
|
|
|
|
|
|
|
dma_addr_t phys_addr = 0;
|
|
|
|
dma_addr_t txcmd_phys;
|
|
|
|
dma_addr_t scratch_phys;
|
|
|
|
u16 len, firstlen, secondlen;
|
|
|
|
u8 wait_write_ptr = 0;
|
|
|
|
u8 hdr_len = ieee80211_hdrlen(fc);
|
|
|
|
|
|
|
|
/* Set up driver data for this TFD */
|
|
|
|
memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
|
|
|
|
txq->txb[q->write_ptr].skb = skb;
|
|
|
|
txq->txb[q->write_ptr].ctx = ctx;
|
|
|
|
|
|
|
|
/* Set up first empty entry in queue's array of Tx/cmd buffers */
|
|
|
|
out_meta = &txq->meta[q->write_ptr];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Use the first empty entry in this queue's command buffer array
|
|
|
|
* to contain the Tx command and MAC header concatenated together
|
|
|
|
* (payload data will be in another buffer).
|
|
|
|
* Size of this varies, due to varying MAC header length.
|
|
|
|
* If end is not dword aligned, we'll have 2 extra bytes at the end
|
|
|
|
* of the MAC header (device reads on dword boundaries).
|
|
|
|
* We'll tell device about this padding later.
|
|
|
|
*/
|
|
|
|
len = sizeof(struct iwl_tx_cmd) +
|
|
|
|
sizeof(struct iwl_cmd_header) + hdr_len;
|
|
|
|
firstlen = (len + 3) & ~3;
|
|
|
|
|
|
|
|
/* Tell NIC about any 2-byte padding after MAC header */
|
|
|
|
if (firstlen != len)
|
|
|
|
tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
|
|
|
|
|
|
|
|
/* Physical address of this Tx command's header (not MAC header!),
|
|
|
|
* within command buffer array. */
|
2011-07-11 07:48:51 +00:00
|
|
|
txcmd_phys = dma_map_single(priv->bus->dev,
|
2011-07-03 08:22:15 +00:00
|
|
|
&dev_cmd->hdr, firstlen,
|
|
|
|
DMA_BIDIRECTIONAL);
|
2011-07-11 07:48:51 +00:00
|
|
|
if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys)))
|
2011-07-03 08:22:15 +00:00
|
|
|
return -1;
|
|
|
|
dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
|
|
|
|
dma_unmap_len_set(out_meta, len, firstlen);
|
|
|
|
|
|
|
|
if (!ieee80211_has_morefrags(fc)) {
|
|
|
|
txq->need_update = 1;
|
|
|
|
} else {
|
|
|
|
wait_write_ptr = 1;
|
|
|
|
txq->need_update = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set up TFD's 2nd entry to point directly to remainder of skb,
|
|
|
|
* if any (802.11 null frames have no payload). */
|
|
|
|
secondlen = skb->len - hdr_len;
|
|
|
|
if (secondlen > 0) {
|
2011-07-11 07:48:51 +00:00
|
|
|
phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len,
|
2011-07-03 08:22:15 +00:00
|
|
|
secondlen, DMA_TO_DEVICE);
|
2011-07-11 07:48:51 +00:00
|
|
|
if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
|
|
|
|
dma_unmap_single(priv->bus->dev,
|
2011-07-03 08:22:15 +00:00
|
|
|
dma_unmap_addr(out_meta, mapping),
|
|
|
|
dma_unmap_len(out_meta, len),
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Attach buffers to TFD */
|
2011-08-26 06:11:06 +00:00
|
|
|
iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, txcmd_phys,
|
|
|
|
firstlen, 1);
|
2011-07-03 08:22:15 +00:00
|
|
|
if (secondlen > 0)
|
2011-08-26 06:11:06 +00:00
|
|
|
iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, phys_addr,
|
2011-07-03 08:22:15 +00:00
|
|
|
secondlen, 0);
|
|
|
|
|
|
|
|
scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
|
|
|
|
offsetof(struct iwl_tx_cmd, scratch);
|
|
|
|
|
|
|
|
/* take back ownership of DMA buffer to enable update */
|
2011-07-11 07:48:51 +00:00
|
|
|
dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen,
|
2011-07-03 08:22:15 +00:00
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
|
|
|
|
tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
|
|
|
|
|
|
|
|
IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
|
|
|
|
le16_to_cpu(dev_cmd->hdr.sequence));
|
|
|
|
IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
|
|
|
|
iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
|
|
|
|
iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
|
|
|
|
|
|
|
|
/* Set up entry for this TFD in Tx byte-count array */
|
|
|
|
if (ampdu)
|
2011-08-26 06:11:06 +00:00
|
|
|
iwl_trans_txq_update_byte_cnt_tbl(trans(priv), txq,
|
2011-07-03 08:22:15 +00:00
|
|
|
le16_to_cpu(tx_cmd->len));
|
|
|
|
|
2011-07-11 07:48:51 +00:00
|
|
|
dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
|
2011-07-03 08:22:15 +00:00
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
|
|
|
|
trace_iwlwifi_dev_tx(priv,
|
|
|
|
&((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
|
|
|
|
sizeof(struct iwl_tfd),
|
|
|
|
&dev_cmd->hdr, firstlen,
|
|
|
|
skb->data + hdr_len, secondlen);
|
|
|
|
|
|
|
|
/* Tell device the write index *just past* this latest filled TFD */
|
|
|
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
|
|
|
iwl_txq_update_write_ptr(priv, txq);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* At this point the frame is "transmitted" successfully
|
|
|
|
* and we will get a TX status notification eventually,
|
|
|
|
* regardless of the value of ret. "ret" only indicates
|
|
|
|
* whether or not we should update the write pointer.
|
|
|
|
*/
|
2011-08-26 06:11:00 +00:00
|
|
|
if (iwl_queue_space(q) < q->high_mark) {
|
2011-07-03 08:22:15 +00:00
|
|
|
if (wait_write_ptr) {
|
|
|
|
txq->need_update = 1;
|
|
|
|
iwl_txq_update_write_ptr(priv, txq);
|
|
|
|
} else {
|
|
|
|
iwl_stop_queue(priv, txq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
|
2011-07-07 15:20:01 +00:00
|
|
|
{
|
|
|
|
/* Remove all resets to allow NIC to operate */
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_write32(bus(trans), CSR_RESET, 0);
|
2011-07-07 15:20:01 +00:00
|
|
|
}
|
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
|
|
|
|
{
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
int err;
|
|
|
|
|
2011-08-26 06:10:53 +00:00
|
|
|
trans_pcie->inta_mask = CSR_INI_SET_MASK;
|
|
|
|
|
|
|
|
tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
|
|
|
|
iwl_irq_tasklet, (unsigned long)trans);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
|
2011-08-26 06:10:53 +00:00
|
|
|
iwl_alloc_isr_ict(trans);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
|
|
|
|
err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
|
2011-08-26 06:10:53 +00:00
|
|
|
DRV_NAME, trans);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
if (err) {
|
2011-08-26 06:10:53 +00:00
|
|
|
IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
|
|
|
|
iwl_free_isr_ict(trans);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:10:51 +00:00
|
|
|
INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:00 +00:00
|
|
|
static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id,
|
|
|
|
int ssn, u32 status, struct sk_buff_head *skbs)
|
|
|
|
{
|
|
|
|
struct iwl_priv *priv = priv(trans);
|
|
|
|
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
|
|
|
/* n_bd is usually 256 => n_bd - 1 = 0xff */
|
|
|
|
int tfd_num = ssn & (txq->q.n_bd - 1);
|
|
|
|
u8 agg_state;
|
|
|
|
bool cond;
|
|
|
|
|
|
|
|
if (txq->sched_retry) {
|
|
|
|
agg_state =
|
|
|
|
priv->stations[txq->sta_id].tid[txq->tid].agg.state;
|
|
|
|
cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
|
|
|
|
} else {
|
|
|
|
cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (txq->q.read_ptr != tfd_num) {
|
|
|
|
IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
|
|
|
|
"scd_ssn=%d idx=%d txq=%d swq=%d\n",
|
|
|
|
ssn , tfd_num, txq_id, txq->swq_id);
|
|
|
|
iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
|
|
|
|
if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
|
|
|
|
iwl_wake_queue(priv, txq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:10:53 +00:00
|
|
|
static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
|
2011-07-04 06:06:44 +00:00
|
|
|
{
|
2011-08-26 06:10:53 +00:00
|
|
|
unsigned long flags;
|
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&trans->shrd->lock, flags);
|
|
|
|
iwl_disable_interrupts(trans);
|
|
|
|
spin_unlock_irqrestore(&trans->shrd->lock, flags);
|
|
|
|
|
2011-07-04 06:06:44 +00:00
|
|
|
/* wait to make sure we flush pending tasklet*/
|
2011-08-26 06:10:53 +00:00
|
|
|
synchronize_irq(bus(trans)->irq);
|
|
|
|
tasklet_kill(&trans_pcie->irq_tasklet);
|
2011-07-04 06:06:44 +00:00
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:06 +00:00
|
|
|
static void iwl_trans_pcie_free(struct iwl_trans *trans)
|
2011-07-04 05:58:19 +00:00
|
|
|
{
|
2011-08-26 06:11:06 +00:00
|
|
|
free_irq(bus(trans)->irq, trans);
|
|
|
|
iwl_free_isr_ict(trans);
|
|
|
|
trans->shrd->trans = NULL;
|
|
|
|
kfree(trans);
|
2011-07-04 05:58:19 +00:00
|
|
|
}
|
|
|
|
|
2011-08-26 06:10:52 +00:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* This function is called when system goes into suspend state
|
|
|
|
* mac80211 will call iwl_mac_stop() from the mac80211 suspend function
|
|
|
|
* first but since iwl_mac_stop() has no knowledge of who the caller is,
|
|
|
|
* it will not call apm_ops.stop() to stop the DMA operation.
|
|
|
|
* Calling apm_ops.stop here to make sure we stop the DMA.
|
|
|
|
*
|
|
|
|
* But of course ... if we have configured WoWLAN then we did other
|
|
|
|
* things already :-)
|
|
|
|
*/
|
|
|
|
if (!trans->shrd->wowlan)
|
|
|
|
iwl_apm_stop(priv(trans));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int iwl_trans_pcie_resume(struct iwl_trans *trans)
|
|
|
|
{
|
|
|
|
bool hw_rfkill = false;
|
|
|
|
|
2011-08-26 06:10:53 +00:00
|
|
|
iwl_enable_interrupts(trans);
|
2011-08-26 06:10:52 +00:00
|
|
|
|
2011-08-26 06:11:14 +00:00
|
|
|
if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
|
2011-08-26 06:10:52 +00:00
|
|
|
CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
|
|
|
|
hw_rfkill = true;
|
|
|
|
|
|
|
|
if (hw_rfkill)
|
|
|
|
set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
|
|
|
|
else
|
|
|
|
clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
|
|
|
|
|
|
|
|
wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, hw_rfkill);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else /* CONFIG_PM */
|
|
|
|
static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
|
|
|
|
{ return 0; }
|
|
|
|
|
|
|
|
static int iwl_trans_pcie_resume(struct iwl_trans *trans)
|
|
|
|
{ return 0; }
|
|
|
|
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
const struct iwl_trans_ops trans_ops_pcie;
|
2011-07-08 15:46:14 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
|
|
|
|
{
|
|
|
|
struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
|
|
|
|
sizeof(struct iwl_trans_pcie),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (iwl_trans) {
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
iwl_trans->ops = &trans_ops_pcie;
|
|
|
|
iwl_trans->shrd = shrd;
|
2011-08-26 06:10:51 +00:00
|
|
|
trans_pcie->trans = iwl_trans;
|
2011-08-26 06:11:07 +00:00
|
|
|
spin_lock_init(&iwl_trans->hcmd_lock);
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
}
|
2011-07-07 11:37:26 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
return iwl_trans;
|
|
|
|
}
|
2011-07-03 08:22:15 +00:00
|
|
|
|
2011-08-26 06:10:50 +00:00
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
|
|
|
/* create and remove of files */
|
|
|
|
#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
|
2011-08-26 06:10:51 +00:00
|
|
|
if (!debugfs_create_file(#name, mode, parent, trans, \
|
2011-08-26 06:10:50 +00:00
|
|
|
&iwl_dbgfs_##name##_ops)) \
|
|
|
|
return -ENOMEM; \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
/* file operation */
|
|
|
|
#define DEBUGFS_READ_FUNC(name) \
|
|
|
|
static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
|
|
|
|
char __user *user_buf, \
|
|
|
|
size_t count, loff_t *ppos);
|
|
|
|
|
|
|
|
#define DEBUGFS_WRITE_FUNC(name) \
|
|
|
|
static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
|
|
|
|
const char __user *user_buf, \
|
|
|
|
size_t count, loff_t *ppos);
|
|
|
|
|
|
|
|
|
|
|
|
static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
file->private_data = inode->i_private;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DEBUGFS_READ_FILE_OPS(name) \
|
|
|
|
DEBUGFS_READ_FUNC(name); \
|
|
|
|
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
|
|
|
.read = iwl_dbgfs_##name##_read, \
|
|
|
|
.open = iwl_dbgfs_open_file_generic, \
|
|
|
|
.llseek = generic_file_llseek, \
|
|
|
|
};
|
|
|
|
|
2011-08-26 06:11:08 +00:00
|
|
|
#define DEBUGFS_WRITE_FILE_OPS(name) \
|
|
|
|
DEBUGFS_WRITE_FUNC(name); \
|
|
|
|
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
|
|
|
.write = iwl_dbgfs_##name##_write, \
|
|
|
|
.open = iwl_dbgfs_open_file_generic, \
|
|
|
|
.llseek = generic_file_llseek, \
|
|
|
|
};
|
|
|
|
|
2011-08-26 06:10:50 +00:00
|
|
|
#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
|
|
|
|
DEBUGFS_READ_FUNC(name); \
|
|
|
|
DEBUGFS_WRITE_FUNC(name); \
|
|
|
|
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
|
|
|
.write = iwl_dbgfs_##name##_write, \
|
|
|
|
.read = iwl_dbgfs_##name##_read, \
|
|
|
|
.open = iwl_dbgfs_open_file_generic, \
|
|
|
|
.llseek = generic_file_llseek, \
|
|
|
|
};
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
|
|
|
|
char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
{
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-08-26 06:10:50 +00:00
|
|
|
int pos = 0, ofs = 0;
|
|
|
|
int cnt = 0, entry;
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
2011-08-26 06:10:50 +00:00
|
|
|
struct iwl_tx_queue *txq;
|
|
|
|
struct iwl_queue *q;
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_rx_queue *rxq = &trans_pcie->rxq;
|
2011-08-26 06:10:50 +00:00
|
|
|
char *buf;
|
|
|
|
int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
|
|
|
|
(priv->cfg->base_params->num_of_queues * 32 * 8) + 400;
|
|
|
|
const u8 *ptr;
|
|
|
|
ssize_t ret;
|
|
|
|
|
|
|
|
if (!priv->txq) {
|
2011-08-26 06:10:51 +00:00
|
|
|
IWL_ERR(trans, "txq not ready\n");
|
2011-08-26 06:10:50 +00:00
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
buf = kzalloc(bufsz, GFP_KERNEL);
|
|
|
|
if (!buf) {
|
2011-08-26 06:10:51 +00:00
|
|
|
IWL_ERR(trans, "Can not allocate buffer\n");
|
2011-08-26 06:10:50 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n");
|
2011-08-26 06:10:51 +00:00
|
|
|
for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
|
2011-08-26 06:10:50 +00:00
|
|
|
txq = &priv->txq[cnt];
|
|
|
|
q = &txq->q;
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"q[%d]: read_ptr: %u, write_ptr: %u\n",
|
|
|
|
cnt, q->read_ptr, q->write_ptr);
|
|
|
|
}
|
|
|
|
if (priv->tx_traffic &&
|
2011-08-26 06:10:51 +00:00
|
|
|
(iwl_get_debug_level(trans->shrd) & IWL_DL_TX)) {
|
2011-08-26 06:10:50 +00:00
|
|
|
ptr = priv->tx_traffic;
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
2011-08-26 06:10:51 +00:00
|
|
|
"Tx Traffic idx: %u\n", priv->tx_traffic_idx);
|
2011-08-26 06:10:50 +00:00
|
|
|
for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
|
|
|
|
for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
|
|
|
|
entry++, ofs += 16) {
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"0x%.4x ", ofs);
|
|
|
|
hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
|
|
|
|
buf + pos, bufsz - pos, 0);
|
|
|
|
pos += strlen(buf + pos);
|
|
|
|
if (bufsz - pos > 0)
|
|
|
|
buf[pos++] = '\n';
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n");
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"read: %u, write: %u\n",
|
|
|
|
rxq->read, rxq->write);
|
|
|
|
|
|
|
|
if (priv->rx_traffic &&
|
2011-08-26 06:10:51 +00:00
|
|
|
(iwl_get_debug_level(trans->shrd) & IWL_DL_RX)) {
|
2011-08-26 06:10:50 +00:00
|
|
|
ptr = priv->rx_traffic;
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
2011-08-26 06:10:51 +00:00
|
|
|
"Rx Traffic idx: %u\n", priv->rx_traffic_idx);
|
2011-08-26 06:10:50 +00:00
|
|
|
for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
|
|
|
|
for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
|
|
|
|
entry++, ofs += 16) {
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"0x%.4x ", ofs);
|
|
|
|
hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
|
|
|
|
buf + pos, bufsz - pos, 0);
|
|
|
|
pos += strlen(buf + pos);
|
|
|
|
if (bufsz - pos > 0)
|
|
|
|
buf[pos++] = '\n';
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
|
|
|
kfree(buf);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_traffic_log_write(struct file *file,
|
|
|
|
const char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
{
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_trans *trans = file->private_data;
|
2011-08-26 06:10:50 +00:00
|
|
|
char buf[8];
|
|
|
|
int buf_size;
|
|
|
|
int traffic_log;
|
|
|
|
|
|
|
|
memset(buf, 0, sizeof(buf));
|
|
|
|
buf_size = min(count, sizeof(buf) - 1);
|
|
|
|
if (copy_from_user(buf, user_buf, buf_size))
|
|
|
|
return -EFAULT;
|
|
|
|
if (sscanf(buf, "%d", &traffic_log) != 1)
|
|
|
|
return -EFAULT;
|
|
|
|
if (traffic_log == 0)
|
2011-08-26 06:10:51 +00:00
|
|
|
iwl_reset_traffic_log(priv(trans));
|
2011-08-26 06:10:50 +00:00
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
|
|
|
|
char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos) {
|
|
|
|
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
struct iwl_priv *priv = priv(trans);
|
2011-08-26 06:10:50 +00:00
|
|
|
struct iwl_tx_queue *txq;
|
|
|
|
struct iwl_queue *q;
|
|
|
|
char *buf;
|
|
|
|
int pos = 0;
|
|
|
|
int cnt;
|
|
|
|
int ret;
|
|
|
|
const size_t bufsz = sizeof(char) * 64 *
|
|
|
|
priv->cfg->base_params->num_of_queues;
|
|
|
|
|
|
|
|
if (!priv->txq) {
|
|
|
|
IWL_ERR(priv, "txq not ready\n");
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
buf = kzalloc(bufsz, GFP_KERNEL);
|
|
|
|
if (!buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2011-08-26 06:10:51 +00:00
|
|
|
for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
|
2011-08-26 06:10:50 +00:00
|
|
|
txq = &priv->txq[cnt];
|
|
|
|
q = &txq->q;
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"hwq %.2d: read=%u write=%u stop=%d"
|
|
|
|
" swq_id=%#.2x (ac %d/hwq %d)\n",
|
|
|
|
cnt, q->read_ptr, q->write_ptr,
|
|
|
|
!!test_bit(cnt, priv->queue_stopped),
|
|
|
|
txq->swq_id, txq->swq_id & 3,
|
|
|
|
(txq->swq_id >> 2) & 0x1f);
|
|
|
|
if (cnt >= 4)
|
|
|
|
continue;
|
|
|
|
/* for the ACs, display the stop count too */
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
" stop-count: %d\n",
|
|
|
|
atomic_read(&priv->queue_stop_count[cnt]));
|
|
|
|
}
|
|
|
|
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
|
|
|
kfree(buf);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
|
|
|
|
char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos) {
|
2011-08-26 06:10:51 +00:00
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
struct iwl_rx_queue *rxq = &trans_pcie->rxq;
|
2011-08-26 06:10:50 +00:00
|
|
|
char buf[256];
|
|
|
|
int pos = 0;
|
|
|
|
const size_t bufsz = sizeof(buf);
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
|
|
|
|
rxq->read);
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
|
|
|
|
rxq->write);
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
|
|
|
|
rxq->free_count);
|
|
|
|
if (rxq->rb_stts) {
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
|
|
|
|
le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
|
|
|
|
} else {
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"closed_rb_num: Not Allocated\n");
|
|
|
|
}
|
|
|
|
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:10:54 +00:00
|
|
|
static ssize_t iwl_dbgfs_log_event_read(struct file *file,
|
|
|
|
char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
{
|
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
char *buf;
|
|
|
|
int pos = 0;
|
|
|
|
ssize_t ret = -ENOMEM;
|
|
|
|
|
2011-08-26 06:11:09 +00:00
|
|
|
ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
|
2011-08-26 06:10:54 +00:00
|
|
|
if (buf) {
|
|
|
|
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
|
|
|
kfree(buf);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_log_event_write(struct file *file,
|
|
|
|
const char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
{
|
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
u32 event_log_flag;
|
|
|
|
char buf[8];
|
|
|
|
int buf_size;
|
|
|
|
|
|
|
|
memset(buf, 0, sizeof(buf));
|
|
|
|
buf_size = min(count, sizeof(buf) - 1);
|
|
|
|
if (copy_from_user(buf, user_buf, buf_size))
|
|
|
|
return -EFAULT;
|
|
|
|
if (sscanf(buf, "%d", &event_log_flag) != 1)
|
|
|
|
return -EFAULT;
|
|
|
|
if (event_log_flag == 1)
|
2011-08-26 06:11:09 +00:00
|
|
|
iwl_dump_nic_event_log(trans, true, NULL, false);
|
2011-08-26 06:10:54 +00:00
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:10:59 +00:00
|
|
|
static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
|
|
|
|
char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos) {
|
|
|
|
|
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
|
|
|
|
|
|
|
|
int pos = 0;
|
|
|
|
char *buf;
|
|
|
|
int bufsz = 24 * 64; /* 24 items * 64 char per item */
|
|
|
|
ssize_t ret;
|
|
|
|
|
|
|
|
buf = kzalloc(bufsz, GFP_KERNEL);
|
|
|
|
if (!buf) {
|
|
|
|
IWL_ERR(trans, "Can not allocate Buffer\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"Interrupt Statistics Report:\n");
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
|
|
|
|
isr_stats->hw);
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
|
|
|
|
isr_stats->sw);
|
|
|
|
if (isr_stats->sw || isr_stats->hw) {
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"\tLast Restarting Code: 0x%X\n",
|
|
|
|
isr_stats->err_code);
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUG
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
|
|
|
|
isr_stats->sch);
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
|
|
|
|
isr_stats->alive);
|
|
|
|
#endif
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
|
|
|
|
isr_stats->ctkill);
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
|
|
|
|
isr_stats->wakeup);
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos,
|
|
|
|
"Rx command responses:\t\t %u\n", isr_stats->rx);
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
|
|
|
|
isr_stats->tx);
|
|
|
|
|
|
|
|
pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
|
|
|
|
isr_stats->unhandled);
|
|
|
|
|
|
|
|
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
|
|
|
kfree(buf);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
|
|
|
|
const char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
{
|
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
struct iwl_trans_pcie *trans_pcie =
|
|
|
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
|
|
|
|
|
|
|
|
char buf[8];
|
|
|
|
int buf_size;
|
|
|
|
u32 reset_flag;
|
|
|
|
|
|
|
|
memset(buf, 0, sizeof(buf));
|
|
|
|
buf_size = min(count, sizeof(buf) - 1);
|
|
|
|
if (copy_from_user(buf, user_buf, buf_size))
|
|
|
|
return -EFAULT;
|
|
|
|
if (sscanf(buf, "%x", &reset_flag) != 1)
|
|
|
|
return -EFAULT;
|
|
|
|
if (reset_flag == 0)
|
|
|
|
memset(isr_stats, 0, sizeof(*isr_stats));
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:11:08 +00:00
|
|
|
static const char *get_csr_string(int cmd)
|
|
|
|
{
|
|
|
|
switch (cmd) {
|
|
|
|
IWL_CMD(CSR_HW_IF_CONFIG_REG);
|
|
|
|
IWL_CMD(CSR_INT_COALESCING);
|
|
|
|
IWL_CMD(CSR_INT);
|
|
|
|
IWL_CMD(CSR_INT_MASK);
|
|
|
|
IWL_CMD(CSR_FH_INT_STATUS);
|
|
|
|
IWL_CMD(CSR_GPIO_IN);
|
|
|
|
IWL_CMD(CSR_RESET);
|
|
|
|
IWL_CMD(CSR_GP_CNTRL);
|
|
|
|
IWL_CMD(CSR_HW_REV);
|
|
|
|
IWL_CMD(CSR_EEPROM_REG);
|
|
|
|
IWL_CMD(CSR_EEPROM_GP);
|
|
|
|
IWL_CMD(CSR_OTP_GP_REG);
|
|
|
|
IWL_CMD(CSR_GIO_REG);
|
|
|
|
IWL_CMD(CSR_GP_UCODE_REG);
|
|
|
|
IWL_CMD(CSR_GP_DRIVER_REG);
|
|
|
|
IWL_CMD(CSR_UCODE_DRV_GP1);
|
|
|
|
IWL_CMD(CSR_UCODE_DRV_GP2);
|
|
|
|
IWL_CMD(CSR_LED_REG);
|
|
|
|
IWL_CMD(CSR_DRAM_INT_TBL_REG);
|
|
|
|
IWL_CMD(CSR_GIO_CHICKEN_BITS);
|
|
|
|
IWL_CMD(CSR_ANA_PLL_CFG);
|
|
|
|
IWL_CMD(CSR_HW_REV_WA_REG);
|
|
|
|
IWL_CMD(CSR_DBG_HPET_MEM_REG);
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void iwl_dump_csr(struct iwl_trans *trans)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
static const u32 csr_tbl[] = {
|
|
|
|
CSR_HW_IF_CONFIG_REG,
|
|
|
|
CSR_INT_COALESCING,
|
|
|
|
CSR_INT,
|
|
|
|
CSR_INT_MASK,
|
|
|
|
CSR_FH_INT_STATUS,
|
|
|
|
CSR_GPIO_IN,
|
|
|
|
CSR_RESET,
|
|
|
|
CSR_GP_CNTRL,
|
|
|
|
CSR_HW_REV,
|
|
|
|
CSR_EEPROM_REG,
|
|
|
|
CSR_EEPROM_GP,
|
|
|
|
CSR_OTP_GP_REG,
|
|
|
|
CSR_GIO_REG,
|
|
|
|
CSR_GP_UCODE_REG,
|
|
|
|
CSR_GP_DRIVER_REG,
|
|
|
|
CSR_UCODE_DRV_GP1,
|
|
|
|
CSR_UCODE_DRV_GP2,
|
|
|
|
CSR_LED_REG,
|
|
|
|
CSR_DRAM_INT_TBL_REG,
|
|
|
|
CSR_GIO_CHICKEN_BITS,
|
|
|
|
CSR_ANA_PLL_CFG,
|
|
|
|
CSR_HW_REV_WA_REG,
|
|
|
|
CSR_DBG_HPET_MEM_REG
|
|
|
|
};
|
|
|
|
IWL_ERR(trans, "CSR values:\n");
|
|
|
|
IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
|
|
|
|
"CSR_INT_PERIODIC_REG)\n");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
|
|
|
|
IWL_ERR(trans, " %25s: 0X%08x\n",
|
|
|
|
get_csr_string(csr_tbl[i]),
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_read32(bus(trans), csr_tbl[i]));
|
2011-08-26 06:11:08 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_csr_write(struct file *file,
|
|
|
|
const char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
{
|
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
char buf[8];
|
|
|
|
int buf_size;
|
|
|
|
int csr;
|
|
|
|
|
|
|
|
memset(buf, 0, sizeof(buf));
|
|
|
|
buf_size = min(count, sizeof(buf) - 1);
|
|
|
|
if (copy_from_user(buf, user_buf, buf_size))
|
|
|
|
return -EFAULT;
|
|
|
|
if (sscanf(buf, "%d", &csr) != 1)
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
iwl_dump_csr(trans);
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *get_fh_string(int cmd)
|
|
|
|
{
|
|
|
|
switch (cmd) {
|
|
|
|
IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
|
|
|
|
IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
|
|
|
|
IWL_CMD(FH_RSCSR_CHNL0_WPTR);
|
|
|
|
IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
|
|
|
|
IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
|
|
|
|
IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
|
|
|
|
IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
|
|
|
|
IWL_CMD(FH_TSSR_TX_STATUS_REG);
|
|
|
|
IWL_CMD(FH_TSSR_TX_ERROR_REG);
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUG
|
|
|
|
int pos = 0;
|
|
|
|
size_t bufsz = 0;
|
|
|
|
#endif
|
|
|
|
static const u32 fh_tbl[] = {
|
|
|
|
FH_RSCSR_CHNL0_STTS_WPTR_REG,
|
|
|
|
FH_RSCSR_CHNL0_RBDCB_BASE_REG,
|
|
|
|
FH_RSCSR_CHNL0_WPTR,
|
|
|
|
FH_MEM_RCSR_CHNL0_CONFIG_REG,
|
|
|
|
FH_MEM_RSSR_SHARED_CTRL_REG,
|
|
|
|
FH_MEM_RSSR_RX_STATUS_REG,
|
|
|
|
FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
|
|
|
|
FH_TSSR_TX_STATUS_REG,
|
|
|
|
FH_TSSR_TX_ERROR_REG
|
|
|
|
};
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUG
|
|
|
|
if (display) {
|
|
|
|
bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
|
|
|
|
*buf = kmalloc(bufsz, GFP_KERNEL);
|
|
|
|
if (!*buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
pos += scnprintf(*buf + pos, bufsz - pos,
|
|
|
|
"FH register values:\n");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
|
|
|
|
pos += scnprintf(*buf + pos, bufsz - pos,
|
|
|
|
" %34s: 0X%08x\n",
|
|
|
|
get_fh_string(fh_tbl[i]),
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_read_direct32(bus(trans), fh_tbl[i]));
|
2011-08-26 06:11:08 +00:00
|
|
|
}
|
|
|
|
return pos;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
IWL_ERR(trans, "FH register values:\n");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
|
|
|
|
IWL_ERR(trans, " %34s: 0X%08x\n",
|
|
|
|
get_fh_string(fh_tbl[i]),
|
2011-08-26 06:11:14 +00:00
|
|
|
iwl_read_direct32(bus(trans), fh_tbl[i]));
|
2011-08-26 06:11:08 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
|
|
|
|
char __user *user_buf,
|
|
|
|
size_t count, loff_t *ppos)
|
|
|
|
{
|
|
|
|
struct iwl_trans *trans = file->private_data;
|
|
|
|
char *buf;
|
|
|
|
int pos = 0;
|
|
|
|
ssize_t ret = -EFAULT;
|
|
|
|
|
|
|
|
ret = pos = iwl_dump_fh(trans, &buf, true);
|
|
|
|
if (buf) {
|
|
|
|
ret = simple_read_from_buffer(user_buf,
|
|
|
|
count, ppos, buf, pos);
|
|
|
|
kfree(buf);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-08-26 06:10:50 +00:00
|
|
|
DEBUGFS_READ_WRITE_FILE_OPS(traffic_log);
|
2011-08-26 06:10:54 +00:00
|
|
|
DEBUGFS_READ_WRITE_FILE_OPS(log_event);
|
2011-08-26 06:10:59 +00:00
|
|
|
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
|
2011-08-26 06:11:08 +00:00
|
|
|
DEBUGFS_READ_FILE_OPS(fh_reg);
|
2011-08-26 06:10:50 +00:00
|
|
|
DEBUGFS_READ_FILE_OPS(rx_queue);
|
|
|
|
DEBUGFS_READ_FILE_OPS(tx_queue);
|
2011-08-26 06:11:08 +00:00
|
|
|
DEBUGFS_WRITE_FILE_OPS(csr);
|
2011-08-26 06:10:50 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Create the debugfs files and directories
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
|
|
|
|
struct dentry *dir)
|
|
|
|
{
|
|
|
|
DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR);
|
|
|
|
DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
|
|
|
|
DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
|
2011-08-26 06:10:54 +00:00
|
|
|
DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
|
2011-08-26 06:10:59 +00:00
|
|
|
DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
|
2011-08-26 06:11:08 +00:00
|
|
|
DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
|
|
|
|
DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
|
2011-08-26 06:10:50 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
|
|
|
|
struct dentry *dir)
|
|
|
|
{ return 0; }
|
|
|
|
|
|
|
|
#endif /*CONFIG_IWLWIFI_DEBUGFS */
|
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
const struct iwl_trans_ops trans_ops_pcie = {
|
|
|
|
.alloc = iwl_trans_pcie_alloc,
|
|
|
|
.request_irq = iwl_trans_pcie_request_irq,
|
|
|
|
.start_device = iwl_trans_pcie_start_device,
|
|
|
|
.prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
|
|
|
|
.stop_device = iwl_trans_pcie_stop_device,
|
2011-07-10 07:47:01 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
.tx_start = iwl_trans_pcie_tx_start,
|
2011-07-10 07:47:01 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
.rx_free = iwl_trans_pcie_rx_free,
|
|
|
|
.tx_free = iwl_trans_pcie_tx_free,
|
2011-07-04 05:58:19 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
.send_cmd = iwl_trans_pcie_send_cmd,
|
|
|
|
.send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
|
2011-06-14 07:13:24 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
.get_tx_cmd = iwl_trans_pcie_get_tx_cmd,
|
|
|
|
.tx = iwl_trans_pcie_tx,
|
2011-08-26 06:11:00 +00:00
|
|
|
.reclaim = iwl_trans_pcie_reclaim,
|
2011-07-04 05:58:19 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
.txq_agg_disable = iwl_trans_pcie_txq_agg_disable,
|
|
|
|
.txq_agg_setup = iwl_trans_pcie_txq_agg_setup,
|
2011-07-04 05:58:19 +00:00
|
|
|
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
.kick_nic = iwl_trans_pcie_kick_nic,
|
2011-07-21 00:51:22 +00:00
|
|
|
|
2011-08-26 06:10:53 +00:00
|
|
|
.disable_sync_irq = iwl_trans_pcie_disable_sync_irq,
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
.free = iwl_trans_pcie_free,
|
2011-08-26 06:10:50 +00:00
|
|
|
|
|
|
|
.dbgfs_register = iwl_trans_pcie_dbgfs_register,
|
2011-08-26 06:10:52 +00:00
|
|
|
.suspend = iwl_trans_pcie_suspend,
|
|
|
|
.resume = iwl_trans_pcie_resume,
|
iwlagn: bus layer chooses its transport layer
Remove iwl_transport_register which was a W/A. The bus layer knows what
transport to use. So now, the bus layer gives the upper layer a pointer to the
iwl_trans_ops struct that it wants to use. The upper layer then, allocates the
desired transport layer using iwl_trans_ops->alloc function.
As a result of this, priv->trans, no longer exists, priv holds a pointer to
iwl_shared, which holds a pointer to iwl_trans. This required to change all the
calls to the transport layer from upper layer. While we were at it, trans_X
inlines have been renamed to iwl_trans_X to avoid confusions, which of course
required to rename the functions inside the transport layer because of
conflicts in names. So the static API functions inside the transport layer
implementation have been renamed to iwl_trans_pcie_X.
Until now, the IRQ / Tasklet were initialized in iwl_transport_layer. This is
confusing since the registration doesn't mean to request IRQ, so I added a
handler for that.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-08-26 06:10:48 +00:00
|
|
|
};
|
2011-07-11 14:35:34 +00:00
|
|
|
|