2019-06-04 08:11:33 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-08-17 07:15:26 +00:00
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/*
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* Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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2021-03-06 11:24:25 +00:00
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#include <linux/mailbox_client.h>
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2017-08-17 07:15:26 +00:00
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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2021-03-06 11:24:22 +00:00
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#include <linux/of_reserved_mem.h>
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2017-08-17 07:15:26 +00:00
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/remoteproc.h>
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2021-03-06 11:24:25 +00:00
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#include <linux/workqueue.h>
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#include "remoteproc_internal.h"
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2017-08-17 07:15:26 +00:00
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#define IMX7D_SRC_SCR 0x0C
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#define IMX7D_ENABLE_M4 BIT(3)
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#define IMX7D_SW_M4P_RST BIT(2)
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#define IMX7D_SW_M4C_RST BIT(1)
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#define IMX7D_SW_M4C_NON_SCLR_RST BIT(0)
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#define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
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| IMX7D_SW_M4C_RST \
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| IMX7D_SW_M4C_NON_SCLR_RST)
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#define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \
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| IMX7D_SW_M4C_RST)
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#define IMX7D_M4_STOP IMX7D_SW_M4C_NON_SCLR_RST
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/* Address: 0x020D8000 */
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#define IMX6SX_SRC_SCR 0x00
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#define IMX6SX_ENABLE_M4 BIT(22)
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#define IMX6SX_SW_M4P_RST BIT(12)
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#define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4)
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#define IMX6SX_SW_M4C_RST BIT(3)
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#define IMX6SX_M4_START (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
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| IMX6SX_SW_M4C_RST)
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#define IMX6SX_M4_STOP IMX6SX_SW_M4C_NON_SCLR_RST
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#define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \
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| IMX6SX_SW_M4C_NON_SCLR_RST \
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| IMX6SX_SW_M4C_RST)
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#define IMX7D_RPROC_MEM_MAX 8
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/**
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* struct imx_rproc_mem - slim internal memory structure
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* @cpu_addr: MPU virtual address of the memory region
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* @sys_addr: Bus address used to access the memory region
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* @size: Size of the memory region
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*/
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struct imx_rproc_mem {
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void __iomem *cpu_addr;
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phys_addr_t sys_addr;
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size_t size;
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};
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/* att flags */
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/* M4 own area. Can be mapped at probe */
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#define ATT_OWN BIT(1)
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/* address translation table */
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struct imx_rproc_att {
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u32 da; /* device address (From Cortex M4 view)*/
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u32 sa; /* system bus address */
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u32 size; /* size of reg range */
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int flags;
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};
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struct imx_rproc_dcfg {
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u32 src_reg;
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u32 src_mask;
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u32 src_start;
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u32 src_stop;
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const struct imx_rproc_att *att;
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size_t att_size;
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};
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struct imx_rproc {
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struct device *dev;
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struct regmap *regmap;
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struct rproc *rproc;
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const struct imx_rproc_dcfg *dcfg;
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struct imx_rproc_mem mem[IMX7D_RPROC_MEM_MAX];
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struct clk *clk;
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2021-03-06 11:24:25 +00:00
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struct mbox_client cl;
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struct mbox_chan *tx_ch;
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struct mbox_chan *rx_ch;
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struct work_struct rproc_work;
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struct workqueue_struct *workqueue;
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2017-08-17 07:15:26 +00:00
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};
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2021-03-06 11:24:23 +00:00
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static const struct imx_rproc_att imx_rproc_att_imx8mq[] = {
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/* dev addr , sys addr , size , flags */
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/* TCML - alias */
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{ 0x00000000, 0x007e0000, 0x00020000, 0 },
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/* OCRAM_S */
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{ 0x00180000, 0x00180000, 0x00008000, 0 },
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/* OCRAM */
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{ 0x00900000, 0x00900000, 0x00020000, 0 },
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/* OCRAM */
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{ 0x00920000, 0x00920000, 0x00020000, 0 },
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/* QSPI Code - alias */
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{ 0x08000000, 0x08000000, 0x08000000, 0 },
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/* DDR (Code) - alias */
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{ 0x10000000, 0x80000000, 0x0FFE0000, 0 },
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/* TCML */
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{ 0x1FFE0000, 0x007E0000, 0x00020000, ATT_OWN },
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/* TCMU */
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{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN },
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/* OCRAM_S */
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{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
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/* OCRAM */
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{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
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/* OCRAM */
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{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
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/* DDR (Data) */
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{ 0x40000000, 0x40000000, 0x80000000, 0 },
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};
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2017-08-17 07:15:26 +00:00
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static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
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/* dev addr , sys addr , size , flags */
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/* OCRAM_S (M4 Boot code) - alias */
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{ 0x00000000, 0x00180000, 0x00008000, 0 },
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/* OCRAM_S (Code) */
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{ 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
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/* OCRAM (Code) - alias */
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{ 0x00900000, 0x00900000, 0x00020000, 0 },
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/* OCRAM_EPDC (Code) - alias */
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{ 0x00920000, 0x00920000, 0x00020000, 0 },
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/* OCRAM_PXP (Code) - alias */
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{ 0x00940000, 0x00940000, 0x00008000, 0 },
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/* TCML (Code) */
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{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
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/* DDR (Code) - alias, first part of DDR (Data) */
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{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
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/* TCMU (Data) */
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{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
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/* OCRAM (Data) */
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{ 0x20200000, 0x00900000, 0x00020000, 0 },
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/* OCRAM_EPDC (Data) */
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{ 0x20220000, 0x00920000, 0x00020000, 0 },
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/* OCRAM_PXP (Data) */
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{ 0x20240000, 0x00940000, 0x00008000, 0 },
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/* DDR (Data) */
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{ 0x80000000, 0x80000000, 0x60000000, 0 },
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};
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static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
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/* dev addr , sys addr , size , flags */
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/* TCML (M4 Boot Code) - alias */
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{ 0x00000000, 0x007F8000, 0x00008000, 0 },
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/* OCRAM_S (Code) */
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{ 0x00180000, 0x008F8000, 0x00004000, 0 },
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/* OCRAM_S (Code) - alias */
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{ 0x00180000, 0x008FC000, 0x00004000, 0 },
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/* TCML (Code) */
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{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN },
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/* DDR (Code) - alias, first part of DDR (Data) */
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{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },
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/* TCMU (Data) */
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{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
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/* OCRAM_S (Data) - alias? */
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{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
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/* DDR (Data) */
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{ 0x80000000, 0x80000000, 0x60000000, 0 },
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};
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2021-03-06 11:24:23 +00:00
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static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = {
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.src_reg = IMX7D_SRC_SCR,
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.src_mask = IMX7D_M4_RST_MASK,
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.src_start = IMX7D_M4_START,
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.src_stop = IMX7D_M4_STOP,
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.att = imx_rproc_att_imx8mq,
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.att_size = ARRAY_SIZE(imx_rproc_att_imx8mq),
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};
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2017-08-17 07:15:26 +00:00
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static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = {
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.src_reg = IMX7D_SRC_SCR,
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.src_mask = IMX7D_M4_RST_MASK,
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.src_start = IMX7D_M4_START,
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.src_stop = IMX7D_M4_STOP,
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.att = imx_rproc_att_imx7d,
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.att_size = ARRAY_SIZE(imx_rproc_att_imx7d),
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};
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static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = {
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.src_reg = IMX6SX_SRC_SCR,
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.src_mask = IMX6SX_M4_RST_MASK,
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.src_start = IMX6SX_M4_START,
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.src_stop = IMX6SX_M4_STOP,
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.att = imx_rproc_att_imx6sx,
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.att_size = ARRAY_SIZE(imx_rproc_att_imx6sx),
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};
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static int imx_rproc_start(struct rproc *rproc)
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{
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struct imx_rproc *priv = rproc->priv;
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const struct imx_rproc_dcfg *dcfg = priv->dcfg;
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struct device *dev = priv->dev;
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int ret;
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ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
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dcfg->src_mask, dcfg->src_start);
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if (ret)
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2019-06-03 23:46:28 +00:00
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dev_err(dev, "Failed to enable M4!\n");
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2017-08-17 07:15:26 +00:00
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return ret;
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}
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static int imx_rproc_stop(struct rproc *rproc)
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{
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struct imx_rproc *priv = rproc->priv;
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const struct imx_rproc_dcfg *dcfg = priv->dcfg;
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struct device *dev = priv->dev;
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int ret;
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ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
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dcfg->src_mask, dcfg->src_stop);
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if (ret)
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2019-06-03 23:46:28 +00:00
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dev_err(dev, "Failed to stop M4!\n");
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2017-08-17 07:15:26 +00:00
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return ret;
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}
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static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
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2020-03-02 09:38:55 +00:00
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size_t len, u64 *sys)
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2017-08-17 07:15:26 +00:00
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{
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const struct imx_rproc_dcfg *dcfg = priv->dcfg;
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int i;
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/* parse address translation table */
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for (i = 0; i < dcfg->att_size; i++) {
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const struct imx_rproc_att *att = &dcfg->att[i];
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if (da >= att->da && da + len < att->da + att->size) {
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unsigned int offset = da - att->da;
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*sys = att->sa + offset;
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return 0;
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}
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}
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2020-03-02 09:38:55 +00:00
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dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",
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2017-08-17 07:15:26 +00:00
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da, len);
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return -ENOENT;
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}
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2021-03-06 11:24:19 +00:00
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static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
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2017-08-17 07:15:26 +00:00
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{
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struct imx_rproc *priv = rproc->priv;
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void *va = NULL;
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u64 sys;
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int i;
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2020-03-02 09:38:55 +00:00
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if (len == 0)
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2017-08-17 07:15:26 +00:00
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return NULL;
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/*
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* On device side we have many aliases, so we need to convert device
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* address (M4) to system bus address first.
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*/
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if (imx_rproc_da_to_sys(priv, da, len, &sys))
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return NULL;
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for (i = 0; i < IMX7D_RPROC_MEM_MAX; i++) {
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if (sys >= priv->mem[i].sys_addr && sys + len <
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priv->mem[i].sys_addr + priv->mem[i].size) {
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unsigned int offset = sys - priv->mem[i].sys_addr;
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/* __force to make sparse happy with type conversion */
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va = (__force void *)(priv->mem[i].cpu_addr + offset);
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break;
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}
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}
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2020-03-02 09:38:55 +00:00
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dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",
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da, len, va);
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2017-08-17 07:15:26 +00:00
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return va;
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}
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2021-03-06 11:24:22 +00:00
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static int imx_rproc_mem_alloc(struct rproc *rproc,
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struct rproc_mem_entry *mem)
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{
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struct device *dev = rproc->dev.parent;
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void *va;
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dev_dbg(dev, "map memory: %p+%zx\n", &mem->dma, mem->len);
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va = ioremap_wc(mem->dma, mem->len);
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if (IS_ERR_OR_NULL(va)) {
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dev_err(dev, "Unable to map memory region: %p+%zx\n",
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&mem->dma, mem->len);
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return -ENOMEM;
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}
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/* Update memory entry va */
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mem->va = va;
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return 0;
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}
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static int imx_rproc_mem_release(struct rproc *rproc,
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struct rproc_mem_entry *mem)
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{
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dev_dbg(rproc->dev.parent, "unmap memory: %pa\n", &mem->dma);
|
|
|
|
iounmap(mem->va);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_rproc_parse_memory_regions(struct rproc *rproc)
|
|
|
|
{
|
|
|
|
struct imx_rproc *priv = rproc->priv;
|
|
|
|
struct device_node *np = priv->dev->of_node;
|
|
|
|
struct of_phandle_iterator it;
|
|
|
|
struct rproc_mem_entry *mem;
|
|
|
|
struct reserved_mem *rmem;
|
|
|
|
u32 da;
|
|
|
|
|
|
|
|
/* Register associated reserved memory regions */
|
|
|
|
of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);
|
|
|
|
while (of_phandle_iterator_next(&it) == 0) {
|
|
|
|
/*
|
|
|
|
* Ignore the first memory region which will be used vdev buffer.
|
|
|
|
* No need to do extra handlings, rproc_add_virtio_dev will handle it.
|
|
|
|
*/
|
|
|
|
if (!strcmp(it.node->name, "vdev0buffer"))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
rmem = of_reserved_mem_lookup(it.node);
|
|
|
|
if (!rmem) {
|
|
|
|
dev_err(priv->dev, "unable to acquire memory-region\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No need to translate pa to da, i.MX use same map */
|
|
|
|
da = rmem->base;
|
|
|
|
|
|
|
|
/* Register memory region */
|
|
|
|
mem = rproc_mem_entry_init(priv->dev, NULL, (dma_addr_t)rmem->base, rmem->size, da,
|
|
|
|
imx_rproc_mem_alloc, imx_rproc_mem_release,
|
|
|
|
it.node->name);
|
|
|
|
|
|
|
|
if (mem)
|
|
|
|
rproc_coredump_add_segment(rproc, da, rmem->size);
|
|
|
|
else
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
rproc_add_carveout(rproc, mem);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
|
|
|
|
{
|
|
|
|
int ret = imx_rproc_parse_memory_regions(rproc);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = rproc_elf_load_rsc_table(rproc, fw);
|
|
|
|
if (ret)
|
|
|
|
dev_info(&rproc->dev, "No resource table in elf\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-03-06 11:24:25 +00:00
|
|
|
static void imx_rproc_kick(struct rproc *rproc, int vqid)
|
|
|
|
{
|
|
|
|
struct imx_rproc *priv = rproc->priv;
|
|
|
|
int err;
|
|
|
|
__u32 mmsg;
|
|
|
|
|
|
|
|
if (!priv->tx_ch) {
|
|
|
|
dev_err(priv->dev, "No initialized mbox tx channel\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Send the index of the triggered virtqueue as the mu payload.
|
|
|
|
* Let remote processor know which virtqueue is used.
|
|
|
|
*/
|
|
|
|
mmsg = vqid << 16;
|
|
|
|
|
|
|
|
err = mbox_send_message(priv->tx_ch, (void *)&mmsg);
|
|
|
|
if (err < 0)
|
|
|
|
dev_err(priv->dev, "%s: failed (%d, err:%d)\n",
|
|
|
|
__func__, vqid, err);
|
|
|
|
}
|
|
|
|
|
2017-08-17 07:15:26 +00:00
|
|
|
static const struct rproc_ops imx_rproc_ops = {
|
|
|
|
.start = imx_rproc_start,
|
|
|
|
.stop = imx_rproc_stop,
|
2021-03-06 11:24:25 +00:00
|
|
|
.kick = imx_rproc_kick,
|
2017-08-17 07:15:26 +00:00
|
|
|
.da_to_va = imx_rproc_da_to_va,
|
2021-03-06 11:24:22 +00:00
|
|
|
.load = rproc_elf_load_segments,
|
|
|
|
.parse_fw = imx_rproc_parse_fw,
|
|
|
|
.find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
|
|
|
|
.sanity_check = rproc_elf_sanity_check,
|
|
|
|
.get_boot_addr = rproc_elf_get_boot_addr,
|
2017-08-17 07:15:26 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int imx_rproc_addr_init(struct imx_rproc *priv,
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
const struct imx_rproc_dcfg *dcfg = priv->dcfg;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
int a, b = 0, err, nph;
|
|
|
|
|
|
|
|
/* remap required addresses */
|
|
|
|
for (a = 0; a < dcfg->att_size; a++) {
|
|
|
|
const struct imx_rproc_att *att = &dcfg->att[a];
|
|
|
|
|
|
|
|
if (!(att->flags & ATT_OWN))
|
|
|
|
continue;
|
|
|
|
|
2017-10-05 12:58:27 +00:00
|
|
|
if (b >= IMX7D_RPROC_MEM_MAX)
|
2017-08-17 07:15:26 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev,
|
|
|
|
att->sa, att->size);
|
2017-10-11 10:48:44 +00:00
|
|
|
if (!priv->mem[b].cpu_addr) {
|
2021-03-06 11:24:20 +00:00
|
|
|
dev_err(dev, "failed to remap %#x bytes from %#x\n", att->size, att->sa);
|
2017-10-11 10:48:44 +00:00
|
|
|
return -ENOMEM;
|
2017-08-17 07:15:26 +00:00
|
|
|
}
|
|
|
|
priv->mem[b].sys_addr = att->sa;
|
|
|
|
priv->mem[b].size = att->size;
|
|
|
|
b++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* memory-region is optional property */
|
|
|
|
nph = of_count_phandle_with_args(np, "memory-region", NULL);
|
|
|
|
if (nph <= 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* remap optional addresses */
|
|
|
|
for (a = 0; a < nph; a++) {
|
|
|
|
struct device_node *node;
|
|
|
|
struct resource res;
|
|
|
|
|
|
|
|
node = of_parse_phandle(np, "memory-region", a);
|
2021-03-06 11:24:24 +00:00
|
|
|
/* Not map vdev region */
|
|
|
|
if (!strcmp(node->name, "vdev"))
|
|
|
|
continue;
|
2017-08-17 07:15:26 +00:00
|
|
|
err = of_address_to_resource(node, 0, &res);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "unable to resolve memory region\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2017-10-05 12:58:27 +00:00
|
|
|
if (b >= IMX7D_RPROC_MEM_MAX)
|
2017-08-17 07:15:26 +00:00
|
|
|
break;
|
|
|
|
|
2021-03-06 11:24:21 +00:00
|
|
|
/* Not use resource version, because we might share region */
|
|
|
|
priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
|
2021-03-12 08:04:20 +00:00
|
|
|
if (!priv->mem[b].cpu_addr) {
|
2021-03-06 11:24:20 +00:00
|
|
|
dev_err(dev, "failed to remap %pr\n", &res);
|
2021-03-12 08:04:20 +00:00
|
|
|
return -ENOMEM;
|
2017-08-17 07:15:26 +00:00
|
|
|
}
|
|
|
|
priv->mem[b].sys_addr = res.start;
|
|
|
|
priv->mem[b].size = resource_size(&res);
|
|
|
|
b++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-03-06 11:24:25 +00:00
|
|
|
static void imx_rproc_vq_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct imx_rproc *priv = container_of(work, struct imx_rproc,
|
|
|
|
rproc_work);
|
|
|
|
|
|
|
|
rproc_vq_interrupt(priv->rproc, 0);
|
|
|
|
rproc_vq_interrupt(priv->rproc, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_rproc_rx_callback(struct mbox_client *cl, void *msg)
|
|
|
|
{
|
|
|
|
struct rproc *rproc = dev_get_drvdata(cl->dev);
|
|
|
|
struct imx_rproc *priv = rproc->priv;
|
|
|
|
|
|
|
|
queue_work(priv->workqueue, &priv->rproc_work);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_rproc_xtr_mbox_init(struct rproc *rproc)
|
|
|
|
{
|
|
|
|
struct imx_rproc *priv = rproc->priv;
|
|
|
|
struct device *dev = priv->dev;
|
|
|
|
struct mbox_client *cl;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!of_get_property(dev->of_node, "mbox-names", NULL))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cl = &priv->cl;
|
|
|
|
cl->dev = dev;
|
|
|
|
cl->tx_block = true;
|
|
|
|
cl->tx_tout = 100;
|
|
|
|
cl->knows_txdone = false;
|
|
|
|
cl->rx_callback = imx_rproc_rx_callback;
|
|
|
|
|
|
|
|
priv->tx_ch = mbox_request_channel_byname(cl, "tx");
|
|
|
|
if (IS_ERR(priv->tx_ch)) {
|
|
|
|
ret = PTR_ERR(priv->tx_ch);
|
|
|
|
return dev_err_probe(cl->dev, ret,
|
|
|
|
"failed to request tx mailbox channel: %d\n", ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->rx_ch = mbox_request_channel_byname(cl, "rx");
|
|
|
|
if (IS_ERR(priv->rx_ch)) {
|
|
|
|
mbox_free_channel(priv->tx_ch);
|
|
|
|
ret = PTR_ERR(priv->rx_ch);
|
|
|
|
return dev_err_probe(cl->dev, ret,
|
|
|
|
"failed to request rx mailbox channel: %d\n", ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_rproc_free_mbox(struct rproc *rproc)
|
|
|
|
{
|
|
|
|
struct imx_rproc *priv = rproc->priv;
|
|
|
|
|
|
|
|
mbox_free_channel(priv->tx_ch);
|
|
|
|
mbox_free_channel(priv->rx_ch);
|
|
|
|
}
|
|
|
|
|
2017-08-17 07:15:26 +00:00
|
|
|
static int imx_rproc_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
struct imx_rproc *priv;
|
|
|
|
struct rproc *rproc;
|
|
|
|
struct regmap_config config = { .name = "imx-rproc" };
|
|
|
|
const struct imx_rproc_dcfg *dcfg;
|
|
|
|
struct regmap *regmap;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
|
|
|
|
if (IS_ERR(regmap)) {
|
|
|
|
dev_err(dev, "failed to find syscon\n");
|
|
|
|
return PTR_ERR(regmap);
|
|
|
|
}
|
|
|
|
regmap_attach_dev(dev, regmap, &config);
|
|
|
|
|
|
|
|
/* set some other name then imx */
|
|
|
|
rproc = rproc_alloc(dev, "imx-rproc", &imx_rproc_ops,
|
|
|
|
NULL, sizeof(*priv));
|
2018-03-14 19:56:39 +00:00
|
|
|
if (!rproc)
|
|
|
|
return -ENOMEM;
|
2017-08-17 07:15:26 +00:00
|
|
|
|
|
|
|
dcfg = of_device_get_match_data(dev);
|
2018-03-14 19:56:37 +00:00
|
|
|
if (!dcfg) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_put_rproc;
|
|
|
|
}
|
2017-08-17 07:15:26 +00:00
|
|
|
|
|
|
|
priv = rproc->priv;
|
|
|
|
priv->rproc = rproc;
|
|
|
|
priv->regmap = regmap;
|
|
|
|
priv->dcfg = dcfg;
|
|
|
|
priv->dev = dev;
|
|
|
|
|
|
|
|
dev_set_drvdata(dev, rproc);
|
2021-03-06 11:24:25 +00:00
|
|
|
priv->workqueue = create_workqueue(dev_name(dev));
|
|
|
|
if (!priv->workqueue) {
|
|
|
|
dev_err(dev, "cannot create workqueue\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_put_rproc;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = imx_rproc_xtr_mbox_init(rproc);
|
|
|
|
if (ret)
|
|
|
|
goto err_put_wkq;
|
2017-08-17 07:15:26 +00:00
|
|
|
|
|
|
|
ret = imx_rproc_addr_init(priv, pdev);
|
|
|
|
if (ret) {
|
2019-06-03 23:46:28 +00:00
|
|
|
dev_err(dev, "failed on imx_rproc_addr_init\n");
|
2021-03-06 11:24:25 +00:00
|
|
|
goto err_put_mbox;
|
2017-08-17 07:15:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
|
|
if (IS_ERR(priv->clk)) {
|
|
|
|
dev_err(dev, "Failed to get clock\n");
|
2018-03-14 19:56:38 +00:00
|
|
|
ret = PTR_ERR(priv->clk);
|
2021-03-06 11:24:25 +00:00
|
|
|
goto err_put_mbox;
|
2017-08-17 07:15:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* clk for M4 block including memory. Should be
|
|
|
|
* enabled before .start for FW transfer.
|
|
|
|
*/
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&rproc->dev, "Failed to enable clock\n");
|
2021-03-06 11:24:25 +00:00
|
|
|
goto err_put_mbox;
|
2017-08-17 07:15:26 +00:00
|
|
|
}
|
|
|
|
|
2021-03-06 11:24:25 +00:00
|
|
|
INIT_WORK(&priv->rproc_work, imx_rproc_vq_work);
|
|
|
|
|
2017-08-17 07:15:26 +00:00
|
|
|
ret = rproc_add(rproc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "rproc_add failed\n");
|
|
|
|
goto err_put_clk;
|
|
|
|
}
|
|
|
|
|
2018-03-14 19:56:39 +00:00
|
|
|
return 0;
|
2017-08-17 07:15:26 +00:00
|
|
|
|
|
|
|
err_put_clk:
|
|
|
|
clk_disable_unprepare(priv->clk);
|
2021-03-06 11:24:25 +00:00
|
|
|
err_put_mbox:
|
|
|
|
imx_rproc_free_mbox(rproc);
|
|
|
|
err_put_wkq:
|
|
|
|
destroy_workqueue(priv->workqueue);
|
2017-08-17 07:15:26 +00:00
|
|
|
err_put_rproc:
|
|
|
|
rproc_free(rproc);
|
2018-03-14 19:56:39 +00:00
|
|
|
|
2017-08-17 07:15:26 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_rproc_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct rproc *rproc = platform_get_drvdata(pdev);
|
|
|
|
struct imx_rproc *priv = rproc->priv;
|
|
|
|
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
rproc_del(rproc);
|
2021-03-06 11:24:25 +00:00
|
|
|
imx_rproc_free_mbox(rproc);
|
2017-08-17 07:15:26 +00:00
|
|
|
rproc_free(rproc);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id imx_rproc_of_match[] = {
|
|
|
|
{ .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d },
|
|
|
|
{ .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx },
|
2021-03-06 11:24:23 +00:00
|
|
|
{ .compatible = "fsl,imx8mq-cm4", .data = &imx_rproc_cfg_imx8mq },
|
|
|
|
{ .compatible = "fsl,imx8mm-cm4", .data = &imx_rproc_cfg_imx8mq },
|
2017-08-17 07:15:26 +00:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, imx_rproc_of_match);
|
|
|
|
|
|
|
|
static struct platform_driver imx_rproc_driver = {
|
|
|
|
.probe = imx_rproc_probe,
|
|
|
|
.remove = imx_rproc_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "imx-rproc",
|
|
|
|
.of_match_table = imx_rproc_of_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(imx_rproc_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
2021-03-06 11:24:23 +00:00
|
|
|
MODULE_DESCRIPTION("i.MX remote processor control driver");
|
2017-08-17 07:15:26 +00:00
|
|
|
MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
|