2008-07-08 18:58:36 +00:00
|
|
|
/*
|
|
|
|
* offload engine driver for the Marvell XOR engine
|
|
|
|
* Copyright (C) 2007, 2008, Marvell International Ltd.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
* under the terms and conditions of the GNU General Public License,
|
|
|
|
* version 2, as published by the Free Software Foundation.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
* more details.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/init.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
|
|
|
#include <linux/slab.h>
|
2008-07-08 18:58:36 +00:00
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/dma-mapping.h>
|
|
|
|
#include <linux/spinlock.h>
|
|
|
|
#include <linux/interrupt.h>
|
2015-05-26 13:07:34 +00:00
|
|
|
#include <linux/of_device.h>
|
2008-07-08 18:58:36 +00:00
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/memory.h>
|
2012-02-19 12:30:26 +00:00
|
|
|
#include <linux/clk.h>
|
2012-11-15 15:47:58 +00:00
|
|
|
#include <linux/of.h>
|
|
|
|
#include <linux/of_irq.h>
|
|
|
|
#include <linux/irqdomain.h>
|
2015-07-08 14:28:19 +00:00
|
|
|
#include <linux/cpumask.h>
|
2012-08-24 13:21:54 +00:00
|
|
|
#include <linux/platform_data/dma-mv_xor.h>
|
2012-03-06 22:34:26 +00:00
|
|
|
|
|
|
|
#include "dmaengine.h"
|
2008-07-08 18:58:36 +00:00
|
|
|
#include "mv_xor.h"
|
|
|
|
|
2016-04-29 07:49:06 +00:00
|
|
|
enum mv_xor_type {
|
|
|
|
XOR_ORION,
|
|
|
|
XOR_ARMADA_38X,
|
2016-04-29 07:49:07 +00:00
|
|
|
XOR_ARMADA_37XX,
|
2016-04-29 07:49:06 +00:00
|
|
|
};
|
|
|
|
|
2015-05-26 13:07:34 +00:00
|
|
|
enum mv_xor_mode {
|
|
|
|
XOR_MODE_IN_REG,
|
|
|
|
XOR_MODE_IN_DESC,
|
|
|
|
};
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
static void mv_xor_issue_pending(struct dma_chan *chan);
|
|
|
|
|
|
|
|
#define to_mv_xor_chan(chan) \
|
2012-11-15 13:57:44 +00:00
|
|
|
container_of(chan, struct mv_xor_chan, dmachan)
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
#define to_mv_xor_slot(tx) \
|
|
|
|
container_of(tx, struct mv_xor_desc_slot, async_tx)
|
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
#define mv_chan_to_devp(chan) \
|
2012-11-15 14:17:05 +00:00
|
|
|
((chan)->dmadev.dev)
|
2012-11-15 13:17:18 +00:00
|
|
|
|
2014-08-27 13:52:51 +00:00
|
|
|
static void mv_desc_init(struct mv_xor_desc_slot *desc,
|
2014-08-27 13:52:53 +00:00
|
|
|
dma_addr_t addr, u32 byte_count,
|
|
|
|
enum dma_ctrl_flags flags)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
struct mv_xor_desc *hw_desc = desc->hw_desc;
|
|
|
|
|
2014-08-27 13:52:52 +00:00
|
|
|
hw_desc->status = XOR_DESC_DMA_OWNED;
|
2008-07-08 18:58:36 +00:00
|
|
|
hw_desc->phy_next_desc = 0;
|
2014-08-27 13:52:53 +00:00
|
|
|
/* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */
|
|
|
|
hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ?
|
|
|
|
XOR_DESC_EOD_INT_EN : 0;
|
2014-08-27 13:52:51 +00:00
|
|
|
hw_desc->phy_dest_addr = addr;
|
2008-07-08 18:58:36 +00:00
|
|
|
hw_desc->byte_count = byte_count;
|
|
|
|
}
|
|
|
|
|
2016-10-26 08:10:25 +00:00
|
|
|
/* Populate the descriptor */
|
|
|
|
static void mv_xor_config_sg_ll_desc(struct mv_xor_desc_slot *desc,
|
|
|
|
dma_addr_t dma_src, dma_addr_t dma_dst,
|
|
|
|
u32 len, struct mv_xor_desc_slot *prev)
|
|
|
|
{
|
|
|
|
struct mv_xor_desc *hw_desc = desc->hw_desc;
|
|
|
|
|
|
|
|
hw_desc->status = XOR_DESC_DMA_OWNED;
|
|
|
|
hw_desc->phy_next_desc = 0;
|
|
|
|
/* Configure for XOR with only one src address -> MEMCPY */
|
|
|
|
hw_desc->desc_command = XOR_DESC_OPERATION_XOR | (0x1 << 0);
|
|
|
|
hw_desc->phy_dest_addr = dma_dst;
|
|
|
|
hw_desc->phy_src_addr[0] = dma_src;
|
|
|
|
hw_desc->byte_count = len;
|
|
|
|
|
|
|
|
if (prev) {
|
|
|
|
struct mv_xor_desc *hw_prev = prev->hw_desc;
|
|
|
|
|
|
|
|
hw_prev->phy_next_desc = desc->async_tx.phys;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mv_xor_desc_config_eod(struct mv_xor_desc_slot *desc)
|
|
|
|
{
|
|
|
|
struct mv_xor_desc *hw_desc = desc->hw_desc;
|
|
|
|
|
|
|
|
/* Enable end-of-descriptor interrupt */
|
|
|
|
hw_desc->desc_command |= XOR_DESC_EOD_INT_EN;
|
|
|
|
}
|
|
|
|
|
2015-05-26 13:07:34 +00:00
|
|
|
static void mv_desc_set_mode(struct mv_xor_desc_slot *desc)
|
|
|
|
{
|
|
|
|
struct mv_xor_desc *hw_desc = desc->hw_desc;
|
|
|
|
|
|
|
|
switch (desc->type) {
|
|
|
|
case DMA_XOR:
|
|
|
|
case DMA_INTERRUPT:
|
|
|
|
hw_desc->desc_command |= XOR_DESC_OPERATION_XOR;
|
|
|
|
break;
|
|
|
|
case DMA_MEMCPY:
|
|
|
|
hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
|
|
|
|
u32 next_desc_addr)
|
|
|
|
{
|
|
|
|
struct mv_xor_desc *hw_desc = desc->hw_desc;
|
|
|
|
BUG_ON(hw_desc->phy_next_desc);
|
|
|
|
hw_desc->phy_next_desc = next_desc_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
|
|
|
|
int index, dma_addr_t addr)
|
|
|
|
{
|
|
|
|
struct mv_xor_desc *hw_desc = desc->hw_desc;
|
2013-07-29 15:42:14 +00:00
|
|
|
hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
|
2008-07-08 18:58:36 +00:00
|
|
|
if (desc->type == DMA_XOR)
|
|
|
|
hw_desc->desc_command |= (1 << index);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
|
|
|
|
{
|
2013-07-29 15:42:13 +00:00
|
|
|
return readl_relaxed(XOR_CURR_DESC(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
|
|
|
|
u32 next_desc_addr)
|
|
|
|
{
|
2013-07-29 15:42:13 +00:00
|
|
|
writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
|
|
|
|
{
|
2013-07-29 15:42:13 +00:00
|
|
|
u32 val = readl_relaxed(XOR_INTR_MASK(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
|
2013-07-29 15:42:13 +00:00
|
|
|
writel_relaxed(val, XOR_INTR_MASK(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
|
|
|
|
{
|
2013-07-29 15:42:13 +00:00
|
|
|
u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
|
|
|
|
return intr_cause;
|
|
|
|
}
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2014-08-27 13:52:53 +00:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED;
|
|
|
|
val = ~(val << (chan->idx * 16));
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
|
2013-07-29 15:42:13 +00:00
|
|
|
writel_relaxed(val, XOR_INTR_CAUSE(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
static void mv_chan_clear_err_status(struct mv_xor_chan *chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
u32 val = 0xFFFF0000 >> (chan->idx * 16);
|
2013-07-29 15:42:13 +00:00
|
|
|
writel_relaxed(val, XOR_INTR_CAUSE(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
static void mv_chan_set_mode(struct mv_xor_chan *chan,
|
2015-12-22 10:43:28 +00:00
|
|
|
u32 op_mode)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2013-07-29 15:42:13 +00:00
|
|
|
u32 config = readl_relaxed(XOR_CONFIG(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2015-05-26 13:07:34 +00:00
|
|
|
config &= ~0x7;
|
|
|
|
config |= op_mode;
|
|
|
|
|
2013-07-29 15:42:14 +00:00
|
|
|
#if defined(__BIG_ENDIAN)
|
|
|
|
config |= XOR_DESCRIPTOR_SWAP;
|
|
|
|
#else
|
|
|
|
config &= ~XOR_DESCRIPTOR_SWAP;
|
|
|
|
#endif
|
|
|
|
|
2013-07-29 15:42:13 +00:00
|
|
|
writel_relaxed(config, XOR_CONFIG(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mv_chan_activate(struct mv_xor_chan *chan)
|
|
|
|
{
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
|
2014-05-21 21:02:35 +00:00
|
|
|
|
|
|
|
/* writel ensures all descriptors are flushed before activation */
|
|
|
|
writel(BIT(0), XOR_ACTIVATION(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static char mv_chan_is_busy(struct mv_xor_chan *chan)
|
|
|
|
{
|
2013-07-29 15:42:13 +00:00
|
|
|
u32 state = readl_relaxed(XOR_ACTIVATION(chan));
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
state = (state >> 4) & 0x3;
|
|
|
|
|
|
|
|
return (state == 1) ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2015-05-26 13:07:33 +00:00
|
|
|
* mv_chan_start_new_chain - program the engine to operate on new
|
|
|
|
* chain headed by sw_desc
|
2008-07-08 18:58:36 +00:00
|
|
|
* Caller must hold &mv_chan->lock while calling this function
|
|
|
|
*/
|
2015-05-26 13:07:33 +00:00
|
|
|
static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
|
|
|
|
struct mv_xor_desc_slot *sw_desc)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
|
2008-07-08 18:58:36 +00:00
|
|
|
__func__, __LINE__, sw_desc);
|
|
|
|
|
2013-07-03 22:05:06 +00:00
|
|
|
/* set the hardware chain */
|
|
|
|
mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
|
|
|
|
|
2014-08-27 13:52:51 +00:00
|
|
|
mv_chan->pending++;
|
2012-11-15 13:57:44 +00:00
|
|
|
mv_xor_issue_pending(&mv_chan->dmachan);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static dma_cookie_t
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
|
|
|
|
struct mv_xor_chan *mv_chan,
|
|
|
|
dma_cookie_t cookie)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
BUG_ON(desc->async_tx.cookie < 0);
|
|
|
|
|
|
|
|
if (desc->async_tx.cookie > 0) {
|
|
|
|
cookie = desc->async_tx.cookie;
|
|
|
|
|
2016-07-25 17:34:08 +00:00
|
|
|
dma_descriptor_unmap(&desc->async_tx);
|
2008-07-08 18:58:36 +00:00
|
|
|
/* call the callback (must not sleep or submit new
|
|
|
|
* operations to this channel)
|
|
|
|
*/
|
2016-07-20 20:12:13 +00:00
|
|
|
dmaengine_desc_get_callback_invoke(&desc->async_tx, NULL);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* run dependent operations */
|
2009-01-06 00:14:31 +00:00
|
|
|
dma_run_dependencies(&desc->async_tx);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
return cookie;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
struct mv_xor_desc_slot *iter, *_iter;
|
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
|
2008-07-08 18:58:36 +00:00
|
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
|
2015-05-26 13:07:36 +00:00
|
|
|
node) {
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2016-10-26 08:10:25 +00:00
|
|
|
if (async_tx_test_ack(&iter->async_tx)) {
|
2015-05-26 13:07:36 +00:00
|
|
|
list_move_tail(&iter->node, &mv_chan->free_slots);
|
2016-10-26 08:10:25 +00:00
|
|
|
if (!list_empty(&iter->sg_tx_list)) {
|
|
|
|
list_splice_tail_init(&iter->sg_tx_list,
|
|
|
|
&mv_chan->free_slots);
|
|
|
|
}
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_desc_clean_slot(struct mv_xor_desc_slot *desc,
|
|
|
|
struct mv_xor_chan *mv_chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
|
2008-07-08 18:58:36 +00:00
|
|
|
__func__, __LINE__, desc, desc->async_tx.flags);
|
2015-05-26 13:07:36 +00:00
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
/* the client is allowed to attach dependent operations
|
|
|
|
* until 'ack' is set
|
|
|
|
*/
|
2016-10-26 08:10:25 +00:00
|
|
|
if (!async_tx_test_ack(&desc->async_tx)) {
|
2008-07-08 18:58:36 +00:00
|
|
|
/* move this slot to the completed_slots */
|
2015-05-26 13:07:36 +00:00
|
|
|
list_move_tail(&desc->node, &mv_chan->completed_slots);
|
2016-10-26 08:10:25 +00:00
|
|
|
if (!list_empty(&desc->sg_tx_list)) {
|
|
|
|
list_splice_tail_init(&desc->sg_tx_list,
|
|
|
|
&mv_chan->completed_slots);
|
|
|
|
}
|
|
|
|
} else {
|
2015-05-26 13:07:36 +00:00
|
|
|
list_move_tail(&desc->node, &mv_chan->free_slots);
|
2016-10-26 08:10:25 +00:00
|
|
|
if (!list_empty(&desc->sg_tx_list)) {
|
|
|
|
list_splice_tail_init(&desc->sg_tx_list,
|
|
|
|
&mv_chan->free_slots);
|
|
|
|
}
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-07 19:46:47 +00:00
|
|
|
/* This function must be called with the mv_xor_chan spinlock held */
|
2015-05-26 13:07:33 +00:00
|
|
|
static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
struct mv_xor_desc_slot *iter, *_iter;
|
|
|
|
dma_cookie_t cookie = 0;
|
|
|
|
int busy = mv_chan_is_busy(mv_chan);
|
|
|
|
u32 current_desc = mv_chan_get_current_desc(mv_chan);
|
2015-05-26 13:07:32 +00:00
|
|
|
int current_cleaned = 0;
|
|
|
|
struct mv_xor_desc *hw_desc;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
|
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_clean_completed_slots(mv_chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
/* free completed slots from the chain starting with
|
|
|
|
* the oldest descriptor
|
|
|
|
*/
|
|
|
|
|
|
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
|
2015-05-26 13:07:36 +00:00
|
|
|
node) {
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2015-05-26 13:07:32 +00:00
|
|
|
/* clean finished descriptors */
|
|
|
|
hw_desc = iter->hw_desc;
|
|
|
|
if (hw_desc->status & XOR_DESC_SUCCESS) {
|
2015-05-26 13:07:33 +00:00
|
|
|
cookie = mv_desc_run_tx_complete_actions(iter, mv_chan,
|
|
|
|
cookie);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2015-05-26 13:07:32 +00:00
|
|
|
/* done processing desc, clean slot */
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_desc_clean_slot(iter, mv_chan);
|
2015-05-26 13:07:32 +00:00
|
|
|
|
|
|
|
/* break if we did cleaned the current */
|
|
|
|
if (iter->async_tx.phys == current_desc) {
|
|
|
|
current_cleaned = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (iter->async_tx.phys == current_desc) {
|
|
|
|
current_cleaned = 0;
|
2008-07-08 18:58:36 +00:00
|
|
|
break;
|
2015-05-26 13:07:32 +00:00
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((busy == 0) && !list_empty(&mv_chan->chain)) {
|
2015-05-26 13:07:32 +00:00
|
|
|
if (current_cleaned) {
|
|
|
|
/*
|
|
|
|
* current descriptor cleaned and removed, run
|
|
|
|
* from list head
|
|
|
|
*/
|
|
|
|
iter = list_entry(mv_chan->chain.next,
|
|
|
|
struct mv_xor_desc_slot,
|
2015-05-26 13:07:36 +00:00
|
|
|
node);
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_start_new_chain(mv_chan, iter);
|
2015-05-26 13:07:32 +00:00
|
|
|
} else {
|
2015-05-26 13:07:36 +00:00
|
|
|
if (!list_is_last(&iter->node, &mv_chan->chain)) {
|
2015-05-26 13:07:32 +00:00
|
|
|
/*
|
|
|
|
* descriptors are still waiting after
|
|
|
|
* current, trigger them
|
|
|
|
*/
|
2015-05-26 13:07:36 +00:00
|
|
|
iter = list_entry(iter->node.next,
|
2015-05-26 13:07:32 +00:00
|
|
|
struct mv_xor_desc_slot,
|
2015-05-26 13:07:36 +00:00
|
|
|
node);
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_start_new_chain(mv_chan, iter);
|
2015-05-26 13:07:32 +00:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* some descriptors are still waiting
|
|
|
|
* to be cleaned
|
|
|
|
*/
|
|
|
|
tasklet_schedule(&mv_chan->irq_tasklet);
|
|
|
|
}
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cookie > 0)
|
2012-11-15 13:57:44 +00:00
|
|
|
mv_chan->dmachan.completed_cookie = cookie;
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mv_xor_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
|
2014-03-07 19:46:46 +00:00
|
|
|
|
|
|
|
spin_lock_bh(&chan->lock);
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_slot_cleanup(chan);
|
2014-03-07 19:46:46 +00:00
|
|
|
spin_unlock_bh(&chan->lock);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct mv_xor_desc_slot *
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_alloc_slot(struct mv_xor_chan *mv_chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2015-05-26 13:07:36 +00:00
|
|
|
struct mv_xor_desc_slot *iter;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2015-05-26 13:07:36 +00:00
|
|
|
spin_lock_bh(&mv_chan->lock);
|
|
|
|
|
|
|
|
if (!list_empty(&mv_chan->free_slots)) {
|
|
|
|
iter = list_first_entry(&mv_chan->free_slots,
|
|
|
|
struct mv_xor_desc_slot,
|
|
|
|
node);
|
|
|
|
|
|
|
|
list_move_tail(&iter->node, &mv_chan->allocated_slots);
|
|
|
|
|
|
|
|
spin_unlock_bh(&mv_chan->lock);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2014-08-27 13:52:51 +00:00
|
|
|
/* pre-ack descriptor */
|
|
|
|
async_tx_ack(&iter->async_tx);
|
|
|
|
iter->async_tx.cookie = -EBUSY;
|
|
|
|
|
|
|
|
return iter;
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
2015-05-26 13:07:36 +00:00
|
|
|
|
|
|
|
spin_unlock_bh(&mv_chan->lock);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
/* try to free some slots if the allocation fails */
|
|
|
|
tasklet_schedule(&mv_chan->irq_tasklet);
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************ DMA engine API functions ****************************/
|
|
|
|
static dma_cookie_t
|
|
|
|
mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
|
2014-08-27 13:52:51 +00:00
|
|
|
struct mv_xor_desc_slot *old_chain_tail;
|
2008-07-08 18:58:36 +00:00
|
|
|
dma_cookie_t cookie;
|
|
|
|
int new_hw_chain = 1;
|
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan),
|
2008-07-08 18:58:36 +00:00
|
|
|
"%s sw_desc %p: async_tx %p\n",
|
|
|
|
__func__, sw_desc, &sw_desc->async_tx);
|
|
|
|
|
|
|
|
spin_lock_bh(&mv_chan->lock);
|
2012-03-06 22:34:46 +00:00
|
|
|
cookie = dma_cookie_assign(tx);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
if (list_empty(&mv_chan->chain))
|
2015-05-26 13:07:36 +00:00
|
|
|
list_move_tail(&sw_desc->node, &mv_chan->chain);
|
2008-07-08 18:58:36 +00:00
|
|
|
else {
|
|
|
|
new_hw_chain = 0;
|
|
|
|
|
|
|
|
old_chain_tail = list_entry(mv_chan->chain.prev,
|
|
|
|
struct mv_xor_desc_slot,
|
2015-05-26 13:07:36 +00:00
|
|
|
node);
|
|
|
|
list_move_tail(&sw_desc->node, &mv_chan->chain);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2014-02-04 01:13:23 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
|
|
|
|
&old_chain_tail->async_tx.phys);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
/* fix up the hardware chain */
|
2014-08-27 13:52:51 +00:00
|
|
|
mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
/* if the channel is not busy */
|
|
|
|
if (!mv_chan_is_busy(mv_chan)) {
|
|
|
|
u32 current_desc = mv_chan_get_current_desc(mv_chan);
|
|
|
|
/*
|
|
|
|
* and the curren desc is the end of the chain before
|
|
|
|
* the append, then we need to start the channel
|
|
|
|
*/
|
|
|
|
if (current_desc == old_chain_tail->async_tx.phys)
|
|
|
|
new_hw_chain = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (new_hw_chain)
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_start_new_chain(mv_chan, sw_desc);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
spin_unlock_bh(&mv_chan->lock);
|
|
|
|
|
|
|
|
return cookie;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* returns the number of allocated descriptors */
|
2009-01-06 18:38:17 +00:00
|
|
|
static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2014-02-04 01:13:23 +00:00
|
|
|
void *virt_desc;
|
|
|
|
dma_addr_t dma_desc;
|
2008-07-08 18:58:36 +00:00
|
|
|
int idx;
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
|
|
struct mv_xor_desc_slot *slot = NULL;
|
2012-11-15 14:55:30 +00:00
|
|
|
int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
/* Allocate descriptor slots */
|
|
|
|
idx = mv_chan->slots_allocated;
|
|
|
|
while (idx < num_descs_in_pool) {
|
|
|
|
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
|
|
|
|
if (!slot) {
|
2014-08-27 13:52:49 +00:00
|
|
|
dev_info(mv_chan_to_devp(mv_chan),
|
|
|
|
"channel only initialized %d descriptor slots",
|
|
|
|
idx);
|
2008-07-08 18:58:36 +00:00
|
|
|
break;
|
|
|
|
}
|
2014-02-04 01:13:23 +00:00
|
|
|
virt_desc = mv_chan->dma_desc_pool_virt;
|
|
|
|
slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
dma_async_tx_descriptor_init(&slot->async_tx, chan);
|
|
|
|
slot->async_tx.tx_submit = mv_xor_tx_submit;
|
2015-05-26 13:07:36 +00:00
|
|
|
INIT_LIST_HEAD(&slot->node);
|
2016-10-26 08:10:25 +00:00
|
|
|
INIT_LIST_HEAD(&slot->sg_tx_list);
|
2014-02-04 01:13:23 +00:00
|
|
|
dma_desc = mv_chan->dma_desc_pool;
|
|
|
|
slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
|
2008-07-08 18:58:36 +00:00
|
|
|
slot->idx = idx++;
|
|
|
|
|
|
|
|
spin_lock_bh(&mv_chan->lock);
|
|
|
|
mv_chan->slots_allocated = idx;
|
2015-05-26 13:07:36 +00:00
|
|
|
list_add_tail(&slot->node, &mv_chan->free_slots);
|
2008-07-08 18:58:36 +00:00
|
|
|
spin_unlock_bh(&mv_chan->lock);
|
|
|
|
}
|
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan),
|
2015-05-26 13:07:36 +00:00
|
|
|
"allocated %d descriptor slots\n",
|
|
|
|
mv_chan->slots_allocated);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
return mv_chan->slots_allocated ? : -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2016-09-15 05:37:31 +00:00
|
|
|
/*
|
|
|
|
* Check if source or destination is an PCIe/IO address (non-SDRAM) and add
|
|
|
|
* a new MBus window if necessary. Use a cache for these check so that
|
|
|
|
* the MMIO mapped registers don't have to be accessed for this check
|
|
|
|
* to speed up this process.
|
|
|
|
*/
|
|
|
|
static int mv_xor_add_io_win(struct mv_xor_chan *mv_chan, u32 addr)
|
|
|
|
{
|
|
|
|
struct mv_xor_device *xordev = mv_chan->xordev;
|
|
|
|
void __iomem *base = mv_chan->mmr_high_base;
|
|
|
|
u32 win_enable;
|
|
|
|
u32 size;
|
|
|
|
u8 target, attr;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Nothing needs to get done for the Armada 3700 */
|
|
|
|
if (xordev->xor_type == XOR_ARMADA_37XX)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Loop over the cached windows to check, if the requested area
|
|
|
|
* is already mapped. If this the case, nothing needs to be done
|
|
|
|
* and we can return.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < WINDOW_COUNT; i++) {
|
|
|
|
if (addr >= xordev->win_start[i] &&
|
|
|
|
addr <= xordev->win_end[i]) {
|
|
|
|
/* Window is already mapped */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The window is not mapped, so we need to create the new mapping
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* If no IO window is found that addr has to be located in SDRAM */
|
|
|
|
ret = mvebu_mbus_get_io_win_info(addr, &size, &target, &attr);
|
|
|
|
if (ret < 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Mask the base addr 'addr' according to 'size' read back from the
|
|
|
|
* MBus window. Otherwise we might end up with an address located
|
|
|
|
* somewhere in the middle of this area here.
|
|
|
|
*/
|
|
|
|
size -= 1;
|
|
|
|
addr &= ~size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reading one of both enabled register is enough, as they are always
|
|
|
|
* programmed to the identical values
|
|
|
|
*/
|
|
|
|
win_enable = readl(base + WINDOW_BAR_ENABLE(0));
|
|
|
|
|
|
|
|
/* Set 'i' to the first free window to write the new values to */
|
|
|
|
i = ffs(~win_enable) - 1;
|
|
|
|
if (i >= WINDOW_COUNT)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
writel((addr & 0xffff0000) | (attr << 8) | target,
|
|
|
|
base + WINDOW_BASE(i));
|
|
|
|
writel(size & 0xffff0000, base + WINDOW_SIZE(i));
|
|
|
|
|
|
|
|
/* Fill the caching variables for later use */
|
|
|
|
xordev->win_start[i] = addr;
|
|
|
|
xordev->win_end[i] = addr + size;
|
|
|
|
|
|
|
|
win_enable |= (1 << i);
|
|
|
|
win_enable |= 3 << (16 + (2 * i));
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
static struct dma_async_tx_descriptor *
|
|
|
|
mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
|
|
|
|
unsigned int src_cnt, size_t len, unsigned long flags)
|
|
|
|
{
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
2014-08-27 13:52:51 +00:00
|
|
|
struct mv_xor_desc_slot *sw_desc;
|
2016-09-15 05:37:31 +00:00
|
|
|
int ret;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
|
|
|
|
return NULL;
|
|
|
|
|
2011-03-26 17:26:53 +00:00
|
|
|
BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan),
|
2016-04-29 07:49:05 +00:00
|
|
|
"%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
|
2014-02-04 01:13:23 +00:00
|
|
|
__func__, src_cnt, len, &dest, flags);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2016-09-15 05:37:31 +00:00
|
|
|
/* Check if a new window needs to get added for 'dest' */
|
|
|
|
ret = mv_xor_add_io_win(mv_chan, dest);
|
|
|
|
if (ret)
|
|
|
|
return NULL;
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
sw_desc = mv_chan_alloc_slot(mv_chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
if (sw_desc) {
|
|
|
|
sw_desc->type = DMA_XOR;
|
|
|
|
sw_desc->async_tx.flags = flags;
|
2014-08-27 13:52:53 +00:00
|
|
|
mv_desc_init(sw_desc, dest, len, flags);
|
2015-05-26 13:07:34 +00:00
|
|
|
if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
|
|
|
|
mv_desc_set_mode(sw_desc);
|
2016-09-15 05:37:31 +00:00
|
|
|
while (src_cnt--) {
|
|
|
|
/* Check if a new window needs to get added for 'src' */
|
|
|
|
ret = mv_xor_add_io_win(mv_chan, src[src_cnt]);
|
|
|
|
if (ret)
|
|
|
|
return NULL;
|
2014-08-27 13:52:51 +00:00
|
|
|
mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]);
|
2016-09-15 05:37:31 +00:00
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
2015-05-26 13:07:36 +00:00
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan),
|
2008-07-08 18:58:36 +00:00
|
|
|
"%s sw_desc %p async_tx %p \n",
|
|
|
|
__func__, sw_desc, &sw_desc->async_tx);
|
|
|
|
return sw_desc ? &sw_desc->async_tx : NULL;
|
|
|
|
}
|
|
|
|
|
2014-08-27 13:52:50 +00:00
|
|
|
static struct dma_async_tx_descriptor *
|
|
|
|
mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
|
|
|
size_t len, unsigned long flags)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* A MEMCPY operation is identical to an XOR operation with only
|
|
|
|
* a single source address.
|
|
|
|
*/
|
|
|
|
return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
|
|
|
|
}
|
|
|
|
|
2014-08-27 13:52:55 +00:00
|
|
|
static struct dma_async_tx_descriptor *
|
|
|
|
mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
|
|
|
|
{
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
|
|
dma_addr_t src, dest;
|
|
|
|
size_t len;
|
|
|
|
|
|
|
|
src = mv_chan->dummy_src_addr;
|
|
|
|
dest = mv_chan->dummy_dst_addr;
|
|
|
|
len = MV_XOR_MIN_BYTE_COUNT;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We implement the DMA_INTERRUPT operation as a minimum sized
|
|
|
|
* XOR operation with a single dummy source address.
|
|
|
|
*/
|
|
|
|
return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
|
|
|
|
}
|
|
|
|
|
2016-10-26 08:10:25 +00:00
|
|
|
/**
|
|
|
|
* mv_xor_prep_dma_sg - prepare descriptors for a memory sg transaction
|
|
|
|
* @chan: DMA channel
|
|
|
|
* @dst_sg: Destination scatter list
|
|
|
|
* @dst_sg_len: Number of entries in destination scatter list
|
|
|
|
* @src_sg: Source scatter list
|
|
|
|
* @src_sg_len: Number of entries in source scatter list
|
|
|
|
* @flags: transfer ack flags
|
|
|
|
*
|
|
|
|
* Return: Async transaction descriptor on success and NULL on failure
|
|
|
|
*/
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
|
|
mv_xor_prep_dma_sg(struct dma_chan *chan, struct scatterlist *dst_sg,
|
|
|
|
unsigned int dst_sg_len, struct scatterlist *src_sg,
|
|
|
|
unsigned int src_sg_len, unsigned long flags)
|
|
|
|
{
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
|
|
struct mv_xor_desc_slot *new;
|
|
|
|
struct mv_xor_desc_slot *first = NULL;
|
|
|
|
struct mv_xor_desc_slot *prev = NULL;
|
|
|
|
size_t len, dst_avail, src_avail;
|
|
|
|
dma_addr_t dma_dst, dma_src;
|
|
|
|
int desc_cnt = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan),
|
|
|
|
"%s dst_sg_len: %d src_sg_len: %d flags: %ld\n",
|
|
|
|
__func__, dst_sg_len, src_sg_len, flags);
|
|
|
|
|
|
|
|
dst_avail = sg_dma_len(dst_sg);
|
|
|
|
src_avail = sg_dma_len(src_sg);
|
|
|
|
|
|
|
|
/* Run until we are out of scatterlist entries */
|
|
|
|
while (true) {
|
|
|
|
/* Allocate and populate the descriptor */
|
|
|
|
desc_cnt++;
|
|
|
|
new = mv_chan_alloc_slot(mv_chan);
|
|
|
|
if (!new) {
|
|
|
|
dev_err(mv_chan_to_devp(mv_chan),
|
|
|
|
"Out of descriptors (desc_cnt=%d)!\n",
|
|
|
|
desc_cnt);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
len = min_t(size_t, src_avail, dst_avail);
|
|
|
|
len = min_t(size_t, len, MV_XOR_MAX_BYTE_COUNT);
|
|
|
|
if (len == 0)
|
|
|
|
goto fetch;
|
|
|
|
|
|
|
|
if (len < MV_XOR_MIN_BYTE_COUNT) {
|
|
|
|
dev_err(mv_chan_to_devp(mv_chan),
|
|
|
|
"Transfer size of %zu too small!\n", len);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
dma_dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) -
|
|
|
|
dst_avail;
|
|
|
|
dma_src = sg_dma_address(src_sg) + sg_dma_len(src_sg) -
|
|
|
|
src_avail;
|
|
|
|
|
|
|
|
/* Check if a new window needs to get added for 'dst' */
|
|
|
|
ret = mv_xor_add_io_win(mv_chan, dma_dst);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
/* Check if a new window needs to get added for 'src' */
|
|
|
|
ret = mv_xor_add_io_win(mv_chan, dma_src);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
/* Populate the descriptor */
|
|
|
|
mv_xor_config_sg_ll_desc(new, dma_src, dma_dst, len, prev);
|
|
|
|
prev = new;
|
|
|
|
dst_avail -= len;
|
|
|
|
src_avail -= len;
|
|
|
|
|
|
|
|
if (!first)
|
|
|
|
first = new;
|
|
|
|
else
|
|
|
|
list_move_tail(&new->node, &first->sg_tx_list);
|
|
|
|
|
|
|
|
fetch:
|
|
|
|
/* Fetch the next dst scatterlist entry */
|
|
|
|
if (dst_avail == 0) {
|
|
|
|
if (dst_sg_len == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Fetch the next entry: if there are no more: done */
|
|
|
|
dst_sg = sg_next(dst_sg);
|
|
|
|
if (dst_sg == NULL)
|
|
|
|
break;
|
|
|
|
|
|
|
|
dst_sg_len--;
|
|
|
|
dst_avail = sg_dma_len(dst_sg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fetch the next src scatterlist entry */
|
|
|
|
if (src_avail == 0) {
|
|
|
|
if (src_sg_len == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Fetch the next entry: if there are no more: done */
|
|
|
|
src_sg = sg_next(src_sg);
|
|
|
|
if (src_sg == NULL)
|
|
|
|
break;
|
|
|
|
|
|
|
|
src_sg_len--;
|
|
|
|
src_avail = sg_dma_len(src_sg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set the EOD flag in the last descriptor */
|
|
|
|
mv_xor_desc_config_eod(new);
|
|
|
|
first->async_tx.flags = flags;
|
|
|
|
|
|
|
|
return &first->async_tx;
|
|
|
|
|
|
|
|
err:
|
|
|
|
/* Cleanup: Move all descriptors back into the free list */
|
|
|
|
spin_lock_bh(&mv_chan->lock);
|
|
|
|
mv_desc_clean_slot(first, mv_chan);
|
|
|
|
spin_unlock_bh(&mv_chan->lock);
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
static void mv_xor_free_chan_resources(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
|
|
struct mv_xor_desc_slot *iter, *_iter;
|
|
|
|
int in_use_descs = 0;
|
|
|
|
|
|
|
|
spin_lock_bh(&mv_chan->lock);
|
2014-03-07 19:46:46 +00:00
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_slot_cleanup(mv_chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
|
2015-05-26 13:07:36 +00:00
|
|
|
node) {
|
2008-07-08 18:58:36 +00:00
|
|
|
in_use_descs++;
|
2015-05-26 13:07:36 +00:00
|
|
|
list_move_tail(&iter->node, &mv_chan->free_slots);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
|
2015-05-26 13:07:36 +00:00
|
|
|
node) {
|
|
|
|
in_use_descs++;
|
|
|
|
list_move_tail(&iter->node, &mv_chan->free_slots);
|
|
|
|
}
|
|
|
|
list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots,
|
|
|
|
node) {
|
2008-07-08 18:58:36 +00:00
|
|
|
in_use_descs++;
|
2015-05-26 13:07:36 +00:00
|
|
|
list_move_tail(&iter->node, &mv_chan->free_slots);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
list_for_each_entry_safe_reverse(
|
2015-05-26 13:07:36 +00:00
|
|
|
iter, _iter, &mv_chan->free_slots, node) {
|
|
|
|
list_del(&iter->node);
|
2008-07-08 18:58:36 +00:00
|
|
|
kfree(iter);
|
|
|
|
mv_chan->slots_allocated--;
|
|
|
|
}
|
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
|
2008-07-08 18:58:36 +00:00
|
|
|
__func__, mv_chan->slots_allocated);
|
|
|
|
spin_unlock_bh(&mv_chan->lock);
|
|
|
|
|
|
|
|
if (in_use_descs)
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_err(mv_chan_to_devp(mv_chan),
|
2008-07-08 18:58:36 +00:00
|
|
|
"freeing %d in use descriptors!\n", in_use_descs);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2010-03-26 23:50:49 +00:00
|
|
|
* mv_xor_status - poll the status of an XOR transaction
|
2008-07-08 18:58:36 +00:00
|
|
|
* @chan: XOR channel handle
|
|
|
|
* @cookie: XOR transaction identifier
|
2010-03-26 23:50:49 +00:00
|
|
|
* @txstate: XOR transactions state holder (or NULL)
|
2008-07-08 18:58:36 +00:00
|
|
|
*/
|
2010-03-26 23:50:49 +00:00
|
|
|
static enum dma_status mv_xor_status(struct dma_chan *chan,
|
2008-07-08 18:58:36 +00:00
|
|
|
dma_cookie_t cookie,
|
2010-03-26 23:50:49 +00:00
|
|
|
struct dma_tx_state *txstate)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
|
|
enum dma_status ret;
|
|
|
|
|
2012-03-06 22:35:27 +00:00
|
|
|
ret = dma_cookie_status(chan, cookie, txstate);
|
2014-03-07 19:46:45 +00:00
|
|
|
if (ret == DMA_COMPLETE)
|
2008-07-08 18:58:36 +00:00
|
|
|
return ret;
|
2014-03-07 19:46:46 +00:00
|
|
|
|
|
|
|
spin_lock_bh(&mv_chan->lock);
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_slot_cleanup(mv_chan);
|
2014-03-07 19:46:46 +00:00
|
|
|
spin_unlock_bh(&mv_chan->lock);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-03-06 22:35:27 +00:00
|
|
|
return dma_cookie_status(chan, cookie, txstate);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
static void mv_chan_dump_regs(struct mv_xor_chan *chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
2013-07-29 15:42:13 +00:00
|
|
|
val = readl_relaxed(XOR_CONFIG(chan));
|
2012-10-28 08:05:44 +00:00
|
|
|
dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-07-29 15:42:13 +00:00
|
|
|
val = readl_relaxed(XOR_ACTIVATION(chan));
|
2012-10-28 08:05:44 +00:00
|
|
|
dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-07-29 15:42:13 +00:00
|
|
|
val = readl_relaxed(XOR_INTR_CAUSE(chan));
|
2012-10-28 08:05:44 +00:00
|
|
|
dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-07-29 15:42:13 +00:00
|
|
|
val = readl_relaxed(XOR_INTR_MASK(chan));
|
2012-10-28 08:05:44 +00:00
|
|
|
dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-07-29 15:42:13 +00:00
|
|
|
val = readl_relaxed(XOR_ERROR_CAUSE(chan));
|
2012-10-28 08:05:44 +00:00
|
|
|
dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-07-29 15:42:13 +00:00
|
|
|
val = readl_relaxed(XOR_ERROR_ADDR(chan));
|
2012-10-28 08:05:44 +00:00
|
|
|
dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan,
|
|
|
|
u32 intr_cause)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2014-08-27 13:52:52 +00:00
|
|
|
if (intr_cause & XOR_INT_ERR_DECODE) {
|
|
|
|
dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");
|
|
|
|
return;
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2014-08-27 13:52:52 +00:00
|
|
|
dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",
|
2012-11-15 11:50:27 +00:00
|
|
|
chan->idx, intr_cause);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_dump_regs(chan);
|
2014-08-27 13:52:52 +00:00
|
|
|
WARN_ON(1);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct mv_xor_chan *chan = data;
|
|
|
|
u32 intr_cause = mv_chan_get_intr_cause(chan);
|
|
|
|
|
2012-11-15 13:17:18 +00:00
|
|
|
dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2014-08-27 13:52:52 +00:00
|
|
|
if (intr_cause & XOR_INTR_ERRORS)
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_err_interrupt_handler(chan, intr_cause);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
tasklet_schedule(&chan->irq_tasklet);
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_clear_eoc_cause(chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mv_xor_issue_pending(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
|
|
|
|
|
|
|
|
if (mv_chan->pending >= MV_XOR_THRESHOLD) {
|
|
|
|
mv_chan->pending = 0;
|
|
|
|
mv_chan_activate(mv_chan);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Perform a transaction to verify the HW works.
|
|
|
|
*/
|
|
|
|
|
2015-05-26 13:07:33 +00:00
|
|
|
static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2013-12-10 12:32:37 +00:00
|
|
|
int i, ret;
|
2008-07-08 18:58:36 +00:00
|
|
|
void *src, *dest;
|
|
|
|
dma_addr_t src_dma, dest_dma;
|
|
|
|
struct dma_chan *dma_chan;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
struct dma_async_tx_descriptor *tx;
|
2013-12-10 12:32:36 +00:00
|
|
|
struct dmaengine_unmap_data *unmap;
|
2008-07-08 18:58:36 +00:00
|
|
|
int err = 0;
|
|
|
|
|
2013-12-10 12:32:36 +00:00
|
|
|
src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
|
2008-07-08 18:58:36 +00:00
|
|
|
if (!src)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2013-12-10 12:32:36 +00:00
|
|
|
dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
|
2008-07-08 18:58:36 +00:00
|
|
|
if (!dest) {
|
|
|
|
kfree(src);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fill in src buffer */
|
2013-12-10 12:32:36 +00:00
|
|
|
for (i = 0; i < PAGE_SIZE; i++)
|
2008-07-08 18:58:36 +00:00
|
|
|
((u8 *) src)[i] = (u8)i;
|
|
|
|
|
2012-11-15 14:09:42 +00:00
|
|
|
dma_chan = &mv_chan->dmachan;
|
2009-01-06 18:38:17 +00:00
|
|
|
if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
|
2008-07-08 18:58:36 +00:00
|
|
|
err = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
|
|
|
|
if (!unmap) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
2016-06-01 10:43:32 +00:00
|
|
|
src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src),
|
|
|
|
(size_t)src & ~PAGE_MASK, PAGE_SIZE,
|
|
|
|
DMA_TO_DEVICE);
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap->addr[0] = src_dma;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-12-10 12:32:37 +00:00
|
|
|
ret = dma_mapping_error(dma_chan->device->dev, src_dma);
|
|
|
|
if (ret) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
unmap->to_cnt = 1;
|
|
|
|
|
2016-06-01 10:43:32 +00:00
|
|
|
dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest),
|
|
|
|
(size_t)dest & ~PAGE_MASK, PAGE_SIZE,
|
|
|
|
DMA_FROM_DEVICE);
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap->addr[1] = dest_dma;
|
|
|
|
|
2013-12-10 12:32:37 +00:00
|
|
|
ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
|
|
|
|
if (ret) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
unmap->from_cnt = 1;
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap->len = PAGE_SIZE;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
|
2013-12-10 12:32:36 +00:00
|
|
|
PAGE_SIZE, 0);
|
2013-12-10 12:32:37 +00:00
|
|
|
if (!tx) {
|
|
|
|
dev_err(dma_chan->device->dev,
|
|
|
|
"Self-test cannot prepare operation, disabling\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
cookie = mv_xor_tx_submit(tx);
|
2013-12-10 12:32:37 +00:00
|
|
|
if (dma_submit_error(cookie)) {
|
|
|
|
dev_err(dma_chan->device->dev,
|
|
|
|
"Self-test submit error, disabling\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
mv_xor_issue_pending(dma_chan);
|
|
|
|
async_tx_ack(tx);
|
|
|
|
msleep(1);
|
|
|
|
|
2010-03-26 23:50:49 +00:00
|
|
|
if (mv_xor_status(dma_chan, cookie, NULL) !=
|
2013-10-16 15:21:04 +00:00
|
|
|
DMA_COMPLETE) {
|
2012-11-15 11:50:27 +00:00
|
|
|
dev_err(dma_chan->device->dev,
|
|
|
|
"Self-test copy timed out, disabling\n");
|
2008-07-08 18:58:36 +00:00
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
2012-11-15 12:01:59 +00:00
|
|
|
dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
|
2013-12-10 12:32:36 +00:00
|
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
|
|
if (memcmp(src, dest, PAGE_SIZE)) {
|
2012-11-15 11:50:27 +00:00
|
|
|
dev_err(dma_chan->device->dev,
|
|
|
|
"Self-test copy failed compare, disabling\n");
|
2008-07-08 18:58:36 +00:00
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
|
|
|
free_resources:
|
2013-12-10 12:32:36 +00:00
|
|
|
dmaengine_unmap_put(unmap);
|
2008-07-08 18:58:36 +00:00
|
|
|
mv_xor_free_chan_resources(dma_chan);
|
|
|
|
out:
|
|
|
|
kfree(src);
|
|
|
|
kfree(dest);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
|
2012-11-19 18:22:55 +00:00
|
|
|
static int
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_xor_self_test(struct mv_xor_chan *mv_chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2013-12-10 12:32:37 +00:00
|
|
|
int i, src_idx, ret;
|
2008-07-08 18:58:36 +00:00
|
|
|
struct page *dest;
|
|
|
|
struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
|
|
|
|
dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
|
|
|
|
dma_addr_t dest_dma;
|
|
|
|
struct dma_async_tx_descriptor *tx;
|
2013-12-10 12:32:36 +00:00
|
|
|
struct dmaengine_unmap_data *unmap;
|
2008-07-08 18:58:36 +00:00
|
|
|
struct dma_chan *dma_chan;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
u8 cmp_byte = 0;
|
|
|
|
u32 cmp_word;
|
|
|
|
int err = 0;
|
2013-12-10 12:32:36 +00:00
|
|
|
int src_count = MV_XOR_NUM_SRC_TEST;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-12-10 12:32:36 +00:00
|
|
|
for (src_idx = 0; src_idx < src_count; src_idx++) {
|
2008-07-08 18:58:36 +00:00
|
|
|
xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
|
2009-02-25 12:56:21 +00:00
|
|
|
if (!xor_srcs[src_idx]) {
|
|
|
|
while (src_idx--)
|
2008-07-08 18:58:36 +00:00
|
|
|
__free_page(xor_srcs[src_idx]);
|
2009-02-25 12:56:21 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
dest = alloc_page(GFP_KERNEL);
|
2009-02-25 12:56:21 +00:00
|
|
|
if (!dest) {
|
|
|
|
while (src_idx--)
|
2008-07-08 18:58:36 +00:00
|
|
|
__free_page(xor_srcs[src_idx]);
|
2009-02-25 12:56:21 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
/* Fill in src buffers */
|
2013-12-10 12:32:36 +00:00
|
|
|
for (src_idx = 0; src_idx < src_count; src_idx++) {
|
2008-07-08 18:58:36 +00:00
|
|
|
u8 *ptr = page_address(xor_srcs[src_idx]);
|
|
|
|
for (i = 0; i < PAGE_SIZE; i++)
|
|
|
|
ptr[i] = (1 << src_idx);
|
|
|
|
}
|
|
|
|
|
2013-12-10 12:32:36 +00:00
|
|
|
for (src_idx = 0; src_idx < src_count; src_idx++)
|
2008-07-08 18:58:36 +00:00
|
|
|
cmp_byte ^= (u8) (1 << src_idx);
|
|
|
|
|
|
|
|
cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
|
|
|
|
(cmp_byte << 8) | cmp_byte;
|
|
|
|
|
|
|
|
memset(page_address(dest), 0, PAGE_SIZE);
|
|
|
|
|
2012-11-15 14:09:42 +00:00
|
|
|
dma_chan = &mv_chan->dmachan;
|
2009-01-06 18:38:17 +00:00
|
|
|
if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
|
2008-07-08 18:58:36 +00:00
|
|
|
err = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!unmap) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
/* test xor */
|
2013-12-10 12:32:36 +00:00
|
|
|
for (i = 0; i < src_count; i++) {
|
|
|
|
unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
|
|
|
|
0, PAGE_SIZE, DMA_TO_DEVICE);
|
|
|
|
dma_srcs[i] = unmap->addr[i];
|
2013-12-10 12:32:37 +00:00
|
|
|
ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]);
|
|
|
|
if (ret) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap->to_cnt++;
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
dest_dma = unmap->addr[src_count];
|
2013-12-10 12:32:37 +00:00
|
|
|
ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]);
|
|
|
|
if (ret) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
2013-12-10 12:32:36 +00:00
|
|
|
unmap->from_cnt = 1;
|
|
|
|
unmap->len = PAGE_SIZE;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
|
2013-12-10 12:32:36 +00:00
|
|
|
src_count, PAGE_SIZE, 0);
|
2013-12-10 12:32:37 +00:00
|
|
|
if (!tx) {
|
|
|
|
dev_err(dma_chan->device->dev,
|
|
|
|
"Self-test cannot prepare operation, disabling\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
cookie = mv_xor_tx_submit(tx);
|
2013-12-10 12:32:37 +00:00
|
|
|
if (dma_submit_error(cookie)) {
|
|
|
|
dev_err(dma_chan->device->dev,
|
|
|
|
"Self-test submit error, disabling\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
mv_xor_issue_pending(dma_chan);
|
|
|
|
async_tx_ack(tx);
|
|
|
|
msleep(8);
|
|
|
|
|
2010-03-26 23:50:49 +00:00
|
|
|
if (mv_xor_status(dma_chan, cookie, NULL) !=
|
2013-10-16 15:21:04 +00:00
|
|
|
DMA_COMPLETE) {
|
2012-11-15 11:50:27 +00:00
|
|
|
dev_err(dma_chan->device->dev,
|
|
|
|
"Self-test xor timed out, disabling\n");
|
2008-07-08 18:58:36 +00:00
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
2012-11-15 12:01:59 +00:00
|
|
|
dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
|
2008-07-08 18:58:36 +00:00
|
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
|
|
for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
|
|
|
|
u32 *ptr = page_address(dest);
|
|
|
|
if (ptr[i] != cmp_word) {
|
2012-11-15 11:50:27 +00:00
|
|
|
dev_err(dma_chan->device->dev,
|
2012-10-28 08:05:44 +00:00
|
|
|
"Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
|
|
|
|
i, ptr[i], cmp_word);
|
2008-07-08 18:58:36 +00:00
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
free_resources:
|
2013-12-10 12:32:36 +00:00
|
|
|
dmaengine_unmap_put(unmap);
|
2008-07-08 18:58:36 +00:00
|
|
|
mv_xor_free_chan_resources(dma_chan);
|
|
|
|
out:
|
2013-12-10 12:32:36 +00:00
|
|
|
src_idx = src_count;
|
2008-07-08 18:58:36 +00:00
|
|
|
while (src_idx--)
|
|
|
|
__free_page(xor_srcs[src_idx]);
|
|
|
|
__free_page(dest);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2012-11-15 14:17:05 +00:00
|
|
|
static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
struct dma_chan *chan, *_chan;
|
2012-11-15 14:17:05 +00:00
|
|
|
struct device *dev = mv_chan->dmadev.dev;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 14:17:05 +00:00
|
|
|
dma_async_device_unregister(&mv_chan->dmadev);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 14:55:30 +00:00
|
|
|
dma_free_coherent(dev, MV_XOR_POOL_SIZE,
|
2012-11-15 14:17:05 +00:00
|
|
|
mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
|
2014-08-27 13:52:55 +00:00
|
|
|
dma_unmap_single(dev, mv_chan->dummy_src_addr,
|
|
|
|
MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
|
|
|
|
dma_unmap_single(dev, mv_chan->dummy_dst_addr,
|
|
|
|
MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 14:17:05 +00:00
|
|
|
list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
|
2012-10-29 15:45:46 +00:00
|
|
|
device_node) {
|
2008-07-08 18:58:36 +00:00
|
|
|
list_del(&chan->device_node);
|
|
|
|
}
|
|
|
|
|
2012-11-15 15:11:18 +00:00
|
|
|
free_irq(mv_chan->irq, mv_chan);
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-15 14:17:05 +00:00
|
|
|
static struct mv_xor_chan *
|
2012-11-15 14:29:53 +00:00
|
|
|
mv_xor_channel_add(struct mv_xor_device *xordev,
|
2012-10-29 15:45:46 +00:00
|
|
|
struct platform_device *pdev,
|
2016-04-29 07:49:06 +00:00
|
|
|
int idx, dma_cap_mask_t cap_mask, int irq)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct mv_xor_chan *mv_chan;
|
|
|
|
struct dma_device *dma_dev;
|
|
|
|
|
2012-11-15 14:17:05 +00:00
|
|
|
mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
|
2013-09-02 08:24:20 +00:00
|
|
|
if (!mv_chan)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 14:36:37 +00:00
|
|
|
mv_chan->idx = idx;
|
2012-11-15 15:11:18 +00:00
|
|
|
mv_chan->irq = irq;
|
2016-04-29 07:49:06 +00:00
|
|
|
if (xordev->xor_type == XOR_ORION)
|
|
|
|
mv_chan->op_in_desc = XOR_MODE_IN_REG;
|
|
|
|
else
|
|
|
|
mv_chan->op_in_desc = XOR_MODE_IN_DESC;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 14:17:05 +00:00
|
|
|
dma_dev = &mv_chan->dmadev;
|
2016-09-15 05:37:31 +00:00
|
|
|
mv_chan->xordev = xordev;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2014-08-27 13:52:55 +00:00
|
|
|
/*
|
|
|
|
* These source and destination dummy buffers are used to implement
|
|
|
|
* a DMA_INTERRUPT operation as a minimum-sized XOR operation.
|
|
|
|
* Hence, we only need to map the buffers at initialization-time.
|
|
|
|
*/
|
|
|
|
mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev,
|
|
|
|
mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
|
|
|
|
mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev,
|
|
|
|
mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
/* allocate coherent memory for hardware descriptors
|
|
|
|
* note: writecombine gives slightly better performance, but
|
|
|
|
* requires that we explicitly flush the writes
|
|
|
|
*/
|
2012-11-15 14:17:05 +00:00
|
|
|
mv_chan->dma_desc_pool_virt =
|
dma, mm/pat: Rename dma_*_writecombine() to dma_*_wc()
Rename dma_*_writecombine() to dma_*_wc(), so that the naming
is coherent across the various write-combining APIs. Keep the
old names for compatibility for a while, these can be removed
at a later time. A guard is left to enable backporting of the
rename, and later remove of the old mapping defines seemlessly.
Build tested successfully with allmodconfig.
The following Coccinelle SmPL patch was used for this simple
transformation:
@ rename_dma_alloc_writecombine @
expression dev, size, dma_addr, gfp;
@@
-dma_alloc_writecombine(dev, size, dma_addr, gfp)
+dma_alloc_wc(dev, size, dma_addr, gfp)
@ rename_dma_free_writecombine @
expression dev, size, cpu_addr, dma_addr;
@@
-dma_free_writecombine(dev, size, cpu_addr, dma_addr)
+dma_free_wc(dev, size, cpu_addr, dma_addr)
@ rename_dma_mmap_writecombine @
expression dev, vma, cpu_addr, dma_addr, size;
@@
-dma_mmap_writecombine(dev, vma, cpu_addr, dma_addr, size)
+dma_mmap_wc(dev, vma, cpu_addr, dma_addr, size)
We also keep the old names as compatibility helpers, and
guard against their definition to make backporting easier.
Generated-by: Coccinelle SmPL
Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: airlied@linux.ie
Cc: akpm@linux-foundation.org
Cc: benh@kernel.crashing.org
Cc: bhelgaas@google.com
Cc: bp@suse.de
Cc: dan.j.williams@intel.com
Cc: daniel.vetter@ffwll.ch
Cc: dhowells@redhat.com
Cc: julia.lawall@lip6.fr
Cc: konrad.wilk@oracle.com
Cc: linux-fbdev@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: luto@amacapital.net
Cc: mst@redhat.com
Cc: tomi.valkeinen@ti.com
Cc: toshi.kani@hp.com
Cc: vinod.koul@intel.com
Cc: xen-devel@lists.xensource.com
Link: http://lkml.kernel.org/r/1453516462-4844-1-git-send-email-mcgrof@do-not-panic.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-01-23 02:34:22 +00:00
|
|
|
dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool,
|
|
|
|
GFP_KERNEL);
|
2012-11-15 14:17:05 +00:00
|
|
|
if (!mv_chan->dma_desc_pool_virt)
|
2012-10-29 15:45:46 +00:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
/* discover transaction capabilites from the platform data */
|
2012-10-29 15:45:46 +00:00
|
|
|
dma_dev->cap_mask = cap_mask;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
INIT_LIST_HEAD(&dma_dev->channels);
|
|
|
|
|
|
|
|
/* set base routines */
|
|
|
|
dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
|
|
|
|
dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
|
2010-03-26 23:50:49 +00:00
|
|
|
dma_dev->device_tx_status = mv_xor_status;
|
2008-07-08 18:58:36 +00:00
|
|
|
dma_dev->device_issue_pending = mv_xor_issue_pending;
|
|
|
|
dma_dev->dev = &pdev->dev;
|
|
|
|
|
|
|
|
/* set prep routines based on capability */
|
2014-08-27 13:52:55 +00:00
|
|
|
if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
|
|
|
|
dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt;
|
2008-07-08 18:58:36 +00:00
|
|
|
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
|
|
|
|
dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
|
2016-10-26 08:10:25 +00:00
|
|
|
if (dma_has_cap(DMA_SG, dma_dev->cap_mask))
|
|
|
|
dma_dev->device_prep_dma_sg = mv_xor_prep_dma_sg;
|
2008-07-08 18:58:36 +00:00
|
|
|
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
|
2009-06-28 16:26:21 +00:00
|
|
|
dma_dev->max_xor = 8;
|
2008-07-08 18:58:36 +00:00
|
|
|
dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
|
|
|
|
}
|
|
|
|
|
2012-11-15 14:29:53 +00:00
|
|
|
mv_chan->mmr_base = xordev->xor_base;
|
2013-10-30 15:01:43 +00:00
|
|
|
mv_chan->mmr_high_base = xordev->xor_high_base;
|
2008-07-08 18:58:36 +00:00
|
|
|
tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
|
|
|
|
mv_chan);
|
|
|
|
|
|
|
|
/* clear errors before enabling interrupts */
|
2015-05-26 13:07:33 +00:00
|
|
|
mv_chan_clear_err_status(mv_chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
dma: mv_xor: use request_irq() instead of devm_request_irq()
Even through the usage of devm_*() functions is generally recommended
over their classic variants, in the case of devm_request_irq()
combined with irq_of_parse_and_map(), it doesn't work nicely.
We have the following scenario:
irq_of_parse_and_map(...)
devm_request_irq(...)
For some reason, the driver initialization fails at a later
point. Since irq_of_parse_and_map() is no device-managed, we do a:
irq_dispose_mapping(...)
Unfortunately, this doesn't work, because the free_irq() must be done
prior to calling irq_dispose_mapping(). But with the devm mechanism,
the automatic free_irq() would happen only after we get out of the
->probe() function.
So basically, we revert to using request_irq() with traditional error
handling, so that in case of error, free_irq() gets called before
irq_dispose_mapping().
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2012-11-22 17:19:09 +00:00
|
|
|
ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
|
|
|
|
0, dev_name(&pdev->dev), mv_chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
if (ret)
|
|
|
|
goto err_free_dma;
|
|
|
|
|
|
|
|
mv_chan_unmask_interrupts(mv_chan);
|
|
|
|
|
2015-05-26 13:07:34 +00:00
|
|
|
if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
|
2015-12-22 10:43:28 +00:00
|
|
|
mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC);
|
2015-05-26 13:07:34 +00:00
|
|
|
else
|
2015-12-22 10:43:28 +00:00
|
|
|
mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
spin_lock_init(&mv_chan->lock);
|
|
|
|
INIT_LIST_HEAD(&mv_chan->chain);
|
|
|
|
INIT_LIST_HEAD(&mv_chan->completed_slots);
|
2015-05-26 13:07:36 +00:00
|
|
|
INIT_LIST_HEAD(&mv_chan->free_slots);
|
|
|
|
INIT_LIST_HEAD(&mv_chan->allocated_slots);
|
2012-11-15 13:57:44 +00:00
|
|
|
mv_chan->dmachan.device = dma_dev;
|
|
|
|
dma_cookie_init(&mv_chan->dmachan);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 13:57:44 +00:00
|
|
|
list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
|
2015-05-26 13:07:33 +00:00
|
|
|
ret = mv_chan_memcpy_self_test(mv_chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
|
|
|
|
if (ret)
|
dma: mv_xor: use request_irq() instead of devm_request_irq()
Even through the usage of devm_*() functions is generally recommended
over their classic variants, in the case of devm_request_irq()
combined with irq_of_parse_and_map(), it doesn't work nicely.
We have the following scenario:
irq_of_parse_and_map(...)
devm_request_irq(...)
For some reason, the driver initialization fails at a later
point. Since irq_of_parse_and_map() is no device-managed, we do a:
irq_dispose_mapping(...)
Unfortunately, this doesn't work, because the free_irq() must be done
prior to calling irq_dispose_mapping(). But with the devm mechanism,
the automatic free_irq() would happen only after we get out of the
->probe() function.
So basically, we revert to using request_irq() with traditional error
handling, so that in case of error, free_irq() gets called before
irq_dispose_mapping().
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2012-11-22 17:19:09 +00:00
|
|
|
goto err_free_irq;
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
|
2015-05-26 13:07:33 +00:00
|
|
|
ret = mv_chan_xor_self_test(mv_chan);
|
2008-07-08 18:58:36 +00:00
|
|
|
dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
|
|
|
|
if (ret)
|
dma: mv_xor: use request_irq() instead of devm_request_irq()
Even through the usage of devm_*() functions is generally recommended
over their classic variants, in the case of devm_request_irq()
combined with irq_of_parse_and_map(), it doesn't work nicely.
We have the following scenario:
irq_of_parse_and_map(...)
devm_request_irq(...)
For some reason, the driver initialization fails at a later
point. Since irq_of_parse_and_map() is no device-managed, we do a:
irq_dispose_mapping(...)
Unfortunately, this doesn't work, because the free_irq() must be done
prior to calling irq_dispose_mapping(). But with the devm mechanism,
the automatic free_irq() would happen only after we get out of the
->probe() function.
So basically, we revert to using request_irq() with traditional error
handling, so that in case of error, free_irq() gets called before
irq_dispose_mapping().
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2012-11-22 17:19:09 +00:00
|
|
|
goto err_free_irq;
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2016-10-26 08:10:25 +00:00
|
|
|
dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s%s)\n",
|
2015-05-26 13:07:34 +00:00
|
|
|
mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode",
|
2012-10-28 08:05:44 +00:00
|
|
|
dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
|
|
|
|
dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
|
2016-10-26 08:10:25 +00:00
|
|
|
dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "sg " : "",
|
2012-10-28 08:05:44 +00:00
|
|
|
dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
dma_async_device_register(dma_dev);
|
2012-11-15 14:17:05 +00:00
|
|
|
return mv_chan;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
dma: mv_xor: use request_irq() instead of devm_request_irq()
Even through the usage of devm_*() functions is generally recommended
over their classic variants, in the case of devm_request_irq()
combined with irq_of_parse_and_map(), it doesn't work nicely.
We have the following scenario:
irq_of_parse_and_map(...)
devm_request_irq(...)
For some reason, the driver initialization fails at a later
point. Since irq_of_parse_and_map() is no device-managed, we do a:
irq_dispose_mapping(...)
Unfortunately, this doesn't work, because the free_irq() must be done
prior to calling irq_dispose_mapping(). But with the devm mechanism,
the automatic free_irq() would happen only after we get out of the
->probe() function.
So basically, we revert to using request_irq() with traditional error
handling, so that in case of error, free_irq() gets called before
irq_dispose_mapping().
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2012-11-22 17:19:09 +00:00
|
|
|
err_free_irq:
|
|
|
|
free_irq(mv_chan->irq, mv_chan);
|
2016-06-01 10:43:31 +00:00
|
|
|
err_free_dma:
|
2012-11-15 14:55:30 +00:00
|
|
|
dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
|
2012-11-15 14:17:05 +00:00
|
|
|
mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
|
2012-10-29 15:45:46 +00:00
|
|
|
return ERR_PTR(ret);
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2012-11-15 14:29:53 +00:00
|
|
|
mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
|
2011-12-07 20:48:07 +00:00
|
|
|
const struct mbus_dram_target_info *dram)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2013-10-30 15:01:43 +00:00
|
|
|
void __iomem *base = xordev->xor_high_base;
|
2008-07-08 18:58:36 +00:00
|
|
|
u32 win_enable = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
writel(0, base + WINDOW_BASE(i));
|
|
|
|
writel(0, base + WINDOW_SIZE(i));
|
|
|
|
if (i < 4)
|
|
|
|
writel(0, base + WINDOW_REMAP_HIGH(i));
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dram->num_cs; i++) {
|
2011-12-07 20:48:07 +00:00
|
|
|
const struct mbus_dram_window *cs = dram->cs + i;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
|
|
|
writel((cs->base & 0xffff0000) |
|
|
|
|
(cs->mbus_attr << 8) |
|
|
|
|
dram->mbus_dram_target_id, base + WINDOW_BASE(i));
|
|
|
|
writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
|
|
|
|
|
2016-09-15 05:37:31 +00:00
|
|
|
/* Fill the caching variables for later use */
|
|
|
|
xordev->win_start[i] = cs->base;
|
|
|
|
xordev->win_end[i] = cs->base + cs->size - 1;
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
win_enable |= (1 << i);
|
|
|
|
win_enable |= 3 << (16 + (2 * i));
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
|
2012-11-22 17:16:37 +00:00
|
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(0));
|
|
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(1));
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2016-04-29 07:49:07 +00:00
|
|
|
static void
|
|
|
|
mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev)
|
|
|
|
{
|
|
|
|
void __iomem *base = xordev->xor_high_base;
|
|
|
|
u32 win_enable = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
writel(0, base + WINDOW_BASE(i));
|
|
|
|
writel(0, base + WINDOW_SIZE(i));
|
|
|
|
if (i < 4)
|
|
|
|
writel(0, base + WINDOW_REMAP_HIGH(i));
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* For Armada3700 open default 4GB Mbus window. The dram
|
|
|
|
* related configuration are done at AXIS level.
|
|
|
|
*/
|
|
|
|
writel(0xffff0000, base + WINDOW_SIZE(0));
|
|
|
|
win_enable |= 1;
|
|
|
|
win_enable |= 3 << 16;
|
|
|
|
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
|
|
|
|
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
|
|
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(0));
|
|
|
|
writel(0, base + WINDOW_OVERRIDE_CTRL(1));
|
|
|
|
}
|
|
|
|
|
2015-12-22 10:43:29 +00:00
|
|
|
/*
|
|
|
|
* Since this XOR driver is basically used only for RAID5, we don't
|
|
|
|
* need to care about synchronizing ->suspend with DMA activity,
|
|
|
|
* because the DMA engine will naturally be quiet due to the block
|
|
|
|
* devices being suspended.
|
|
|
|
*/
|
|
|
|
static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
|
|
|
|
{
|
|
|
|
struct mv_xor_device *xordev = platform_get_drvdata(pdev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
|
|
|
|
struct mv_xor_chan *mv_chan = xordev->channels[i];
|
|
|
|
|
|
|
|
if (!mv_chan)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
mv_chan->saved_config_reg =
|
|
|
|
readl_relaxed(XOR_CONFIG(mv_chan));
|
|
|
|
mv_chan->saved_int_mask_reg =
|
|
|
|
readl_relaxed(XOR_INTR_MASK(mv_chan));
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mv_xor_resume(struct platform_device *dev)
|
|
|
|
{
|
|
|
|
struct mv_xor_device *xordev = platform_get_drvdata(dev);
|
|
|
|
const struct mbus_dram_target_info *dram;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
|
|
|
|
struct mv_xor_chan *mv_chan = xordev->channels[i];
|
|
|
|
|
|
|
|
if (!mv_chan)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
writel_relaxed(mv_chan->saved_config_reg,
|
|
|
|
XOR_CONFIG(mv_chan));
|
|
|
|
writel_relaxed(mv_chan->saved_int_mask_reg,
|
|
|
|
XOR_INTR_MASK(mv_chan));
|
|
|
|
}
|
|
|
|
|
2016-04-29 07:49:07 +00:00
|
|
|
if (xordev->xor_type == XOR_ARMADA_37XX) {
|
|
|
|
mv_xor_conf_mbus_windows_a3700(xordev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-12-22 10:43:29 +00:00
|
|
|
dram = mv_mbus_dram_info();
|
|
|
|
if (dram)
|
|
|
|
mv_xor_conf_mbus_windows(xordev, dram);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-05-26 13:07:34 +00:00
|
|
|
static const struct of_device_id mv_xor_dt_ids[] = {
|
2016-04-29 07:49:06 +00:00
|
|
|
{ .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
|
|
|
|
{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
|
2016-04-29 07:49:07 +00:00
|
|
|
{ .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX },
|
2015-05-26 13:07:34 +00:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
2015-07-08 14:28:19 +00:00
|
|
|
static unsigned int mv_xor_engine_count;
|
2015-05-26 13:07:34 +00:00
|
|
|
|
2012-12-14 22:54:26 +00:00
|
|
|
static int mv_xor_probe(struct platform_device *pdev)
|
2008-07-08 18:58:36 +00:00
|
|
|
{
|
2011-12-07 20:48:07 +00:00
|
|
|
const struct mbus_dram_target_info *dram;
|
2012-11-15 14:29:53 +00:00
|
|
|
struct mv_xor_device *xordev;
|
2013-07-30 08:09:11 +00:00
|
|
|
struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
2008-07-08 18:58:36 +00:00
|
|
|
struct resource *res;
|
2015-07-08 14:28:19 +00:00
|
|
|
unsigned int max_engines, max_channels;
|
2012-10-29 15:54:49 +00:00
|
|
|
int i, ret;
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-10-28 08:05:44 +00:00
|
|
|
dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-11-15 14:29:53 +00:00
|
|
|
xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
|
|
|
|
if (!xordev)
|
2008-07-08 18:58:36 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2012-11-15 14:29:53 +00:00
|
|
|
xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
|
|
|
|
resource_size(res));
|
|
|
|
if (!xordev->xor_base)
|
2008-07-08 18:58:36 +00:00
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
|
|
if (!res)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2012-11-15 14:29:53 +00:00
|
|
|
xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
|
|
|
|
resource_size(res));
|
|
|
|
if (!xordev->xor_high_base)
|
2008-07-08 18:58:36 +00:00
|
|
|
return -EBUSY;
|
|
|
|
|
2012-11-15 14:29:53 +00:00
|
|
|
platform_set_drvdata(pdev, xordev);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2016-04-29 07:49:06 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to know which type of XOR device we use before
|
|
|
|
* setting up. In non-dt case it can only be the legacy one.
|
|
|
|
*/
|
|
|
|
xordev->xor_type = XOR_ORION;
|
|
|
|
if (pdev->dev.of_node) {
|
|
|
|
const struct of_device_id *of_id =
|
|
|
|
of_match_device(mv_xor_dt_ids,
|
|
|
|
&pdev->dev);
|
|
|
|
|
|
|
|
xordev->xor_type = (uintptr_t)of_id->data;
|
|
|
|
}
|
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
/*
|
|
|
|
* (Re-)program MBUS remapping windows if we are asked to.
|
|
|
|
*/
|
2016-04-29 07:49:07 +00:00
|
|
|
if (xordev->xor_type == XOR_ARMADA_37XX) {
|
|
|
|
mv_xor_conf_mbus_windows_a3700(xordev);
|
|
|
|
} else {
|
|
|
|
dram = mv_mbus_dram_info();
|
|
|
|
if (dram)
|
|
|
|
mv_xor_conf_mbus_windows(xordev, dram);
|
|
|
|
}
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2012-02-19 12:30:26 +00:00
|
|
|
/* Not all platforms can gate the clock, so it is not
|
|
|
|
* an error if the clock does not exists.
|
|
|
|
*/
|
2012-11-15 14:29:53 +00:00
|
|
|
xordev->clk = clk_get(&pdev->dev, NULL);
|
|
|
|
if (!IS_ERR(xordev->clk))
|
|
|
|
clk_prepare_enable(xordev->clk);
|
2012-02-19 12:30:26 +00:00
|
|
|
|
2015-07-08 14:28:19 +00:00
|
|
|
/*
|
|
|
|
* We don't want to have more than one channel per CPU in
|
|
|
|
* order for async_tx to perform well. So we limit the number
|
|
|
|
* of engines and channels so that we take into account this
|
|
|
|
* constraint. Note that we also want to use channels from
|
2016-04-29 07:49:07 +00:00
|
|
|
* separate engines when possible. For dual-CPU Armada 3700
|
|
|
|
* SoC with single XOR engine allow using its both channels.
|
2015-07-08 14:28:19 +00:00
|
|
|
*/
|
|
|
|
max_engines = num_present_cpus();
|
2016-04-29 07:49:07 +00:00
|
|
|
if (xordev->xor_type == XOR_ARMADA_37XX)
|
|
|
|
max_channels = num_present_cpus();
|
|
|
|
else
|
|
|
|
max_channels = min_t(unsigned int,
|
|
|
|
MV_XOR_MAX_CHANNELS,
|
|
|
|
DIV_ROUND_UP(num_present_cpus(), 2));
|
2015-07-08 14:28:19 +00:00
|
|
|
|
|
|
|
if (mv_xor_engine_count >= max_engines)
|
|
|
|
return 0;
|
|
|
|
|
2012-11-15 15:47:58 +00:00
|
|
|
if (pdev->dev.of_node) {
|
|
|
|
struct device_node *np;
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
for_each_child_of_node(pdev->dev.of_node, np) {
|
2013-12-12 23:59:08 +00:00
|
|
|
struct mv_xor_chan *chan;
|
2012-11-15 15:47:58 +00:00
|
|
|
dma_cap_mask_t cap_mask;
|
|
|
|
int irq;
|
|
|
|
|
2015-07-08 14:28:19 +00:00
|
|
|
if (i >= max_channels)
|
|
|
|
continue;
|
|
|
|
|
2012-11-15 15:47:58 +00:00
|
|
|
dma_cap_zero(cap_mask);
|
dmaengine: mv_xor: remove support for dmacap,* DT properties
The only reason why we had dmacap,* properties is because back when
DMA_MEMSET was supported, only one out of the two channels per engine
could do a memset operation. But this is something that the driver
already knows anyway, and since then, the DMA_MEMSET support has been
removed.
The driver is already well aware of what each channel supports and the
one to one mapping between Linux specific implementation details (such
as dmacap,interrupt enabling DMA_INTERRUPT) and DT properties is a
good indication that these DT properties are wrong.
Therefore, this commit simply gets rid of these dmacap,* properties,
they are now ignored, and the driver is responsible for knowing the
capabilities of the hardware with regard to the dmaengine subsystem
expectations.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-07-08 14:28:16 +00:00
|
|
|
dma_cap_set(DMA_MEMCPY, cap_mask);
|
2016-10-26 08:10:25 +00:00
|
|
|
dma_cap_set(DMA_SG, cap_mask);
|
dmaengine: mv_xor: remove support for dmacap,* DT properties
The only reason why we had dmacap,* properties is because back when
DMA_MEMSET was supported, only one out of the two channels per engine
could do a memset operation. But this is something that the driver
already knows anyway, and since then, the DMA_MEMSET support has been
removed.
The driver is already well aware of what each channel supports and the
one to one mapping between Linux specific implementation details (such
as dmacap,interrupt enabling DMA_INTERRUPT) and DT properties is a
good indication that these DT properties are wrong.
Therefore, this commit simply gets rid of these dmacap,* properties,
they are now ignored, and the driver is responsible for knowing the
capabilities of the hardware with regard to the dmaengine subsystem
expectations.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-07-08 14:28:16 +00:00
|
|
|
dma_cap_set(DMA_XOR, cap_mask);
|
|
|
|
dma_cap_set(DMA_INTERRUPT, cap_mask);
|
2012-11-15 15:47:58 +00:00
|
|
|
|
|
|
|
irq = irq_of_parse_and_map(np, 0);
|
2012-11-22 17:22:12 +00:00
|
|
|
if (!irq) {
|
|
|
|
ret = -ENODEV;
|
2012-11-15 15:47:58 +00:00
|
|
|
goto err_channel_add;
|
|
|
|
}
|
|
|
|
|
2013-12-12 23:59:08 +00:00
|
|
|
chan = mv_xor_channel_add(xordev, pdev, i,
|
2016-04-29 07:49:06 +00:00
|
|
|
cap_mask, irq);
|
2013-12-12 23:59:08 +00:00
|
|
|
if (IS_ERR(chan)) {
|
|
|
|
ret = PTR_ERR(chan);
|
2012-11-15 15:47:58 +00:00
|
|
|
irq_dispose_mapping(irq);
|
|
|
|
goto err_channel_add;
|
|
|
|
}
|
|
|
|
|
2013-12-12 23:59:08 +00:00
|
|
|
xordev->channels[i] = chan;
|
2012-11-15 15:47:58 +00:00
|
|
|
i++;
|
|
|
|
}
|
|
|
|
} else if (pdata && pdata->channels) {
|
2015-07-08 14:28:19 +00:00
|
|
|
for (i = 0; i < max_channels; i++) {
|
2012-10-30 10:56:26 +00:00
|
|
|
struct mv_xor_channel_data *cd;
|
2013-12-12 23:59:08 +00:00
|
|
|
struct mv_xor_chan *chan;
|
2012-10-29 15:54:49 +00:00
|
|
|
int irq;
|
|
|
|
|
|
|
|
cd = &pdata->channels[i];
|
|
|
|
if (!cd) {
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err_channel_add;
|
|
|
|
}
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, i);
|
|
|
|
if (irq < 0) {
|
|
|
|
ret = irq;
|
|
|
|
goto err_channel_add;
|
|
|
|
}
|
|
|
|
|
2013-12-12 23:59:08 +00:00
|
|
|
chan = mv_xor_channel_add(xordev, pdev, i,
|
2016-04-29 07:49:06 +00:00
|
|
|
cd->cap_mask, irq);
|
2013-12-12 23:59:08 +00:00
|
|
|
if (IS_ERR(chan)) {
|
|
|
|
ret = PTR_ERR(chan);
|
2012-10-29 15:54:49 +00:00
|
|
|
goto err_channel_add;
|
|
|
|
}
|
2013-12-12 23:59:08 +00:00
|
|
|
|
|
|
|
xordev->channels[i] = chan;
|
2012-10-29 15:54:49 +00:00
|
|
|
}
|
|
|
|
}
|
2012-02-19 12:30:26 +00:00
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
return 0;
|
2012-10-29 15:54:49 +00:00
|
|
|
|
|
|
|
err_channel_add:
|
|
|
|
for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
|
2012-11-15 15:47:58 +00:00
|
|
|
if (xordev->channels[i]) {
|
2013-01-06 10:10:43 +00:00
|
|
|
mv_xor_channel_remove(xordev->channels[i]);
|
2012-11-15 15:47:58 +00:00
|
|
|
if (pdev->dev.of_node)
|
|
|
|
irq_dispose_mapping(xordev->channels[i]->irq);
|
|
|
|
}
|
2012-10-29 15:54:49 +00:00
|
|
|
|
2013-01-06 10:10:44 +00:00
|
|
|
if (!IS_ERR(xordev->clk)) {
|
|
|
|
clk_disable_unprepare(xordev->clk);
|
|
|
|
clk_put(xordev->clk);
|
|
|
|
}
|
|
|
|
|
2012-10-29 15:54:49 +00:00
|
|
|
return ret;
|
2008-07-08 18:58:36 +00:00
|
|
|
}
|
|
|
|
|
2012-10-30 11:05:40 +00:00
|
|
|
static struct platform_driver mv_xor_driver = {
|
|
|
|
.probe = mv_xor_probe,
|
2015-12-22 10:43:29 +00:00
|
|
|
.suspend = mv_xor_suspend,
|
|
|
|
.resume = mv_xor_resume,
|
2008-07-08 18:58:36 +00:00
|
|
|
.driver = {
|
2012-11-15 15:47:58 +00:00
|
|
|
.name = MV_XOR_NAME,
|
|
|
|
.of_match_table = of_match_ptr(mv_xor_dt_ids),
|
2008-07-08 18:58:36 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2016-11-18 14:12:26 +00:00
|
|
|
builtin_platform_driver(mv_xor_driver);
|
2008-07-08 18:58:36 +00:00
|
|
|
|
2015-08-21 20:27:49 +00:00
|
|
|
/*
|
2008-07-08 18:58:36 +00:00
|
|
|
MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
|
|
|
|
MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
|
|
|
|
MODULE_LICENSE("GPL");
|
2015-08-21 20:27:49 +00:00
|
|
|
*/
|