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linux-stable/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-27 06:55:01 +00:00
// SPDX-License-Identifier: GPL-2.0-or-later
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
/*
* Copyright (C) 2016 IBM Corp.
*/
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
pinctrl: aspeed: Read and write bits in LPC and GFX controllers The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:48 +00:00
#include <linux/mfd/syscon.h>
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/string.h>
#include <linux/types.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
/* Wrap some of the common macros for clarity */
#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
/*
* The "Multi-function Pins Mapping and Control" table in the SoC datasheet
* references registers by the device/offset mnemonic. The register macros
* below are named the same way to ease transcription and verification (as
* opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
* reference registers beyond those dedicated to pinmux, such as the system
* reset control and MAC clock configuration registers. The AST2500 goes a step
* further and references registers in the graphics IP block.
*/
#define SCU2C 0x2C /* Misc. Control Register */
#define SCU3C 0x3C /* System Reset Control/Status Register */
#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
#define SCU80 0x80 /* Multi-function Pin Control #1 */
#define SCU84 0x84 /* Multi-function Pin Control #2 */
#define SCU88 0x88 /* Multi-function Pin Control #3 */
#define SCU8C 0x8C /* Multi-function Pin Control #4 */
#define SCU90 0x90 /* Multi-function Pin Control #5 */
#define SCU94 0x94 /* Multi-function Pin Control #6 */
#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
#define SCUAC 0xAC /* Multi-function Pin Control #10 */
#define HW_STRAP2 0xD0 /* Strapping */
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
#define ASPEED_G5_NR_PINS 236
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed: Read and write bits in LPC and GFX controllers The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:48 +00:00
#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
/* LHCR0 is offset from the end of the H8S/2168-compatible registers */
pinctrl: aspeed-g5: Adapt to new LPC device tree layout Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-4-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-03-19 06:27:35 +00:00
#define LHCR0 0xa0
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define GFX064 0x64
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define B14 0
SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define D14 1
SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
#define D13 2
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SPI1CS1, D13);
FUNC_GROUP_DECL(TIMER3, D13);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E13 3
SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
#define C14 4
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(TIMER5, C14);
#define A13 5
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(TIMER6, A13);
FUNC_GROUP_DECL(I2C9, C14, A13);
#define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
#define C13 6
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(TIMER7, C13);
#define B13 7
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(TIMER8, B13);
FUNC_GROUP_DECL(MDIO2, C13, B13);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define K19 8
GPIO_PIN_DECL(K19, GPIOB0);
#define L19 9
GPIO_PIN_DECL(L19, GPIOB1);
#define L18 10
GPIO_PIN_DECL(L18, GPIOB2);
#define K18 11
GPIO_PIN_DECL(K18, GPIOB3);
#define J20 12
SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
#define H21 13
#define H21_DESC SIG_DESC_SET(SCU80, 13)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC);
SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LPCPD, H21);
FUNC_GROUP_DECL(LPCSMI, H21);
#define H22 14
SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define H20 15
GPIO_PIN_DECL(H20, GPIOB7);
#define SD1_DESC SIG_DESC_SET(SCU90, 0)
#define C12 16
#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define A12 17
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C10, C12, A12);
#define B12 18
#define I2C11_DESC SIG_DESC_SET(SCU90, 24)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D9 19
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C11, B12, D9);
#define D10 20
#define I2C12_DESC SIG_DESC_SET(SCU90, 25)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E12 21
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C12, D10, E12);
#define C11 22
#define I2C13_DESC SIG_DESC_SET(SCU90, 26)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define B11 23
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C13, C11, B11);
FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
#define SD2_DESC SIG_DESC_SET(SCU90, 1)
#define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
#define F19 24
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E21 25
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(GPID0, F19, E21);
#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
pinctrl: aspeed-g5: Fix names of GPID2 pins Fixes simple typos in the initial commit. There is no behavioural change. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Reported-by: Xo Wang <xow@google.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:14 +00:00
#define F20 26
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed-g5: Fix names of GPID2 pins Fixes simple typos in the initial commit. There is no behavioural change. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Reported-by: Xo Wang <xow@google.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:14 +00:00
#define D20 27
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed-g5: Fix names of GPID2 pins Fixes simple typos in the initial commit. There is no behavioural change. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Reported-by: Xo Wang <xow@google.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:14 +00:00
FUNC_GROUP_DECL(GPID2, F20, D20);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
#define D21 28
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define E20 29
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(GPID4, D21, E20);
#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
#define G18 30
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define C21 31
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(GPID6, G18, C21);
FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
#define B20 32
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NCTS3, B20);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define C20 33
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDCD3, C20);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(GPIE0, B20, C20);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
#define F18 34
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDSR3, F18);
#define F17 35
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRI3, F17);
FUNC_GROUP_DECL(GPIE2, F18, F17);
#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
#define E18 36
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDTR3, E18);
#define D19 37
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRTS3, D19);
FUNC_GROUP_DECL(GPIE4, E18, D19);
#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
#define A20 38
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(TXD3, A20);
#define B19 39
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(RXD3, B19);
FUNC_GROUP_DECL(GPIE6, A20, B19);
#define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0)
#define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
#define J19 40
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NCTS4, J19);
#define J18 41
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDCD4, J18);
#define B22 42
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDSR4, B22);
#define B21 43
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRI4, B21);
#define A21 44
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDTR4, A21);
#define H19 45
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRTS4, H19);
#define G17 46
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(TXD4, G17);
#define H18 47
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(H18, GPIOF7, LHRST, RXD4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(RXD4, H18);
FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
#define A19 48
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(A19, GPIOG0, SGPS1CK);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define E19 49
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(E19, GPIOG1, SGPS1LD);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define C19 50
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(C19, GPIOG2, SGPS1I0);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define E16 51
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(E16, GPIOG3, SGPS1I1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
#define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
#define E17 52
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT1, E17);
#define D16 53
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT2, D16);
#define D15 54
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT3, D15);
#define E14 55
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT4, E14);
FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
#define UART6_DESC SIG_DESC_SET(SCU90, 7)
#define A18 56
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define B18 57
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define D17 58
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define C17 59
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define A17 60
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define B17 61
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define A16 62
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(A16, GPIOH6, TXD6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define D18 63
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(D18, GPIOH7, RXD6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
pinctrl: aspeed: Read and write bits in LPC and GFX controllers The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:48 +00:00
#define SPI1_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
#define SPI1DEBUG_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
#define SPI1PASSTHRU_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define C18 64
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(C18, GPIOI0, SYSCS);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E15 65
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(E15, GPIOI1, SYSCK);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
#define B16 66
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(B16, GPIOI2, SYSMOSI);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define C16 67
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(C16, GPIOI3, SYSMISO);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
#define B15 68
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
SIG_EXPR_PTR(SPI1CS0, SPI1),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS);
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
#define C15 69
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
SIG_EXPR_PTR(SPI1CK, SPI1),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK);
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
#define A14 70
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1,
SIG_EXPR_PTR(SPI1MOSI, SPI1),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI);
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
#define A15 71
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1MISO, SPI1,
SIG_EXPR_PTR(SPI1MISO, SPI1),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO);
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
#define R2 72
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(R2, GPIOJ0, SGPMCK);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define L2 73
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(L2, GPIOJ1, SGPMLD);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define N3 74
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(N3, GPIOJ2, SGPMO);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define N4 75
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(N4, GPIOJ3, SGPMI);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
pinctrl: aspeed: Add SGPM pinmux Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-04 21:53:32 +00:00
FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define N5 76
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(VGAHS, N5);
#define R4 77
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(VGAVS, R4);
#define R3 78
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(DDCCLK, R3);
#define T3 79
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(DDCDAT, T3);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
#define L3 80
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(L3, GPIOK0, SCL5);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define L4 81
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(L4, GPIOK1, SDA5);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C5, L3, L4);
#define I2C6_DESC SIG_DESC_SET(SCU90, 19)
#define L1 82
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(L1, GPIOK2, SCL6);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define N2 83
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(N2, GPIOK3, SDA6);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C6, L1, N2);
#define I2C7_DESC SIG_DESC_SET(SCU90, 20)
#define N1 84
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(N1, GPIOK4, SCL7);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define P1 85
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(P1, GPIOK5, SDA7);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C7, N1, P1);
#define I2C8_DESC SIG_DESC_SET(SCU90, 21)
#define P2 86
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(P2, GPIOK6, SCL8);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define R1 87
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(R1, GPIOK7, SDA8);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C8, P2, R1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define T2 88
SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
pinctrl: aspeed: Read and write bits in LPC and GFX controllers The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:48 +00:00
#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
#define T1 89
#define T1_DESC SIG_DESC_SET(SCU84, 17)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDCD1, T1);
#define U1 90
#define U1_DESC SIG_DESC_SET(SCU84, 18)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDSR1, U1);
#define U2 91
#define U2_DESC SIG_DESC_SET(SCU84, 19)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRI1, U2);
#define P4 92
#define P4_DESC SIG_DESC_SET(SCU84, 20)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDTR1, P4);
#define P3 93
#define P3_DESC SIG_DESC_SET(SCU84, 21)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRTS1, P3);
#define V1 94
#define V1_DESC SIG_DESC_SET(SCU84, 22)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(TXD1, V1);
#define W1 95
#define W1_DESC SIG_DESC_SET(SCU84, 23)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(RXD1, W1);
#define Y1 96
#define Y1_DESC SIG_DESC_SET(SCU84, 24)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NCTS2, Y1);
#define AB2 97
#define AB2_DESC SIG_DESC_SET(SCU84, 25)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDCD2, AB2);
#define AA1 98
#define AA1_DESC SIG_DESC_SET(SCU84, 26)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDSR2, AA1);
#define Y2 99
#define Y2_DESC SIG_DESC_SET(SCU84, 27)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRI2, Y2);
#define AA2 100
#define AA2_DESC SIG_DESC_SET(SCU84, 28)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NDTR2, AA2);
#define P5 101
#define P5_DESC SIG_DESC_SET(SCU84, 29)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(NRTS2, P5);
#define R5 102
#define R5_DESC SIG_DESC_SET(SCU84, 30)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(TXD2, R5);
#define T5 103
#define T5_DESC SIG_DESC_SET(SCU84, 31)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(RXD2, T5);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define V2 104
#define V2_DESC SIG_DESC_SET(SCU88, 0)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(V2, GPION0, DASHN0, PWM0);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM0, V2);
#define W2 105
#define W2_DESC SIG_DESC_SET(SCU88, 1)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(W2, GPION1, DASHN1, PWM1);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM1, W2);
#define V3 106
#define V3_DESC SIG_DESC_SET(SCU88, 2)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(V3, GPION2, VPIG2, PWM2);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM2, V3);
#define U3 107
#define U3_DESC SIG_DESC_SET(SCU88, 3)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(U3, GPION3, VPIG3, PWM3);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM3, U3);
#define W3 108
#define W3_DESC SIG_DESC_SET(SCU88, 4)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(W3, GPION4, VPIG4, PWM4);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM4, W3);
#define AA3 109
#define AA3_DESC SIG_DESC_SET(SCU88, 5)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(AA3, GPION5, VPIG5, PWM5);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM5, AA3);
#define Y3 110
#define Y3_DESC SIG_DESC_SET(SCU88, 6)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(Y3, GPION6, VPIG6, PWM6);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM6, Y3);
#define T4 111
#define T4_DESC SIG_DESC_SET(SCU88, 7)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC);
SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(T4, GPION7, VPIG7, PWM7);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(PWM7, T4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define U5 112
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(U5, GPIOO0, VPIG8);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define U4 113
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(U4, GPIOO1, VPIG9);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define V5 114
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC,
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
SIG_DESC_SET(SCU88, 10));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(V5, GPIOO2, DASHV5);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define AB4 115
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
SIG_DESC_SET(SCU88, 11));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(AB4, GPIOO3, DASHAB4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define AB3 116
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 12), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(AB3, GPIOO4, VPIR2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define Y4 117
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 13), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(Y4, GPIOO5, VPIR3);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define AA4 118
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 14), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(AA4, GPIOO6, VPIR4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define W4 119
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 15), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(W4, GPIOO7, VPIR5);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define V4 120
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 16), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(V4, GPIOP0, VPIR6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define W5 121
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 17), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(W5, GPIOP1, VPIR7);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define AA5 122
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 18), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(AA5, GPIOP2, VPIR8);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define AB5 123
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 19), COND2);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(AB5, GPIOP3, VPIR9);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
AB5);
#define Y6 124
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
SIG_DESC_SET(SCU88, 20));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(Y6, GPIOP4, DASHY6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define Y5 125
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
SIG_DESC_SET(SCU88, 21));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(Y5, GPIOP5, DASHY5);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define W6 126
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
SIG_DESC_SET(SCU88, 22));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(W6, GPIOP6, DASHW6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define V6 127
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
SIG_DESC_SET(SCU88, 23));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(V6, GPIOP7, DASHV6);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
#define A11 128
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(A11, GPIOQ0, SCL3);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define A10 129
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(A10, GPIOQ1, SDA3);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C3, A11, A10);
#define I2C4_DESC SIG_DESC_SET(SCU90, 17)
#define A9 130
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(A9, GPIOQ2, SCL4);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define B9 131
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(B9, GPIOQ3, SDA4);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C4, A9, B9);
#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
#define N21 132
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(N21, GPIOQ4, SCL14);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define N22 133
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(N22, GPIOQ5, SDA14);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(I2C14, N21, N22);
#define B10 134
SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
#define N20 135
SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define AA19 136
SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
#define T19 137
SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
#define T17 138
SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
#define Y19 139
SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
#define W19 140
SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
#define V19 141
SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D8 142
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(D8, GPIOR6, MDC1);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E10 143
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(E10, GPIOR7, MDIO1);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(MDIO1, D8, E10);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
#define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
#define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
#define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7)
#define V20 144
#define V20_DESC SIG_DESC_SET(SCU8C, 0)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB2, VPO,
SIG_EXPR_PTR(VPOB2, VPO),
SIG_EXPR_PTR(VPOB2, VPOOFF1),
SIG_EXPR_PTR(VPOB2, VPOOFF2));
SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO);
SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SPI2CS1, V20);
#define U19 145
#define U19_DESC SIG_DESC_SET(SCU8C, 1)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB3, VPO,
SIG_EXPR_PTR(VPOB3, VPO),
SIG_EXPR_PTR(VPOB3, VPOOFF1),
SIG_EXPR_PTR(VPOB3, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO);
SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(BMCINT, U19);
#define R18 146
#define R18_DESC SIG_DESC_SET(SCU8C, 2)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB4, VPO,
SIG_EXPR_PTR(VPOB4, VPO),
SIG_EXPR_PTR(VPOB4, VPOOFF1),
SIG_EXPR_PTR(VPOB4, VPOOFF2));
SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO);
SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT5, R18);
#define P18 147
#define P18_DESC SIG_DESC_SET(SCU8C, 3)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB5, VPO,
SIG_EXPR_PTR(VPOB5, VPO),
SIG_EXPR_PTR(VPOB5, VPOOFF1),
SIG_EXPR_PTR(VPOB5, VPOOFF2));
SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO);
SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT6, P18);
#define R19 148
#define R19_DESC SIG_DESC_SET(SCU8C, 4)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB6, VPO,
SIG_EXPR_PTR(VPOB6, VPO),
SIG_EXPR_PTR(VPOB6, VPOOFF1),
SIG_EXPR_PTR(VPOB6, VPOOFF2));
SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(R19, GPIOS4, VPOB6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define W20 149
#define W20_DESC SIG_DESC_SET(SCU8C, 5)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB7, VPO,
SIG_EXPR_PTR(VPOB7, VPO),
SIG_EXPR_PTR(VPOB7, VPOOFF1),
SIG_EXPR_PTR(VPOB7, VPOOFF2));
SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(W20, GPIOS5, VPOB7);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define U20 150
#define U20_DESC SIG_DESC_SET(SCU8C, 6)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB8, VPO,
SIG_EXPR_PTR(VPOB8, VPO),
SIG_EXPR_PTR(VPOB8, VPOOFF1),
SIG_EXPR_PTR(VPOB8, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(U20, GPIOS6, VPOB8);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define AA20 151
#define AA20_DESC SIG_DESC_SET(SCU8C, 7)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB9, VPO,
SIG_EXPR_PTR(VPOB9, VPO),
SIG_EXPR_PTR(VPOB9, VPOOFF1),
SIG_EXPR_PTR(VPOB9, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_1(AA20, GPIOS7, VPOB9);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
/* RGMII1/RMII1 */
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
#define B5 152
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC,
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
SIG_DESC_SET(SCU48, 29));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1);
PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO),
SIG_EXPR_LIST_PTR(B5, RGMII1TXCK));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E9 153
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1);
PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN),
SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define F9 154
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1);
PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0),
SIG_EXPR_LIST_PTR(F9, RGMII1TXD0));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define A5 155
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1);
PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1),
SIG_EXPR_LIST_PTR(A5, RGMII1TXD1));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E7 156
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1);
PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0),
SIG_EXPR_LIST_PTR(E7, RGMII1TXD2));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D7 157
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1);
PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1),
SIG_EXPR_LIST_PTR(D7, RGMII1TXD3));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define B2 158
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC,
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
SIG_DESC_SET(SCU48, 30));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2);
PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO),
SIG_EXPR_LIST_PTR(B2, RGMII2TXCK));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define B1 159
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2);
PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN),
SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define A2 160
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2);
PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0),
SIG_EXPR_LIST_PTR(A2, RGMII2TXD0));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define B3 161
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2);
PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1),
SIG_EXPR_LIST_PTR(B3, RGMII2TXD1));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D5 162
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2);
PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0),
SIG_EXPR_LIST_PTR(D5, RGMII2TXD2));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D4 163
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2);
PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1),
SIG_EXPR_LIST_PTR(D4, RGMII2TXD3));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define B4 164
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1);
PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI),
SIG_EXPR_LIST_PTR(B4, RGMII1RXCK));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define A4 165
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1);
PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2),
SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define A3 166
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1);
PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0),
SIG_EXPR_LIST_PTR(A3, RGMII1RXD0));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D6 167
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1);
PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1),
SIG_EXPR_LIST_PTR(D6, RGMII1RXD1));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define C5 168
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1);
PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV),
SIG_EXPR_LIST_PTR(C5, RGMII1RXD2));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define C4 169
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1);
PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER),
SIG_EXPR_LIST_PTR(C4, RGMII1RXD3));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
#define C2 170
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2);
PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI),
SIG_EXPR_LIST_PTR(C2, RGMII2RXCK));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define C1 171
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2);
PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2),
SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define C3 172
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2);
PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0),
SIG_EXPR_LIST_PTR(C3, RGMII2RXD0));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D1 173
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2);
PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1),
SIG_EXPR_LIST_PTR(D1, RGMII2RXD1));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define D2 174
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2);
PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV),
SIG_EXPR_LIST_PTR(D2, RGMII2RXD2));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
#define E6 175
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2);
PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER),
SIG_EXPR_LIST_PTR(E6, RGMII2RXD3));
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define F4 176
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0);
PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC0, F4);
#define F5 177
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1);
PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC1, F5);
#define E2 178
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2);
PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC2, E2);
#define E1 179
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3);
PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC3, E1);
#define F3 180
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4);
PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC4, F3);
#define E3 181
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5);
PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC5, E3);
#define G5 182
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6);
PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC6, G5);
#define G4 183
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7);
PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC7, G4);
#define F2 184
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8);
PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC8, F2);
#define G3 185
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9);
PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC9, G3);
#define G2 186
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10);
PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC10, G2);
#define F1 187
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11);
PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC11, F1);
#define H5 188
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12);
PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC12, H5);
#define G1 189
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13);
PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC13, G1);
#define H3 190
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14);
PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC14, H3);
#define H4 191
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15);
PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(ADC15, H4);
#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
#define R22 192
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOS3, R22);
#define R21 193
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOS5, R21);
#define P22 194
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOPWREQ, P22);
#define P21 195
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOONCTRL, P21);
#define M18 196
SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
#define M19 197
SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
#define M20 198
SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
#define P20 199
SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
#define PNOR_DESC SIG_DESC_SET(SCU90, 31)
#define Y20 200
#define Y20_DESC SIG_DESC_SET(SCUA4, 16)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG2, VPO,
SIG_EXPR_PTR(VPOG2, VPO),
SIG_EXPR_PTR(VPOG2, VPOOFF1),
SIG_EXPR_PTR(VPOG2, VPOOFF2));
SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO);
SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC);
SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC);
SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0);
PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI),
SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOPBI, Y20);
#define AB20 201
#define AB20_DESC SIG_DESC_SET(SCUA4, 17)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG3, VPO,
SIG_EXPR_PTR(VPOG3, VPO),
SIG_EXPR_PTR(VPOG3, VPOOFF1),
SIG_EXPR_PTR(VPOG3, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO);
SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC);
SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC);
SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1);
PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3),
SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1),
SIG_EXPR_LIST_PTR(AB20, GPIOZ1));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOPWRGD, AB20);
#define AB21 202
#define AB21_DESC SIG_DESC_SET(SCUA4, 18)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG4, VPO,
SIG_EXPR_PTR(VPOG4, VPO),
SIG_EXPR_PTR(VPOG4, VPOOFF1),
SIG_EXPR_PTR(VPOG4, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO);
SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC);
SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC);
SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2);
PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4),
SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2),
SIG_EXPR_LIST_PTR(AB21, GPIOZ2));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOPBO, AB21);
#define AA21 203
#define AA21_DESC SIG_DESC_SET(SCUA4, 19)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG5, VPO,
SIG_EXPR_PTR(VPOG5, VPO),
SIG_EXPR_PTR(VPOG5, VPOOFF1),
SIG_EXPR_PTR(VPOG5, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO);
SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC);
SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC);
SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3);
PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5),
SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3),
SIG_EXPR_LIST_PTR(AA21, GPIOZ3));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SIOSCI, AA21);
FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
/* CRT DVO disabled, configured for single-edge mode */
#define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
/* CRT DVO disabled, configured for dual-edge mode */
#define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
/* CRT DVO enabled, configured for single-edge mode */
#define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
/* CRT DVO enabled, configured for dual-edge mode */
#define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
#define U21 204
#define U21_DESC SIG_DESC_SET(SCUA4, 20)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG6, VPO,
SIG_EXPR_PTR(VPOG6, VPO),
SIG_EXPR_PTR(VPOG6, VPOOFF1),
SIG_EXPR_PTR(VPOG6, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO);
SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define W22 205
#define W22_DESC SIG_DESC_SET(SCUA4, 21)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG7, VPO,
SIG_EXPR_PTR(VPOG7, VPO),
SIG_EXPR_PTR(VPOG7, VPOOFF1),
SIG_EXPR_PTR(VPOG7, VPOOFF2));
SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO);
SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define V22 206
#define V22_DESC SIG_DESC_SET(SCUA4, 22)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG8, VPO,
SIG_EXPR_PTR(VPOG8, VPO),
SIG_EXPR_PTR(VPOG8, VPOOFF1),
SIG_EXPR_PTR(VPOG8, VPOOFF2));
SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO);
SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define W21 207
#define W21_DESC SIG_DESC_SET(SCUA4, 23)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG9, VPO,
SIG_EXPR_PTR(VPOG9, VPO),
SIG_EXPR_PTR(VPOG9, VPOOFF1),
SIG_EXPR_PTR(VPOG9, VPOOFF2));
SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO);
SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define Y21 208
#define Y21_DESC SIG_DESC_SET(SCUA4, 24)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR2, VPO,
SIG_EXPR_PTR(VPOR2, VPO),
SIG_EXPR_PTR(VPOR2, VPOOFF1),
SIG_EXPR_PTR(VPOR2, VPOOFF2));
SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO);
SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0);
PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7),
SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT7, Y21);
#define V21 209
#define V21_DESC SIG_DESC_SET(SCUA4, 25)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR3, VPO,
SIG_EXPR_PTR(VPOR3, VPO),
SIG_EXPR_PTR(VPOR3, VPOOFF1),
SIG_EXPR_PTR(VPOR3, VPOOFF2));
SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO);
SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1);
PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8),
SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT8, V21);
#define Y22 210
#define Y22_DESC SIG_DESC_SET(SCUA4, 26)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR4, VPO,
SIG_EXPR_PTR(VPOR4, VPO),
SIG_EXPR_PTR(VPOR4, VPOOFF1),
SIG_EXPR_PTR(VPOR4, VPOOFF2));
SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO);
SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2);
PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9),
SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT9, Y22);
#define AA22 211
#define AA22_DESC SIG_DESC_SET(SCUA4, 27)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR5, VPO,
SIG_EXPR_PTR(VPOR5, VPO),
SIG_EXPR_PTR(VPOR5, VPOOFF1),
SIG_EXPR_PTR(VPOR5, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO);
SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3);
PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5),
SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3),
SIG_EXPR_LIST_PTR(AA22, GPIOAA3));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT10, AA22);
#define U22 212
#define U22_DESC SIG_DESC_SET(SCUA4, 28)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR6, VPO,
SIG_EXPR_PTR(VPOR6, VPO),
SIG_EXPR_PTR(VPOR6, VPOOFF1),
SIG_EXPR_PTR(VPOR6, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO);
SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC);
SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4);
PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11),
SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT11, U22);
#define T20 213
#define T20_DESC SIG_DESC_SET(SCUA4, 29)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR7, VPO,
SIG_EXPR_PTR(VPOR7, VPO),
SIG_EXPR_PTR(VPOR7, VPOOFF1),
SIG_EXPR_PTR(VPOR7, VPOOFF2));
SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO);
SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC);
SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5);
PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12),
SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT12, T20);
#define N18 214
#define N18_DESC SIG_DESC_SET(SCUA4, 30)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR8, VPO,
SIG_EXPR_PTR(VPOR8, VPO),
SIG_EXPR_PTR(VPOR8, VPOOFF1),
SIG_EXPR_PTR(VPOR8, VPOOFF2));
SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO);
SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC);
SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6);
PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13),
SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT13, N18);
#define P19 215
#define P19_DESC SIG_DESC_SET(SCUA4, 31)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR9, VPO,
SIG_EXPR_PTR(VPOR9, VPO),
SIG_EXPR_PTR(VPOR9, VPOOFF1),
SIG_EXPR_PTR(VPOR9, VPOOFF2));
SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO);
SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC);
SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7);
PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14),
SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7));
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(SALT14, P19);
#define N19 216
#define N19_DESC SIG_DESC_SET(SCUA8, 0)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPODE, VPO,
SIG_EXPR_PTR(VPODE, VPO),
SIG_EXPR_PTR(VPODE, VPOOFF1),
SIG_EXPR_PTR(VPODE, VPOOFF2));
SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO);
SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
#define T21 217
#define T21_DESC SIG_DESC_SET(SCUA8, 1)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOHS, VPO,
SIG_EXPR_PTR(VPOHS, VPO),
SIG_EXPR_PTR(VPOHS, VPOOFF1),
SIG_EXPR_PTR(VPOHS, VPOOFF2));
SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO);
SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
AA22, U22, T20, N18, P19, N19, T21);
#define T22 218
#define T22_DESC SIG_DESC_SET(SCUA8, 2)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOVS, VPO,
SIG_EXPR_PTR(VPOVS, VPO),
SIG_EXPR_PTR(VPOVS, VPOOFF1),
SIG_EXPR_PTR(VPOVS, VPOOFF2));
SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO);
SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(WDTRST1, T22);
#define R20 219
#define R20_DESC SIG_DESC_SET(SCUA8, 3)
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOCLK, VPO,
SIG_EXPR_PTR(VPOCLK, VPO),
SIG_EXPR_PTR(VPOCLK, VPOOFF1),
SIG_EXPR_PTR(VPOCLK, VPOOFF2));
SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO);
SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC);
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(WDTRST2, R20);
FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
N18, P19, N19, T21, T22, R20);
#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
#define G21 224
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LAD0, G21);
#define G20 225
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LAD1, G20);
#define D22 226
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LAD2, D22);
#define E22 227
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LAD3, E22);
#define C22 228
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LCLK, C22);
#define F21 229
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LFRAME, F21);
#define F22 230
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LSIRQ, F22);
#define G22 231
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
pinctrl: aspeed: Rename pin declaration macros Rename macros as follows: * s/SS_PIN_DECL()/PIN_DECL_1()/ * s/MS_PIN_DECL()/PIN_DECL_2()/ * s/MS_PIN_DECL_()/PIN_DECL_()/ This is in preparation for adding PIN_DECL_3(). We could clean this up with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far given how much of a macro jungle we already have. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:00 +00:00
PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST);
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
FUNC_GROUP_DECL(LPCRST, G22);
FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
#define A7 232
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP));
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
#define A8 233
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN));
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
FUNC_GROUP_DECL(USB2AH, A7, A8);
FUNC_GROUP_DECL(USB2AD, A7, A8);
#define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
#define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
#define B6 234
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH,
SIG_EXPR_PTR(USB2BHDP1, USB2BH),
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
SIG_EXPR_PTR(USB2BHDP2, USB2BH));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH);
PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP),
SIG_EXPR_LIST_PTR(B6, USB2BHDP));
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
#define A6 235
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH,
SIG_EXPR_PTR(USB2BHDN1, USB2BH),
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
SIG_EXPR_PTR(USB2BHDN2, USB2BH));
pinctrl: aspeed: Add multiple pin group support for functions The AST2400 and AST2500 SoCs only exposed one pin group per function. Lone pin groups drove some implementation simplifications in the ASPEED pinmux infrastructure that is now invalid for the AST2600, which supports multiple groups per function for some functions on the chip (SMBus Alert pins and UARTs among others). This patch reworks the macro jungle to enable support for multiple pin groups. In the process we inflict some collateral damage on the existing AST2400 and AST2500 drivers, but the rework is mostly a relatively straight-forward, automated transform of adding the pin name as an argument to some macro calls and implementing wrappers to paper over groups in the cases where there aren't multiple. As previously documented, the macro infrastructure exposes mux configuration as symbols in the source file which are used to detect accidental duplication. Previously these symbols were named in terms of the signal for a given expression. As the AST2600 supports multiple pin groups for a function, the signal name on its own is no-longer unique, and we must switch to the (signal, group) tuple. However, this means that we can no-longer derive the signal expression symbol name from the signal name alone, which among other cases, impacts the operation of the PIN_DECL_x() macros. To fix that and avoid requiring we awkwardly provide the associated group name for every signal for every PIN_DECL_x() invocation, instead opportunistically alias the name of the signal expression symbol from the unique (signal, group) tuple to the also unique (pin, signal) tuple, then reference the alias symbol in the tables generated by PIN_DECL_x(). This way we do not require extra group parameters for PIN_DECL_x() as the pin name was already provided as an argument, and instead simply require that the pin name be provided to the expression declaration macros in order to generate the alias symbol. The patch implements the alias strategy and fixes up all the expression definition macro calls in the AST2400 and AST2500 drivers to account for pin groups. Given the implementation strategy has the property that compilation either fails or loudly warns for bad pin descriptions, this patch is theoretically tested by successfully compiling both affected drivers. For a more practical test I've inspected the diff of the content of the pinctrl debugfs entries before and after the patch under qemu; all pins, functions and groups match. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 05:56:02 +00:00
SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH);
PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN),
SIG_EXPR_LIST_PTR(A6, USB2BHDN));
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
FUNC_GROUP_DECL(USB11BHID, B6, A6);
FUNC_GROUP_DECL(USB2BD, B6, A6);
FUNC_GROUP_DECL(USB2BH, B6, A6);
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A10),
ASPEED_PINCTRL_PIN(A11),
ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13),
ASPEED_PINCTRL_PIN(A14),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
ASPEED_PINCTRL_PIN(A15),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(A16),
ASPEED_PINCTRL_PIN(A17),
ASPEED_PINCTRL_PIN(A18),
ASPEED_PINCTRL_PIN(A19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(A2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(A20),
ASPEED_PINCTRL_PIN(A21),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(A7),
ASPEED_PINCTRL_PIN(A8),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(A9),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(AA1),
ASPEED_PINCTRL_PIN(AA19),
ASPEED_PINCTRL_PIN(AA2),
ASPEED_PINCTRL_PIN(AA20),
ASPEED_PINCTRL_PIN(AA21),
ASPEED_PINCTRL_PIN(AA22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(AA3),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(AA4),
ASPEED_PINCTRL_PIN(AA5),
ASPEED_PINCTRL_PIN(AB2),
ASPEED_PINCTRL_PIN(AB20),
ASPEED_PINCTRL_PIN(AB21),
ASPEED_PINCTRL_PIN(AB3),
ASPEED_PINCTRL_PIN(AB4),
ASPEED_PINCTRL_PIN(AB5),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
ASPEED_PINCTRL_PIN(B12),
ASPEED_PINCTRL_PIN(B13),
ASPEED_PINCTRL_PIN(B14),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
ASPEED_PINCTRL_PIN(B15),
ASPEED_PINCTRL_PIN(B16),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(B17),
ASPEED_PINCTRL_PIN(B18),
ASPEED_PINCTRL_PIN(B19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B20),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(B21),
ASPEED_PINCTRL_PIN(B22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B5),
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
ASPEED_PINCTRL_PIN(B6),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(B9),
ASPEED_PINCTRL_PIN(C1),
ASPEED_PINCTRL_PIN(C11),
ASPEED_PINCTRL_PIN(C12),
ASPEED_PINCTRL_PIN(C13),
ASPEED_PINCTRL_PIN(C14),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
ASPEED_PINCTRL_PIN(C15),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(C16),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(C17),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(C18),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(C19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(C2),
ASPEED_PINCTRL_PIN(C20),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(C21),
ASPEED_PINCTRL_PIN(C22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(D1),
ASPEED_PINCTRL_PIN(D10),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(D13),
ASPEED_PINCTRL_PIN(D14),
ASPEED_PINCTRL_PIN(D15),
ASPEED_PINCTRL_PIN(D16),
ASPEED_PINCTRL_PIN(D17),
ASPEED_PINCTRL_PIN(D18),
ASPEED_PINCTRL_PIN(D19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D20),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(D21),
ASPEED_PINCTRL_PIN(D22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
ASPEED_PINCTRL_PIN(D8),
ASPEED_PINCTRL_PIN(D9),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(E1),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E12),
ASPEED_PINCTRL_PIN(E13),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(E14),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(E15),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(E16),
ASPEED_PINCTRL_PIN(E17),
ASPEED_PINCTRL_PIN(E18),
ASPEED_PINCTRL_PIN(E19),
ASPEED_PINCTRL_PIN(E2),
ASPEED_PINCTRL_PIN(E20),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(E21),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(E22),
ASPEED_PINCTRL_PIN(E3),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
ASPEED_PINCTRL_PIN(E9),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(F1),
ASPEED_PINCTRL_PIN(F17),
ASPEED_PINCTRL_PIN(F18),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(F19),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(F2),
pinctrl: aspeed-g5: Fix names of GPID2 pins Fixes simple typos in the initial commit. There is no behavioural change. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Reported-by: Xo Wang <xow@google.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:14 +00:00
ASPEED_PINCTRL_PIN(F20),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(F21),
ASPEED_PINCTRL_PIN(F22),
ASPEED_PINCTRL_PIN(F3),
ASPEED_PINCTRL_PIN(F4),
ASPEED_PINCTRL_PIN(F5),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(F9),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(G1),
ASPEED_PINCTRL_PIN(G17),
ASPEED_PINCTRL_PIN(G18),
ASPEED_PINCTRL_PIN(G2),
ASPEED_PINCTRL_PIN(G20),
ASPEED_PINCTRL_PIN(G21),
ASPEED_PINCTRL_PIN(G22),
ASPEED_PINCTRL_PIN(G3),
ASPEED_PINCTRL_PIN(G4),
ASPEED_PINCTRL_PIN(G5),
ASPEED_PINCTRL_PIN(H18),
ASPEED_PINCTRL_PIN(H19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(H20),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(H21),
ASPEED_PINCTRL_PIN(H22),
ASPEED_PINCTRL_PIN(H3),
ASPEED_PINCTRL_PIN(H4),
ASPEED_PINCTRL_PIN(H5),
ASPEED_PINCTRL_PIN(J18),
ASPEED_PINCTRL_PIN(J19),
ASPEED_PINCTRL_PIN(J20),
ASPEED_PINCTRL_PIN(K18),
ASPEED_PINCTRL_PIN(K19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(L1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(L18),
ASPEED_PINCTRL_PIN(L19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(L2),
ASPEED_PINCTRL_PIN(L3),
ASPEED_PINCTRL_PIN(L4),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(M18),
ASPEED_PINCTRL_PIN(M19),
ASPEED_PINCTRL_PIN(M20),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(N1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(N18),
ASPEED_PINCTRL_PIN(N19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(N2),
ASPEED_PINCTRL_PIN(N20),
ASPEED_PINCTRL_PIN(N21),
ASPEED_PINCTRL_PIN(N22),
ASPEED_PINCTRL_PIN(N3),
ASPEED_PINCTRL_PIN(N4),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(N5),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(P1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(P18),
ASPEED_PINCTRL_PIN(P19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(P2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(P20),
ASPEED_PINCTRL_PIN(P21),
ASPEED_PINCTRL_PIN(P22),
ASPEED_PINCTRL_PIN(P3),
ASPEED_PINCTRL_PIN(P4),
ASPEED_PINCTRL_PIN(P5),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(R1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(R18),
ASPEED_PINCTRL_PIN(R19),
ASPEED_PINCTRL_PIN(R2),
ASPEED_PINCTRL_PIN(R20),
ASPEED_PINCTRL_PIN(R21),
ASPEED_PINCTRL_PIN(R22),
ASPEED_PINCTRL_PIN(R3),
ASPEED_PINCTRL_PIN(R4),
ASPEED_PINCTRL_PIN(R5),
ASPEED_PINCTRL_PIN(T1),
ASPEED_PINCTRL_PIN(T17),
ASPEED_PINCTRL_PIN(T19),
ASPEED_PINCTRL_PIN(T2),
ASPEED_PINCTRL_PIN(T20),
ASPEED_PINCTRL_PIN(T21),
ASPEED_PINCTRL_PIN(T22),
ASPEED_PINCTRL_PIN(T3),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(T4),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(T5),
ASPEED_PINCTRL_PIN(U1),
ASPEED_PINCTRL_PIN(U19),
ASPEED_PINCTRL_PIN(U2),
ASPEED_PINCTRL_PIN(U20),
ASPEED_PINCTRL_PIN(U21),
ASPEED_PINCTRL_PIN(U22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(U3),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(U4),
ASPEED_PINCTRL_PIN(U5),
ASPEED_PINCTRL_PIN(V1),
ASPEED_PINCTRL_PIN(V19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(V2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(V20),
ASPEED_PINCTRL_PIN(V21),
ASPEED_PINCTRL_PIN(V22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(V3),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(V4),
ASPEED_PINCTRL_PIN(V5),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(V6),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(W1),
ASPEED_PINCTRL_PIN(W19),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(W2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(W20),
ASPEED_PINCTRL_PIN(W21),
ASPEED_PINCTRL_PIN(W22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(W3),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(W4),
ASPEED_PINCTRL_PIN(W5),
ASPEED_PINCTRL_PIN(W6),
ASPEED_PINCTRL_PIN(Y1),
ASPEED_PINCTRL_PIN(Y19),
ASPEED_PINCTRL_PIN(Y2),
ASPEED_PINCTRL_PIN(Y20),
ASPEED_PINCTRL_PIN(Y21),
ASPEED_PINCTRL_PIN(Y22),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_PIN(Y3),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_PIN(Y4),
ASPEED_PINCTRL_PIN(Y5),
ASPEED_PINCTRL_PIN(Y6),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
};
static const struct aspeed_pin_group aspeed_g5_groups[] = {
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(ACPI),
ASPEED_PINCTRL_GROUP(ADC0),
ASPEED_PINCTRL_GROUP(ADC1),
ASPEED_PINCTRL_GROUP(ADC10),
ASPEED_PINCTRL_GROUP(ADC11),
ASPEED_PINCTRL_GROUP(ADC12),
ASPEED_PINCTRL_GROUP(ADC13),
ASPEED_PINCTRL_GROUP(ADC14),
ASPEED_PINCTRL_GROUP(ADC15),
ASPEED_PINCTRL_GROUP(ADC2),
ASPEED_PINCTRL_GROUP(ADC3),
ASPEED_PINCTRL_GROUP(ADC4),
ASPEED_PINCTRL_GROUP(ADC5),
ASPEED_PINCTRL_GROUP(ADC6),
ASPEED_PINCTRL_GROUP(ADC7),
ASPEED_PINCTRL_GROUP(ADC8),
ASPEED_PINCTRL_GROUP(ADC9),
ASPEED_PINCTRL_GROUP(BMCINT),
ASPEED_PINCTRL_GROUP(DDCCLK),
ASPEED_PINCTRL_GROUP(DDCDAT),
ASPEED_PINCTRL_GROUP(ESPI),
ASPEED_PINCTRL_GROUP(FWSPICS1),
ASPEED_PINCTRL_GROUP(FWSPICS2),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(GPID0),
ASPEED_PINCTRL_GROUP(GPID2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(GPID4),
ASPEED_PINCTRL_GROUP(GPID6),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(GPIE0),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(GPIE2),
ASPEED_PINCTRL_GROUP(GPIE4),
ASPEED_PINCTRL_GROUP(GPIE6),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(I2C10),
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
ASPEED_PINCTRL_GROUP(I2C13),
ASPEED_PINCTRL_GROUP(I2C14),
ASPEED_PINCTRL_GROUP(I2C3),
ASPEED_PINCTRL_GROUP(I2C4),
ASPEED_PINCTRL_GROUP(I2C5),
ASPEED_PINCTRL_GROUP(I2C6),
ASPEED_PINCTRL_GROUP(I2C7),
ASPEED_PINCTRL_GROUP(I2C8),
ASPEED_PINCTRL_GROUP(I2C9),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(LAD0),
ASPEED_PINCTRL_GROUP(LAD1),
ASPEED_PINCTRL_GROUP(LAD2),
ASPEED_PINCTRL_GROUP(LAD3),
ASPEED_PINCTRL_GROUP(LCLK),
ASPEED_PINCTRL_GROUP(LFRAME),
ASPEED_PINCTRL_GROUP(LPCHC),
ASPEED_PINCTRL_GROUP(LPCPD),
ASPEED_PINCTRL_GROUP(LPCPLUS),
ASPEED_PINCTRL_GROUP(LPCPME),
ASPEED_PINCTRL_GROUP(LPCRST),
ASPEED_PINCTRL_GROUP(LPCSMI),
ASPEED_PINCTRL_GROUP(LSIRQ),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(MAC1LINK),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(MAC2LINK),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(NCTS1),
ASPEED_PINCTRL_GROUP(NCTS2),
ASPEED_PINCTRL_GROUP(NCTS3),
ASPEED_PINCTRL_GROUP(NCTS4),
ASPEED_PINCTRL_GROUP(NDCD1),
ASPEED_PINCTRL_GROUP(NDCD2),
ASPEED_PINCTRL_GROUP(NDCD3),
ASPEED_PINCTRL_GROUP(NDCD4),
ASPEED_PINCTRL_GROUP(NDSR1),
ASPEED_PINCTRL_GROUP(NDSR2),
ASPEED_PINCTRL_GROUP(NDSR3),
ASPEED_PINCTRL_GROUP(NDSR4),
ASPEED_PINCTRL_GROUP(NDTR1),
ASPEED_PINCTRL_GROUP(NDTR2),
ASPEED_PINCTRL_GROUP(NDTR3),
ASPEED_PINCTRL_GROUP(NDTR4),
ASPEED_PINCTRL_GROUP(NRI1),
ASPEED_PINCTRL_GROUP(NRI2),
ASPEED_PINCTRL_GROUP(NRI3),
ASPEED_PINCTRL_GROUP(NRI4),
ASPEED_PINCTRL_GROUP(NRTS1),
ASPEED_PINCTRL_GROUP(NRTS2),
ASPEED_PINCTRL_GROUP(NRTS3),
ASPEED_PINCTRL_GROUP(NRTS4),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PEWAKE),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(PNOR),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM2),
ASPEED_PINCTRL_GROUP(PWM3),
ASPEED_PINCTRL_GROUP(PWM4),
ASPEED_PINCTRL_GROUP(PWM5),
ASPEED_PINCTRL_GROUP(PWM6),
ASPEED_PINCTRL_GROUP(PWM7),
ASPEED_PINCTRL_GROUP(RGMII1),
ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RMII1),
ASPEED_PINCTRL_GROUP(RMII2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(RXD1),
ASPEED_PINCTRL_GROUP(RXD2),
ASPEED_PINCTRL_GROUP(RXD3),
ASPEED_PINCTRL_GROUP(RXD4),
ASPEED_PINCTRL_GROUP(SALT1),
ASPEED_PINCTRL_GROUP(SALT10),
ASPEED_PINCTRL_GROUP(SALT11),
ASPEED_PINCTRL_GROUP(SALT12),
ASPEED_PINCTRL_GROUP(SALT13),
ASPEED_PINCTRL_GROUP(SALT14),
ASPEED_PINCTRL_GROUP(SALT2),
ASPEED_PINCTRL_GROUP(SALT3),
ASPEED_PINCTRL_GROUP(SALT4),
ASPEED_PINCTRL_GROUP(SALT5),
ASPEED_PINCTRL_GROUP(SALT6),
ASPEED_PINCTRL_GROUP(SALT7),
ASPEED_PINCTRL_GROUP(SALT8),
ASPEED_PINCTRL_GROUP(SALT9),
ASPEED_PINCTRL_GROUP(SCL1),
ASPEED_PINCTRL_GROUP(SCL2),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(SD1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(SD2),
ASPEED_PINCTRL_GROUP(SDA1),
ASPEED_PINCTRL_GROUP(SDA2),
pinctrl: aspeed: Add SGPM pinmux Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-04 21:53:32 +00:00
ASPEED_PINCTRL_GROUP(SGPM),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(SGPS1),
ASPEED_PINCTRL_GROUP(SGPS2),
ASPEED_PINCTRL_GROUP(SIOONCTRL),
ASPEED_PINCTRL_GROUP(SIOPBI),
ASPEED_PINCTRL_GROUP(SIOPBO),
ASPEED_PINCTRL_GROUP(SIOPWREQ),
ASPEED_PINCTRL_GROUP(SIOPWRGD),
ASPEED_PINCTRL_GROUP(SIOS3),
ASPEED_PINCTRL_GROUP(SIOS5),
ASPEED_PINCTRL_GROUP(SIOSCI),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(SPI1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(SPI1CS1),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(SPI2CK),
ASPEED_PINCTRL_GROUP(SPI2CS0),
ASPEED_PINCTRL_GROUP(SPI2CS1),
ASPEED_PINCTRL_GROUP(SPI2MISO),
ASPEED_PINCTRL_GROUP(SPI2MOSI),
ASPEED_PINCTRL_GROUP(TIMER3),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(TXD1),
ASPEED_PINCTRL_GROUP(TXD2),
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
ASPEED_PINCTRL_GROUP(USB11BHID),
ASPEED_PINCTRL_GROUP(USB2AD),
ASPEED_PINCTRL_GROUP(USB2AH),
ASPEED_PINCTRL_GROUP(USB2BD),
ASPEED_PINCTRL_GROUP(USB2BH),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(USBCKI),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
ASPEED_PINCTRL_GROUP(VGABIOSROM),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_GROUP(VGAHS),
ASPEED_PINCTRL_GROUP(VGAVS),
ASPEED_PINCTRL_GROUP(VPI24),
ASPEED_PINCTRL_GROUP(VPO),
ASPEED_PINCTRL_GROUP(WDTRST1),
ASPEED_PINCTRL_GROUP(WDTRST2),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
};
static const struct aspeed_pin_function aspeed_g5_functions[] = {
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(ACPI),
ASPEED_PINCTRL_FUNC(ADC0),
ASPEED_PINCTRL_FUNC(ADC1),
ASPEED_PINCTRL_FUNC(ADC10),
ASPEED_PINCTRL_FUNC(ADC11),
ASPEED_PINCTRL_FUNC(ADC12),
ASPEED_PINCTRL_FUNC(ADC13),
ASPEED_PINCTRL_FUNC(ADC14),
ASPEED_PINCTRL_FUNC(ADC15),
ASPEED_PINCTRL_FUNC(ADC2),
ASPEED_PINCTRL_FUNC(ADC3),
ASPEED_PINCTRL_FUNC(ADC4),
ASPEED_PINCTRL_FUNC(ADC5),
ASPEED_PINCTRL_FUNC(ADC6),
ASPEED_PINCTRL_FUNC(ADC7),
ASPEED_PINCTRL_FUNC(ADC8),
ASPEED_PINCTRL_FUNC(ADC9),
ASPEED_PINCTRL_FUNC(BMCINT),
ASPEED_PINCTRL_FUNC(DDCCLK),
ASPEED_PINCTRL_FUNC(DDCDAT),
ASPEED_PINCTRL_FUNC(ESPI),
ASPEED_PINCTRL_FUNC(FWSPICS1),
ASPEED_PINCTRL_FUNC(FWSPICS2),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(GPID0),
ASPEED_PINCTRL_FUNC(GPID2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(GPID4),
ASPEED_PINCTRL_FUNC(GPID6),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(GPIE0),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(GPIE2),
ASPEED_PINCTRL_FUNC(GPIE4),
ASPEED_PINCTRL_FUNC(GPIE6),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(I2C10),
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
ASPEED_PINCTRL_FUNC(I2C13),
ASPEED_PINCTRL_FUNC(I2C14),
ASPEED_PINCTRL_FUNC(I2C3),
ASPEED_PINCTRL_FUNC(I2C4),
ASPEED_PINCTRL_FUNC(I2C5),
ASPEED_PINCTRL_FUNC(I2C6),
ASPEED_PINCTRL_FUNC(I2C7),
ASPEED_PINCTRL_FUNC(I2C8),
ASPEED_PINCTRL_FUNC(I2C9),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(LAD0),
ASPEED_PINCTRL_FUNC(LAD1),
ASPEED_PINCTRL_FUNC(LAD2),
ASPEED_PINCTRL_FUNC(LAD3),
ASPEED_PINCTRL_FUNC(LCLK),
ASPEED_PINCTRL_FUNC(LFRAME),
ASPEED_PINCTRL_FUNC(LPCHC),
ASPEED_PINCTRL_FUNC(LPCPD),
ASPEED_PINCTRL_FUNC(LPCPLUS),
ASPEED_PINCTRL_FUNC(LPCPME),
ASPEED_PINCTRL_FUNC(LPCRST),
ASPEED_PINCTRL_FUNC(LPCSMI),
ASPEED_PINCTRL_FUNC(LSIRQ),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(MAC1LINK),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(MAC2LINK),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(NCTS1),
ASPEED_PINCTRL_FUNC(NCTS2),
ASPEED_PINCTRL_FUNC(NCTS3),
ASPEED_PINCTRL_FUNC(NCTS4),
ASPEED_PINCTRL_FUNC(NDCD1),
ASPEED_PINCTRL_FUNC(NDCD2),
ASPEED_PINCTRL_FUNC(NDCD3),
ASPEED_PINCTRL_FUNC(NDCD4),
ASPEED_PINCTRL_FUNC(NDSR1),
ASPEED_PINCTRL_FUNC(NDSR2),
ASPEED_PINCTRL_FUNC(NDSR3),
ASPEED_PINCTRL_FUNC(NDSR4),
ASPEED_PINCTRL_FUNC(NDTR1),
ASPEED_PINCTRL_FUNC(NDTR2),
ASPEED_PINCTRL_FUNC(NDTR3),
ASPEED_PINCTRL_FUNC(NDTR4),
ASPEED_PINCTRL_FUNC(NRI1),
ASPEED_PINCTRL_FUNC(NRI2),
ASPEED_PINCTRL_FUNC(NRI3),
ASPEED_PINCTRL_FUNC(NRI4),
ASPEED_PINCTRL_FUNC(NRTS1),
ASPEED_PINCTRL_FUNC(NRTS2),
ASPEED_PINCTRL_FUNC(NRTS3),
ASPEED_PINCTRL_FUNC(NRTS4),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PEWAKE),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(PNOR),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM2),
ASPEED_PINCTRL_FUNC(PWM3),
ASPEED_PINCTRL_FUNC(PWM4),
ASPEED_PINCTRL_FUNC(PWM5),
ASPEED_PINCTRL_FUNC(PWM6),
ASPEED_PINCTRL_FUNC(PWM7),
ASPEED_PINCTRL_FUNC(RGMII1),
ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RMII1),
ASPEED_PINCTRL_FUNC(RMII2),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(RXD1),
ASPEED_PINCTRL_FUNC(RXD2),
ASPEED_PINCTRL_FUNC(RXD3),
ASPEED_PINCTRL_FUNC(RXD4),
ASPEED_PINCTRL_FUNC(SALT1),
ASPEED_PINCTRL_FUNC(SALT10),
ASPEED_PINCTRL_FUNC(SALT11),
ASPEED_PINCTRL_FUNC(SALT12),
ASPEED_PINCTRL_FUNC(SALT13),
ASPEED_PINCTRL_FUNC(SALT14),
ASPEED_PINCTRL_FUNC(SALT2),
ASPEED_PINCTRL_FUNC(SALT3),
ASPEED_PINCTRL_FUNC(SALT4),
ASPEED_PINCTRL_FUNC(SALT5),
ASPEED_PINCTRL_FUNC(SALT6),
ASPEED_PINCTRL_FUNC(SALT7),
ASPEED_PINCTRL_FUNC(SALT8),
ASPEED_PINCTRL_FUNC(SALT9),
ASPEED_PINCTRL_FUNC(SCL1),
ASPEED_PINCTRL_FUNC(SCL2),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(SD1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(SD2),
ASPEED_PINCTRL_FUNC(SDA1),
ASPEED_PINCTRL_FUNC(SDA2),
pinctrl: aspeed: Add SGPM pinmux Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-04 21:53:32 +00:00
ASPEED_PINCTRL_FUNC(SGPM),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(SGPS1),
ASPEED_PINCTRL_FUNC(SGPS2),
ASPEED_PINCTRL_FUNC(SIOONCTRL),
ASPEED_PINCTRL_FUNC(SIOPBI),
ASPEED_PINCTRL_FUNC(SIOPBO),
ASPEED_PINCTRL_FUNC(SIOPWREQ),
ASPEED_PINCTRL_FUNC(SIOPWRGD),
ASPEED_PINCTRL_FUNC(SIOS3),
ASPEED_PINCTRL_FUNC(SIOS5),
ASPEED_PINCTRL_FUNC(SIOSCI),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(SPI1),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(SPI1CS1),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(SPI2CK),
ASPEED_PINCTRL_FUNC(SPI2CS0),
ASPEED_PINCTRL_FUNC(SPI2CS1),
ASPEED_PINCTRL_FUNC(SPI2MISO),
ASPEED_PINCTRL_FUNC(SPI2MOSI),
ASPEED_PINCTRL_FUNC(TIMER3),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(TXD1),
ASPEED_PINCTRL_FUNC(TXD2),
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
pinctrl: aspeed: g5: Add USB device and host support Implement the AST2500 USB functions as described by the devicetree bindings. The AST2500 exposes five USB controllers through two USB ports. Similar to the AST2400, the pins exposing USB are outliers with respect to the rest of the pinmux as they not capable of GPIO. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-07-18 05:24:53 +00:00
ASPEED_PINCTRL_FUNC(USB11BHID),
ASPEED_PINCTRL_FUNC(USB2AD),
ASPEED_PINCTRL_FUNC(USB2AH),
ASPEED_PINCTRL_FUNC(USB2BD),
ASPEED_PINCTRL_FUNC(USB2BH),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(USBCKI),
pinctrl: aspeed-g5: Fix pin association of SPI1 function The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-27 14:50:16 +00:00
ASPEED_PINCTRL_FUNC(VGABIOSROM),
pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:50 +00:00
ASPEED_PINCTRL_FUNC(VGAHS),
ASPEED_PINCTRL_FUNC(VGAVS),
ASPEED_PINCTRL_FUNC(VPI24),
ASPEED_PINCTRL_FUNC(VPO),
ASPEED_PINCTRL_FUNC(WDTRST1),
ASPEED_PINCTRL_FUNC(WDTRST2),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
};
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
static struct aspeed_pin_config aspeed_g5_configs[] = {
/* GPIOA, GPIOQ */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOB, GPIOR */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOC, GPIOS*/
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOD, GPIOY */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOE, GPIOZ */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOF, GPIOAA */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
/* GPIOG, GPIOAB */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOH, GPIOAC */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOs [I, P] */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOs T[0-5] (RGMII1 Tx pins) */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* GPIOs V[2-7] (RGMII2 Rx pins) */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/* ADC pull-downs (SCUA8[19:4]) */
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
/*
* Debounce settings for GPIOs D and E passthrough mode are in
* SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
* banks D and E is handled by the GPIO driver - GPIO passthrough is
* treated like any other non-GPIO mux function. There is a catch
* however, in that the debounce period is configured in the GPIO
* controller. Due to this tangle between GPIO and pinctrl we don't yet
* fully support pass-through debounce.
*/
pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:29 +00:00
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27),
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
};
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
int ip)
{
if (ip == ASPEED_IP_SCU) {
WARN(!ctx->maps[ip], "Missing SCU syscon!");
return ctx->maps[ip];
}
if (ip >= ASPEED_NR_PINMUX_IPS)
return ERR_PTR(-EINVAL);
if (likely(ctx->maps[ip]))
return ctx->maps[ip];
if (ip == ASPEED_IP_GFX) {
struct device_node *node;
struct regmap *map;
node = of_parse_phandle(ctx->dev->of_node,
"aspeed,external-nodes", 0);
if (node) {
map = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(map))
return map;
} else
return ERR_PTR(-ENODEV);
ctx->maps[ASPEED_IP_GFX] = map;
dev_dbg(ctx->dev, "Acquired GFX regmap");
return map;
}
if (ip == ASPEED_IP_LPC) {
pinctrl: aspeed-g5: Adapt to new LPC device tree layout Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-4-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-03-19 06:27:35 +00:00
struct device_node *np;
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
struct regmap *map;
pinctrl: aspeed-g5: Adapt to new LPC device tree layout Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-4-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-03-19 06:27:35 +00:00
np = of_parse_phandle(ctx->dev->of_node,
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
"aspeed,external-nodes", 1);
pinctrl: aspeed-g5: Adapt to new LPC device tree layout Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-4-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-03-19 06:27:35 +00:00
if (np) {
if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") &&
!of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") &&
!of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2"))
return ERR_PTR(-ENODEV);
map = syscon_node_to_regmap(np->parent);
of_node_put(np);
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
if (IS_ERR(map))
return map;
} else
pinctrl: aspeed: Fix spurious mux failures on the AST2500 Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") was determined to be a partial fix to the problem of acquiring the LPC Host Controller and GFX regmaps: The AST2500 pin controller may need to fetch syscon regmaps during expression evaluation as well as when setting mux state. For example, this case is hit by attempting to export pins exposing the LPC Host Controller as GPIOs. An optional eval() hook is added to the Aspeed pinmux operation struct and called from aspeed_sig_expr_eval() if the pointer is set by the SoC-specific driver. This enables the AST2500 to perform the custom action of acquiring its regmap dependencies as required. John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based) where the issue was found, and I've booted the fix on Witherspoon (AST2500) and Palmetto (AST2400) machines, and poked at relevant pins under QEMU by forcing mux configurations via devmem before exporting GPIOs to exercise the driver. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Fixes: 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") Reported-by: John Wang <wangzqbj@inspur.com> Tested-by: John Wang <wangzqbj@inspur.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190829071738.2523-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-29 07:17:38 +00:00
return ERR_PTR(-ENODEV);
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
ctx->maps[ASPEED_IP_LPC] = map;
dev_dbg(ctx->dev, "Acquired LPC regmap");
return map;
}
return ERR_PTR(-EINVAL);
}
pinctrl: aspeed: Fix spurious mux failures on the AST2500 Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") was determined to be a partial fix to the problem of acquiring the LPC Host Controller and GFX regmaps: The AST2500 pin controller may need to fetch syscon regmaps during expression evaluation as well as when setting mux state. For example, this case is hit by attempting to export pins exposing the LPC Host Controller as GPIOs. An optional eval() hook is added to the Aspeed pinmux operation struct and called from aspeed_sig_expr_eval() if the pointer is set by the SoC-specific driver. This enables the AST2500 to perform the custom action of acquiring its regmap dependencies as required. John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based) where the issue was found, and I've booted the fix on Witherspoon (AST2500) and Palmetto (AST2400) machines, and poked at relevant pins under QEMU by forcing mux configurations via devmem before exporting GPIOs to exercise the driver. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Fixes: 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") Reported-by: John Wang <wangzqbj@inspur.com> Tested-by: John Wang <wangzqbj@inspur.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190829071738.2523-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-29 07:17:38 +00:00
static int aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enabled)
{
int ret;
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
struct regmap *map;
map = aspeed_g5_acquire_regmap(ctx, desc->ip);
if (IS_ERR(map)) {
dev_err(ctx->dev,
"Failed to acquire regmap for IP block %d\n",
desc->ip);
return PTR_ERR(map);
}
ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
if (ret <= 0)
return ret;
}
return 1;
}
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
/**
* Configure a pin's signal by applying an expression's descriptor state for
* all descriptors in the expression.
*
* @ctx: The pinmux context
* @expr: The expression associated with the function whose signal is to be
* configured
* @enable: true to enable an function's signal through a pin's signal
* expression, false to disable the function's signal
*
* Return: 0 if the expression is configured as requested and a negative error
* code otherwise
*/
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
const struct aspeed_sig_expr *expr,
bool enable)
{
int ret;
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
u32 pattern = enable ? desc->enable : desc->disable;
u32 val = (pattern << __ffs(desc->mask));
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
struct regmap *map;
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
map = aspeed_g5_acquire_regmap(ctx, desc->ip);
if (IS_ERR(map)) {
dev_err(ctx->dev,
"Failed to acquire regmap for IP block %d\n",
desc->ip);
return PTR_ERR(map);
}
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
/*
* Strap registers are configured in hardware or by early-boot
* firmware. Treat them as read-only despite that we can write
* them. This may mean that certain functions cannot be
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
*
* Port D and port E GPIO loopback modes are the only exception
* as those are commonly used with front-panel buttons to allow
* normal operation of the host when the BMC is powered off or
* fails to boot. Once the BMC has booted, the loopback mode
* must be disabled for the BMC to control host power-on and
* reset.
*/
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
!(desc->mask & (BIT(21) | BIT(22))))
continue;
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
continue;
/* On AST2500, Set bits in SCU70 are cleared from SCU7C */
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
u32 value = ~val & desc->mask;
if (value) {
ret = regmap_write(ctx->maps[desc->ip],
HW_REVISION_ID, value);
if (ret < 0)
return ret;
}
}
ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
desc->mask, val);
if (ret)
return ret;
}
ret = aspeed_sig_expr_eval(ctx, expr, enable);
if (ret < 0)
return ret;
if (!ret)
return -EPERM;
return 0;
}
pinctrl: aspeed: Move aspeed_pin_config_map to separate source file The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:30 +00:00
static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = {
pinctrl: aspeed: Use masks to describe pinconf bitfields Since some of the AST2600 pinconf setting are not just single bit, modified aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to support configuring multiple bits. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:31 +00:00
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
pinctrl: aspeed: Move aspeed_pin_config_map to separate source file The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:30 +00:00
};
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
static const struct aspeed_pinmux_ops aspeed_g5_ops = {
pinctrl: aspeed: Fix spurious mux failures on the AST2500 Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") was determined to be a partial fix to the problem of acquiring the LPC Host Controller and GFX regmaps: The AST2500 pin controller may need to fetch syscon regmaps during expression evaluation as well as when setting mux state. For example, this case is hit by attempting to export pins exposing the LPC Host Controller as GPIOs. An optional eval() hook is added to the Aspeed pinmux operation struct and called from aspeed_sig_expr_eval() if the pointer is set by the SoC-specific driver. This enables the AST2500 to perform the custom action of acquiring its regmap dependencies as required. John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based) where the issue was found, and I've booted the fix on Witherspoon (AST2500) and Palmetto (AST2400) machines, and poked at relevant pins under QEMU by forcing mux configurations via devmem before exporting GPIOs to exercise the driver. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Fixes: 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") Reported-by: John Wang <wangzqbj@inspur.com> Tested-by: John Wang <wangzqbj@inspur.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190829071738.2523-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-29 07:17:38 +00:00
.eval = aspeed_g5_sig_expr_eval,
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
.set = aspeed_g5_sig_expr_set,
};
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
.pins = aspeed_g5_pins,
.npins = ARRAY_SIZE(aspeed_g5_pins),
pinctrl: aspeed: Split out pinmux from general pinctrl ASPEED have completely rearranged the System Control Unit register layout with the AST2600. The existing code took advantage of the fact that the AST2400 and AST2500 had layouts that were similar enough to have little impact on the pinmux infrastructure (though there is a wart with read-modify-write vs write-1-clear semantics of the hardware strapping registers between the two). Given that any similarity has been thrown out with the AST2600, separate out the function applying an expression state to be driver-specific. With it, extract out the pinmux macro jungle to its own header and implementation so the pieces can be composed without dependency cycles. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-28 02:38:37 +00:00
.pinmux = {
.ops = &aspeed_g5_ops,
.groups = aspeed_g5_groups,
.ngroups = ARRAY_SIZE(aspeed_g5_groups),
.functions = aspeed_g5_functions,
.nfunctions = ARRAY_SIZE(aspeed_g5_functions),
},
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
.configs = aspeed_g5_configs,
.nconfigs = ARRAY_SIZE(aspeed_g5_configs),
pinctrl: aspeed: Move aspeed_pin_config_map to separate source file The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-02 06:14:30 +00:00
.confmaps = aspeed_g5_pin_config_map,
.nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map),
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
};
pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-10 10:06:21 +00:00
static const struct pinmux_ops aspeed_g5_pinmux_ops = {
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
.set_mux = aspeed_pinmux_set_mux,
.gpio_request_enable = aspeed_gpio_request_enable,
.strict = true,
};
pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-10 10:06:21 +00:00
static const struct pinctrl_ops aspeed_g5_pinctrl_ops = {
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
.dt_free_map = pinctrl_utils_free_map,
};
pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-10 10:06:21 +00:00
static const struct pinconf_ops aspeed_g5_conf_ops = {
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
.is_generic = true,
.pin_config_get = aspeed_pin_config_get,
.pin_config_set = aspeed_pin_config_set,
.pin_config_group_get = aspeed_pin_config_group_get,
.pin_config_group_set = aspeed_pin_config_group_set,
};
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
.name = "aspeed-g5-pinctrl",
.pins = aspeed_g5_pins,
.npins = ARRAY_SIZE(aspeed_g5_pins),
.pctlops = &aspeed_g5_pinctrl_ops,
.pmxops = &aspeed_g5_pinmux_ops,
pinctrl: aspeed: g5: Add pinconf support Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-07 12:57:13 +00:00
.confops = &aspeed_g5_conf_ops,
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
};
static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
{
int i;
for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
aspeed_g5_pins[i].number = i;
pinctrl: aspeed-g5: Delay acquisition of regmaps While sorting out some devicetree issues I found that the pinctrl driver was failing to acquire its GFX regmap even though the phandle was present in the devicetree: [ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail Without access to the GFX regmap we fail to configure the mux for the VPO function: [ 1.548866] pinctrl core: add 1 pinctrl maps [ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO [ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display [ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display ... [ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display [ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display [ 1.563113] Muxing pin 144 for VPO [ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000 [ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back This turned out to be a simple problem of timing: The ASPEED pinctrl driver is probed during arch_initcall(), while GFX is processed much later. As such the GFX syscon is not yet registered during the pinctrl probe() and we get an -EPROBE_DEFER when we try to look it up, however we must not defer probing the pinctrl driver for the inability to mux some GFX-related functions. Switch to lazily grabbing the regmaps when they're first required by the mux configuration. This generates a bit of noise in the patch as we have to drop the `const` qualifier on arguments for several function prototypes, but has the benefit of working. I've smoke tested this for the ast2500-evb under qemu with a dummy graphics device. We now succeed in our attempts to configure the SoC's VPO pinmux function. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:01:55 +00:00
aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;
pinctrl: aspeed: Read and write bits in LPC and GFX controllers The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-20 07:35:48 +00:00
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
&aspeed_g5_pinctrl_data);
}
static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
{ .compatible = "aspeed,ast2500-pinctrl", },
pinctrl: aspeed: Document existence of deprecated compatibles Otherwise they look odd in the face of not being listed in the bindings documents. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190724081313.12934-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-24 08:13:12 +00:00
/*
* The aspeed,g5-pinctrl compatible has been removed the from the
* bindings, but keep the match in case of old devicetrees.
*/
pinctrl: Add pinctrl-aspeed-g5 driver A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-08-30 07:54:26 +00:00
{ .compatible = "aspeed,g5-pinctrl", },
{ },
};
static struct platform_driver aspeed_g5_pinctrl_driver = {
.probe = aspeed_g5_pinctrl_probe,
.driver = {
.name = "aspeed-g5-pinctrl",
.of_match_table = aspeed_g5_pinctrl_of_match,
},
};
static int aspeed_g5_pinctrl_init(void)
{
return platform_driver_register(&aspeed_g5_pinctrl_driver);
}
arch_initcall(aspeed_g5_pinctrl_init);
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