License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-16 22:20:36 +00:00
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/*
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* Implement the default iomap interfaces
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*
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* (C) Copyright 2004 Linus Torvalds
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*/
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#include <linux/pci.h>
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devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 07:00:26 +00:00
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#include <linux/io.h>
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2011-11-17 02:29:17 +00:00
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#include <linux/export.h>
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2005-04-16 22:20:36 +00:00
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/*
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* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
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* access or a MMIO access, these functions don't care. The info is
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* encoded in the hardware mapping set up by the mapping functions
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* (or the cookie itself, depending on implementation and hw).
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*
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* The generic routines don't assume any hardware mappings, and just
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* encode the PIO/MMIO as part of the cookie. They coldly assume that
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* the MMIO IO mappings are not in the low address range.
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*
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* Architectures for which this is not true can't use this generic
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* implementation and should do their own copy.
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*/
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#ifndef HAVE_ARCH_PIO_SIZE
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/*
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* We encode the physical PIO addresses (0-0xffff) into the
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* pointer by offsetting them with a constant (0x10000) and
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* assuming that all the low addresses are always PIO. That means
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* we can do some sanity checks on the low bits, and don't
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* need to just take things for granted.
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*/
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#define PIO_OFFSET 0x10000UL
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#define PIO_MASK 0x0ffffUL
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#define PIO_RESERVED 0x40000UL
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#endif
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2007-05-05 03:44:23 +00:00
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static void bad_io_access(unsigned long port, const char *access)
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{
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static int count = 10;
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if (count) {
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count--;
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2008-07-26 02:45:39 +00:00
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WARN(1, KERN_ERR "Bad IO access at port %#lx (%s)\n", port, access);
|
2007-05-05 03:44:23 +00:00
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}
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}
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2005-04-16 22:20:36 +00:00
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/*
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* Ugly macros are a way of life.
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*/
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#define IO_COND(addr, is_pio, is_mmio) do { \
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unsigned long port = (unsigned long __force)addr; \
|
2007-05-05 03:44:23 +00:00
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if (port >= PIO_RESERVED) { \
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is_mmio; \
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} else if (port > PIO_OFFSET) { \
|
2005-04-16 22:20:36 +00:00
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port &= PIO_MASK; \
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is_pio; \
|
2007-05-05 03:44:23 +00:00
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} else \
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bad_io_access(port, #is_pio ); \
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2005-04-16 22:20:36 +00:00
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} while (0)
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2006-11-11 06:24:46 +00:00
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#ifndef pio_read16be
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#define pio_read16be(port) swab16(inw(port))
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#define pio_read32be(port) swab32(inl(port))
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#endif
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#ifndef mmio_read16be
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2019-01-16 18:25:18 +00:00
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#define mmio_read16be(addr) swab16(readw(addr))
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#define mmio_read32be(addr) swab32(readl(addr))
|
2019-01-16 18:25:20 +00:00
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#define mmio_read64be(addr) swab64(readq(addr))
|
2006-11-11 06:24:46 +00:00
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#endif
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2020-08-15 00:32:07 +00:00
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unsigned int ioread8(const void __iomem *addr)
|
2005-04-16 22:20:36 +00:00
|
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{
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IO_COND(addr, return inb(port), return readb(addr));
|
2007-05-05 03:44:23 +00:00
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return 0xff;
|
2005-04-16 22:20:36 +00:00
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}
|
2020-08-15 00:32:07 +00:00
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unsigned int ioread16(const void __iomem *addr)
|
2005-04-16 22:20:36 +00:00
|
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{
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IO_COND(addr, return inw(port), return readw(addr));
|
2007-05-05 03:44:23 +00:00
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return 0xffff;
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2005-04-16 22:20:36 +00:00
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}
|
2020-08-15 00:32:07 +00:00
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unsigned int ioread16be(const void __iomem *addr)
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
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{
|
2006-11-11 06:24:46 +00:00
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IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
|
2007-05-05 03:44:23 +00:00
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return 0xffff;
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
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}
|
2020-08-15 00:32:07 +00:00
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unsigned int ioread32(const void __iomem *addr)
|
2005-04-16 22:20:36 +00:00
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|
{
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IO_COND(addr, return inl(port), return readl(addr));
|
2007-05-05 03:44:23 +00:00
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return 0xffffffff;
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2005-04-16 22:20:36 +00:00
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}
|
2020-08-15 00:32:07 +00:00
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unsigned int ioread32be(const void __iomem *addr)
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
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{
|
2006-11-11 06:24:46 +00:00
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IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
|
2007-05-05 03:44:23 +00:00
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return 0xffffffff;
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
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|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
EXPORT_SYMBOL(ioread8);
|
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|
EXPORT_SYMBOL(ioread16);
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
|
EXPORT_SYMBOL(ioread16be);
|
2005-04-16 22:20:36 +00:00
|
|
|
EXPORT_SYMBOL(ioread32);
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
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EXPORT_SYMBOL(ioread32be);
|
2005-04-16 22:20:36 +00:00
|
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|
|
2019-01-16 18:25:20 +00:00
|
|
|
#ifdef readq
|
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static u64 pio_read64_lo_hi(unsigned long port)
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{
|
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u64 lo, hi;
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lo = inl(port);
|
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hi = inl(port + sizeof(u32));
|
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return lo | (hi << 32);
|
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|
}
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static u64 pio_read64_hi_lo(unsigned long port)
|
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|
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{
|
|
|
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u64 lo, hi;
|
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hi = inl(port + sizeof(u32));
|
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lo = inl(port);
|
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return lo | (hi << 32);
|
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}
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static u64 pio_read64be_lo_hi(unsigned long port)
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{
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u64 lo, hi;
|
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lo = pio_read32be(port + sizeof(u32));
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hi = pio_read32be(port);
|
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return lo | (hi << 32);
|
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}
|
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static u64 pio_read64be_hi_lo(unsigned long port)
|
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{
|
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u64 lo, hi;
|
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hi = pio_read32be(port);
|
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lo = pio_read32be(port + sizeof(u32));
|
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return lo | (hi << 32);
|
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}
|
|
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|
|
2020-08-15 00:32:07 +00:00
|
|
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u64 ioread64_lo_hi(const void __iomem *addr)
|
2019-01-16 18:25:20 +00:00
|
|
|
{
|
|
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|
IO_COND(addr, return pio_read64_lo_hi(port), return readq(addr));
|
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|
return 0xffffffffffffffffULL;
|
|
|
|
}
|
|
|
|
|
2020-08-15 00:32:07 +00:00
|
|
|
u64 ioread64_hi_lo(const void __iomem *addr)
|
2019-01-16 18:25:20 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, return pio_read64_hi_lo(port), return readq(addr));
|
|
|
|
return 0xffffffffffffffffULL;
|
|
|
|
}
|
|
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|
|
2020-08-15 00:32:07 +00:00
|
|
|
u64 ioread64be_lo_hi(const void __iomem *addr)
|
2019-01-16 18:25:20 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, return pio_read64be_lo_hi(port),
|
|
|
|
return mmio_read64be(addr));
|
|
|
|
return 0xffffffffffffffffULL;
|
|
|
|
}
|
|
|
|
|
2020-08-15 00:32:07 +00:00
|
|
|
u64 ioread64be_hi_lo(const void __iomem *addr)
|
2019-01-16 18:25:20 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, return pio_read64be_hi_lo(port),
|
|
|
|
return mmio_read64be(addr));
|
|
|
|
return 0xffffffffffffffffULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(ioread64_lo_hi);
|
|
|
|
EXPORT_SYMBOL(ioread64_hi_lo);
|
|
|
|
EXPORT_SYMBOL(ioread64be_lo_hi);
|
|
|
|
EXPORT_SYMBOL(ioread64be_hi_lo);
|
|
|
|
|
|
|
|
#endif /* readq */
|
|
|
|
|
2006-11-11 06:24:46 +00:00
|
|
|
#ifndef pio_write16be
|
|
|
|
#define pio_write16be(val,port) outw(swab16(val),port)
|
|
|
|
#define pio_write32be(val,port) outl(swab32(val),port)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef mmio_write16be
|
2019-01-16 18:25:18 +00:00
|
|
|
#define mmio_write16be(val,port) writew(swab16(val),port)
|
|
|
|
#define mmio_write32be(val,port) writel(swab32(val),port)
|
2019-01-16 18:25:20 +00:00
|
|
|
#define mmio_write64be(val,port) writeq(swab64(val),port)
|
2006-11-11 06:24:46 +00:00
|
|
|
#endif
|
|
|
|
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite8(u8 val, void __iomem *addr)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, outb(val,port), writeb(val, addr));
|
|
|
|
}
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite16(u16 val, void __iomem *addr)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, outw(val,port), writew(val, addr));
|
|
|
|
}
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite16be(u16 val, void __iomem *addr)
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
|
{
|
2006-11-11 06:24:46 +00:00
|
|
|
IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
|
}
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite32(u32 val, void __iomem *addr)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, outl(val,port), writel(val, addr));
|
|
|
|
}
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite32be(u32 val, void __iomem *addr)
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
|
{
|
2006-11-11 06:24:46 +00:00
|
|
|
IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
EXPORT_SYMBOL(iowrite8);
|
|
|
|
EXPORT_SYMBOL(iowrite16);
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
|
EXPORT_SYMBOL(iowrite16be);
|
2005-04-16 22:20:36 +00:00
|
|
|
EXPORT_SYMBOL(iowrite32);
|
[PATCH] add Big Endian variants of ioread/iowrite
In the new io infrastructure, all of our operators are expecting the
underlying device to be little endian (because the PCI bus, their main
consumer, is LE).
However, there are a fair few devices and busses in the world that are
actually Big Endian. There's even evidence that some of these BE bus and
chip types are attached to LE systems. Thus, there's a need for a BE
equivalent of our io{read,write}{16,32} operations.
The attached patch adds this as io{read,write}{16,32}be. When it's in,
I'll add the first consume (the 53c700 SCSI chip driver).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-16 22:25:54 +00:00
|
|
|
EXPORT_SYMBOL(iowrite32be);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2019-01-16 18:25:20 +00:00
|
|
|
#ifdef writeq
|
|
|
|
static void pio_write64_lo_hi(u64 val, unsigned long port)
|
|
|
|
{
|
|
|
|
outl(val, port);
|
|
|
|
outl(val >> 32, port + sizeof(u32));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pio_write64_hi_lo(u64 val, unsigned long port)
|
|
|
|
{
|
|
|
|
outl(val >> 32, port + sizeof(u32));
|
|
|
|
outl(val, port);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pio_write64be_lo_hi(u64 val, unsigned long port)
|
|
|
|
{
|
|
|
|
pio_write32be(val, port + sizeof(u32));
|
|
|
|
pio_write32be(val >> 32, port);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pio_write64be_hi_lo(u64 val, unsigned long port)
|
|
|
|
{
|
|
|
|
pio_write32be(val >> 32, port);
|
|
|
|
pio_write32be(val, port + sizeof(u32));
|
|
|
|
}
|
|
|
|
|
|
|
|
void iowrite64_lo_hi(u64 val, void __iomem *addr)
|
|
|
|
{
|
|
|
|
IO_COND(addr, pio_write64_lo_hi(val, port),
|
|
|
|
writeq(val, addr));
|
|
|
|
}
|
|
|
|
|
|
|
|
void iowrite64_hi_lo(u64 val, void __iomem *addr)
|
|
|
|
{
|
|
|
|
IO_COND(addr, pio_write64_hi_lo(val, port),
|
|
|
|
writeq(val, addr));
|
|
|
|
}
|
|
|
|
|
|
|
|
void iowrite64be_lo_hi(u64 val, void __iomem *addr)
|
|
|
|
{
|
|
|
|
IO_COND(addr, pio_write64be_lo_hi(val, port),
|
|
|
|
mmio_write64be(val, addr));
|
|
|
|
}
|
|
|
|
|
|
|
|
void iowrite64be_hi_lo(u64 val, void __iomem *addr)
|
|
|
|
{
|
|
|
|
IO_COND(addr, pio_write64be_hi_lo(val, port),
|
|
|
|
mmio_write64be(val, addr));
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(iowrite64_lo_hi);
|
|
|
|
EXPORT_SYMBOL(iowrite64_hi_lo);
|
|
|
|
EXPORT_SYMBOL(iowrite64be_lo_hi);
|
|
|
|
EXPORT_SYMBOL(iowrite64be_hi_lo);
|
|
|
|
|
|
|
|
#endif /* readq */
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* These are the "repeat MMIO read/write" functions.
|
|
|
|
* Note the "__raw" accesses, since we don't want to
|
|
|
|
* convert to CPU byte order. We write in "IO byte
|
|
|
|
* order" (we also don't have IO barriers).
|
|
|
|
*/
|
2006-11-11 06:24:46 +00:00
|
|
|
#ifndef mmio_insb
|
2020-08-15 00:32:07 +00:00
|
|
|
static inline void mmio_insb(const void __iomem *addr, u8 *dst, int count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
while (--count >= 0) {
|
|
|
|
u8 data = __raw_readb(addr);
|
|
|
|
*dst = data;
|
|
|
|
dst++;
|
|
|
|
}
|
|
|
|
}
|
2020-08-15 00:32:07 +00:00
|
|
|
static inline void mmio_insw(const void __iomem *addr, u16 *dst, int count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
while (--count >= 0) {
|
|
|
|
u16 data = __raw_readw(addr);
|
|
|
|
*dst = data;
|
|
|
|
dst++;
|
|
|
|
}
|
|
|
|
}
|
2020-08-15 00:32:07 +00:00
|
|
|
static inline void mmio_insl(const void __iomem *addr, u32 *dst, int count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
while (--count >= 0) {
|
|
|
|
u32 data = __raw_readl(addr);
|
|
|
|
*dst = data;
|
|
|
|
dst++;
|
|
|
|
}
|
|
|
|
}
|
2006-11-11 06:24:46 +00:00
|
|
|
#endif
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-11-11 06:24:46 +00:00
|
|
|
#ifndef mmio_outsb
|
2005-04-16 22:20:36 +00:00
|
|
|
static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
|
|
|
|
{
|
|
|
|
while (--count >= 0) {
|
|
|
|
__raw_writeb(*src, addr);
|
|
|
|
src++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
|
|
|
|
{
|
|
|
|
while (--count >= 0) {
|
|
|
|
__raw_writew(*src, addr);
|
|
|
|
src++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
|
|
|
|
{
|
|
|
|
while (--count >= 0) {
|
|
|
|
__raw_writel(*src, addr);
|
|
|
|
src++;
|
|
|
|
}
|
|
|
|
}
|
2006-11-11 06:24:46 +00:00
|
|
|
#endif
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2020-08-15 00:32:07 +00:00
|
|
|
void ioread8_rep(const void __iomem *addr, void *dst, unsigned long count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
|
|
|
|
}
|
2020-08-15 00:32:07 +00:00
|
|
|
void ioread16_rep(const void __iomem *addr, void *dst, unsigned long count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
|
|
|
|
}
|
2020-08-15 00:32:07 +00:00
|
|
|
void ioread32_rep(const void __iomem *addr, void *dst, unsigned long count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ioread8_rep);
|
|
|
|
EXPORT_SYMBOL(ioread16_rep);
|
|
|
|
EXPORT_SYMBOL(ioread32_rep);
|
|
|
|
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
|
|
|
|
}
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
|
|
|
|
}
|
2008-02-08 12:19:55 +00:00
|
|
|
void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(iowrite8_rep);
|
|
|
|
EXPORT_SYMBOL(iowrite16_rep);
|
|
|
|
EXPORT_SYMBOL(iowrite32_rep);
|
|
|
|
|
2014-04-07 22:39:19 +00:00
|
|
|
#ifdef CONFIG_HAS_IOPORT_MAP
|
2005-04-16 22:20:36 +00:00
|
|
|
/* Create a virtual mapping cookie for an IO port range */
|
|
|
|
void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
|
|
|
{
|
|
|
|
if (port > PIO_MASK)
|
|
|
|
return NULL;
|
|
|
|
return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ioport_unmap(void __iomem *addr)
|
|
|
|
{
|
|
|
|
/* Nothing to do */
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ioport_map);
|
|
|
|
EXPORT_SYMBOL(ioport_unmap);
|
2014-04-07 22:39:19 +00:00
|
|
|
#endif /* CONFIG_HAS_IOPORT_MAP */
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2011-07-02 15:23:29 +00:00
|
|
|
#ifdef CONFIG_PCI
|
2011-11-24 18:45:20 +00:00
|
|
|
/* Hide the details if this is a MMIO or PIO address space and just do what
|
|
|
|
* you expect in the correct way. */
|
2005-04-16 22:20:36 +00:00
|
|
|
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
|
|
|
|
{
|
|
|
|
IO_COND(addr, /* nothing */, iounmap(addr));
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_iounmap);
|
2011-07-02 15:23:29 +00:00
|
|
|
#endif /* CONFIG_PCI */
|