2017-11-07 20:07:52 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2009-06-13 11:38:31 +00:00
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/*
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* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
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* All rights reserved.
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*
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* File: rf.c
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*
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* Purpose: rf function code
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*
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* Author: Jerry Chen
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*
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* Date: Feb. 19, 2004
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*
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* Functions:
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2014-05-27 20:05:20 +00:00
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* vnt_rf_write_embedded - Embedded write RF register via MAC
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2009-06-13 11:38:31 +00:00
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*
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* Revision History:
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2013-05-27 13:03:42 +00:00
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* RF_VT3226: RobertYu:20051111, VT3226C0 and before
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* RF_VT3226D0: RobertYu:20051228
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2013-05-27 13:05:51 +00:00
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* RF_VT3342A0: RobertYu:20060609
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2009-06-13 11:38:31 +00:00
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*
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*/
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2020-04-14 15:38:45 +00:00
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#include <linux/errno.h>
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2009-06-13 11:38:31 +00:00
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#include "mac.h"
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#include "rf.h"
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#include "baseband.h"
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2014-05-26 12:59:07 +00:00
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#include "usbpipe.h"
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2009-06-13 11:38:31 +00:00
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#define CB_AL2230_INIT_SEQ 15
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#define CB_AL7230_INIT_SEQ 16
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#define AL7230_PWR_IDX_LEN 64
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#define CB_VT3226_INIT_SEQ 11
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#define VT3226_PWR_IDX_LEN 64
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#define CB_VT3342_INIT_SEQ 13
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#define VT3342_PWR_IDX_LEN 64
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2013-05-27 13:09:52 +00:00
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static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = {
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2014-07-12 10:30:00 +00:00
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{0x03, 0xf7, 0x90},
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{0x03, 0x33, 0x31},
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{0x01, 0xb8, 0x02},
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{0x00, 0xff, 0xf3},
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{0x00, 0x05, 0xa4},
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{0x0f, 0x4d, 0xc5},
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{0x08, 0x05, 0xb6},
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{0x01, 0x47, 0xc7},
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{0x00, 0x06, 0x88},
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{0x04, 0x03, 0xb9},
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{0x00, 0xdb, 0xba},
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{0x00, 0x09, 0x9b},
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{0x0b, 0xdf, 0xfc},
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{0x00, 0x00, 0x0d},
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{0x00, 0x58, 0x0f}
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};
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2009-06-13 11:38:31 +00:00
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2013-05-27 13:09:52 +00:00
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static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = {
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2014-07-12 10:30:00 +00:00
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{0x03, 0xf7, 0x90},
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{0x03, 0xf7, 0x90},
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{0x03, 0xe7, 0x90},
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{0x03, 0xe7, 0x90},
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{0x03, 0xf7, 0xa0},
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{0x03, 0xf7, 0xa0},
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{0x03, 0xe7, 0xa0},
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{0x03, 0xe7, 0xa0},
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{0x03, 0xf7, 0xb0},
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{0x03, 0xf7, 0xb0},
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{0x03, 0xe7, 0xb0},
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{0x03, 0xe7, 0xb0},
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{0x03, 0xf7, 0xc0},
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{0x03, 0xe7, 0xc0}
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};
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2009-06-13 11:38:31 +00:00
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2013-05-27 13:09:52 +00:00
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static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = {
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2014-07-12 10:30:00 +00:00
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x06, 0x66, 0x61}
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};
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2009-06-13 11:38:31 +00:00
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2013-05-27 13:09:52 +00:00
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static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = {
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2014-07-12 10:30:00 +00:00
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{0x20, 0x37, 0x90},
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{0x13, 0x33, 0x31},
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{0x84, 0x1f, 0xf2},
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{0x3f, 0xdf, 0xa3},
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{0x7f, 0xd7, 0x84},
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{0x80, 0x2b, 0x55},
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{0x56, 0xaf, 0x36},
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{0xce, 0x02, 0x07},
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{0x6e, 0xbc, 0x98},
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{0x22, 0x1b, 0xb9},
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{0xe0, 0x00, 0x0a},
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{0x08, 0x03, 0x1b},
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{0x00, 0x0a, 0x3c},
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{0xff, 0xff, 0xfd},
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{0x00, 0x00, 0x0e},
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{0x1a, 0xba, 0x8f}
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};
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2009-06-13 11:38:31 +00:00
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2013-05-27 13:09:52 +00:00
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static u8 al7230_init_table_amode[CB_AL7230_INIT_SEQ][3] = {
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2014-07-12 10:30:00 +00:00
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{0x2f, 0xf5, 0x20},
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{0x00, 0x00, 0x01},
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{0x45, 0x1f, 0xe2},
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{0x5f, 0xdf, 0xa3},
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{0x6f, 0xd7, 0x84},
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{0x85, 0x3f, 0x55},
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{0x56, 0xaf, 0x36},
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{0xce, 0x02, 0x07},
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{0x6e, 0xbc, 0x98},
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{0x22, 0x1b, 0xb9},
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{0xe0, 0x60, 0x0a},
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{0x08, 0x03, 0x1b},
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{0x00, 0x14, 0x7c},
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{0xff, 0xff, 0xfd},
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{0x00, 0x00, 0x0e},
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{0x12, 0xba, 0xcf}
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};
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2009-06-13 11:38:31 +00:00
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2013-05-27 13:09:52 +00:00
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static u8 al7230_channel_table0[CB_MAX_CHANNEL][3] = {
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2014-07-12 10:30:00 +00:00
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0x90},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xa0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xb0},
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{0x20, 0x37, 0xc0},
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{0x20, 0x37, 0xc0},
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{0x0f, 0xf5, 0x20}, /* channel 15 Tf = 4915MHz */
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{0x2f, 0xf5, 0x20},
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{0x0f, 0xf5, 0x20},
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{0x0f, 0xf5, 0x20},
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{0x2f, 0xf5, 0x20},
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{0x0f, 0xf5, 0x20},
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{0x2f, 0xf5, 0x30},
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{0x2f, 0xf5, 0x30},
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{0x0f, 0xf5, 0x40},
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{0x2f, 0xf5, 0x40},
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{0x0f, 0xf5, 0x40},
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{0x0f, 0xf5, 0x40},
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{0x2f, 0xf5, 0x40},
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{0x2f, 0xf5, 0x50},
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{0x2f, 0xf5, 0x60},
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{0x2f, 0xf5, 0x60},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x70},
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{0x2f, 0xf5, 0x80},
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{0x2f, 0xf5, 0x80},
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{0x2f, 0xf5, 0x80},
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{0x2f, 0xf5, 0x90},
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{0x2f, 0xf5, 0xc0},
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{0x2f, 0xf5, 0xc0},
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{0x2f, 0xf5, 0xc0},
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{0x2f, 0xf5, 0xd0},
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{0x2f, 0xf5, 0xd0},
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{0x2f, 0xf5, 0xd0},
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{0x2f, 0xf5, 0xe0},
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{0x2f, 0xf5, 0xe0},
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{0x2f, 0xf5, 0xe0},
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{0x2f, 0xf5, 0xf0},
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{0x2f, 0xf5, 0xf0},
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{0x2f, 0xf6, 0x00},
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{0x2f, 0xf6, 0x00},
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{0x2f, 0xf6, 0x00},
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{0x2f, 0xf6, 0x10},
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{0x2f, 0xf6, 0x10}
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};
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2009-06-13 11:38:31 +00:00
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2013-05-27 13:09:52 +00:00
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static u8 al7230_channel_table1[CB_MAX_CHANNEL][3] = {
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2014-07-12 10:30:00 +00:00
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{0x13, 0x33, 0x31},
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{0x1b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x13, 0x33, 0x31},
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{0x1b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x13, 0x33, 0x31},
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{0x1b, 0x33, 0x31},
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{0x03, 0x33, 0x31},
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{0x0b, 0x33, 0x31},
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{0x13, 0x33, 0x31},
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{0x06, 0x66, 0x61},
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{0x1d, 0x55, 0x51}, /* channel = 15, Tf = 4915MHz */
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{0x00, 0x00, 0x01},
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{0x02, 0xaa, 0xa1},
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{0x08, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x0d, 0x55, 0x51},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x1d, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x02, 0xaa, 0xa1},
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{0x08, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x05, 0x55, 0x51},
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{0x0a, 0xaa, 0xa1},
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{0x10, 0x00, 0x01},
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{0x15, 0x55, 0x51},
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{0x1a, 0xaa, 0xa1},
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{0x00, 0x00, 0x01},
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{0x05, 0x55, 0x51},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x0a, 0xaa, 0xa1},
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{0x15, 0x55, 0x51},
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{0x00, 0x00, 0x01},
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{0x18, 0x00, 0x01},
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{0x02, 0xaa, 0xa1},
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{0x0d, 0x55, 0x51},
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{0x18, 0x00, 0x01},
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{0x02, 0xaa, 0xb1}
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};
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2009-06-13 11:38:31 +00:00
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2013-05-27 13:09:52 +00:00
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static u8 al7230_channel_table2[CB_MAX_CHANNEL][3] = {
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2014-07-12 10:30:00 +00:00
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84}, /* channel = 15 Tf = 4915MHz */
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x6f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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{0x7f, 0xd7, 0x84},
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|
|
{0x6f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x6f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x6f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x6f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84},
|
|
|
|
{0x7f, 0xd7, 0x84}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2014-05-27 20:05:25 +00:00
|
|
|
static u8 vt3226_init_table[CB_VT3226_INIT_SEQ][3] = {
|
2014-07-12 10:30:00 +00:00
|
|
|
{0x03, 0xff, 0x80},
|
|
|
|
{0x02, 0x82, 0xa1},
|
|
|
|
{0x03, 0xc6, 0xa2},
|
|
|
|
{0x01, 0x97, 0x93},
|
|
|
|
{0x03, 0x66, 0x64},
|
|
|
|
{0x00, 0x61, 0xa5},
|
|
|
|
{0x01, 0x7b, 0xd6},
|
|
|
|
{0x00, 0x80, 0x17},
|
|
|
|
{0x03, 0xf8, 0x08},
|
|
|
|
{0x00, 0x02, 0x39},
|
|
|
|
{0x02, 0x00, 0x2a}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2014-05-27 20:05:25 +00:00
|
|
|
static u8 vt3226d0_init_table[CB_VT3226_INIT_SEQ][3] = {
|
2014-07-12 10:30:00 +00:00
|
|
|
{0x03, 0xff, 0x80},
|
|
|
|
{0x03, 0x02, 0x21},
|
|
|
|
{0x03, 0xc6, 0xa2},
|
|
|
|
{0x01, 0x97, 0x93},
|
|
|
|
{0x03, 0x66, 0x64},
|
|
|
|
{0x00, 0x71, 0xa5},
|
|
|
|
{0x01, 0x15, 0xc6},
|
|
|
|
{0x01, 0x2e, 0x07},
|
|
|
|
{0x00, 0x58, 0x08},
|
|
|
|
{0x00, 0x02, 0x79},
|
|
|
|
{0x02, 0x01, 0xaa}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2013-05-27 13:09:52 +00:00
|
|
|
static u8 vt3226_channel_table0[CB_MAX_CHANNEL_24G][3] = {
|
2014-07-12 10:30:00 +00:00
|
|
|
{0x01, 0x97, 0x83},
|
|
|
|
{0x01, 0x97, 0x83},
|
|
|
|
{0x01, 0x97, 0x93},
|
|
|
|
{0x01, 0x97, 0x93},
|
|
|
|
{0x01, 0x97, 0x93},
|
|
|
|
{0x01, 0x97, 0x93},
|
|
|
|
{0x01, 0x97, 0xa3},
|
|
|
|
{0x01, 0x97, 0xa3},
|
|
|
|
{0x01, 0x97, 0xa3},
|
|
|
|
{0x01, 0x97, 0xa3},
|
|
|
|
{0x01, 0x97, 0xb3},
|
|
|
|
{0x01, 0x97, 0xb3},
|
|
|
|
{0x01, 0x97, 0xb3},
|
|
|
|
{0x03, 0x37, 0xc3}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2013-05-27 13:09:52 +00:00
|
|
|
static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = {
|
2014-07-12 10:30:00 +00:00
|
|
|
{0x02, 0x66, 0x64},
|
|
|
|
{0x03, 0x66, 0x64},
|
|
|
|
{0x00, 0x66, 0x64},
|
|
|
|
{0x01, 0x66, 0x64},
|
|
|
|
{0x02, 0x66, 0x64},
|
|
|
|
{0x03, 0x66, 0x64},
|
|
|
|
{0x00, 0x66, 0x64},
|
|
|
|
{0x01, 0x66, 0x64},
|
|
|
|
{0x02, 0x66, 0x64},
|
|
|
|
{0x03, 0x66, 0x64},
|
|
|
|
{0x00, 0x66, 0x64},
|
|
|
|
{0x01, 0x66, 0x64},
|
|
|
|
{0x02, 0x66, 0x64},
|
|
|
|
{0x00, 0xcc, 0xc4}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2013-11-04 08:44:02 +00:00
|
|
|
static const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = {
|
2014-07-12 10:30:02 +00:00
|
|
|
0x0135c600,
|
|
|
|
0x0135c600,
|
|
|
|
0x0235c600,
|
|
|
|
0x0235c600,
|
|
|
|
0x0235c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0335c600,
|
|
|
|
0x0135c600
|
2009-06-13 11:38:31 +00:00
|
|
|
};
|
|
|
|
|
2013-05-27 13:09:52 +00:00
|
|
|
static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
|
2014-07-12 10:30:00 +00:00
|
|
|
{0x03, 0xff, 0x80},
|
|
|
|
{0x02, 0x08, 0x81},
|
|
|
|
{0x00, 0xc6, 0x02},
|
|
|
|
{0x03, 0xc5, 0x13},
|
|
|
|
{0x00, 0xee, 0xe4},
|
|
|
|
{0x00, 0x71, 0xa5},
|
|
|
|
{0x01, 0x75, 0x46},
|
|
|
|
{0x01, 0x40, 0x27},
|
|
|
|
{0x01, 0x54, 0x08},
|
|
|
|
{0x00, 0x01, 0x69},
|
|
|
|
{0x02, 0x00, 0xaa},
|
|
|
|
{0x00, 0x08, 0xcb},
|
|
|
|
{0x01, 0x70, 0x0c}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2013-05-27 13:09:52 +00:00
|
|
|
static u8 vt3342_channel_table0[CB_MAX_CHANNEL][3] = {
|
2014-07-12 10:30:00 +00:00
|
|
|
{0x02, 0x05, 0x03},
|
|
|
|
{0x01, 0x15, 0x03},
|
|
|
|
{0x03, 0xc5, 0x03},
|
|
|
|
{0x02, 0x65, 0x03},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x03, 0xc5, 0x13},
|
|
|
|
{0x02, 0x05, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x03, 0xc5, 0x13},
|
|
|
|
{0x02, 0x65, 0x13},
|
|
|
|
{0x01, 0x15, 0x23},
|
|
|
|
{0x03, 0xc5, 0x23},
|
|
|
|
{0x02, 0x05, 0x23},
|
|
|
|
{0x00, 0xd5, 0x23},
|
|
|
|
{0x01, 0x15, 0x13}, /* channel = 15 Tf = 4915MHz */
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x15, 0x13},
|
|
|
|
{0x01, 0x55, 0x63},
|
|
|
|
{0x01, 0x55, 0x63},
|
|
|
|
{0x02, 0xa5, 0x63},
|
|
|
|
{0x02, 0xa5, 0x63},
|
|
|
|
{0x00, 0x05, 0x73},
|
|
|
|
{0x00, 0x05, 0x73},
|
|
|
|
{0x01, 0x55, 0x73},
|
|
|
|
{0x02, 0xa5, 0x73},
|
|
|
|
{0x00, 0x05, 0x83},
|
|
|
|
{0x01, 0x55, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x02, 0xa5, 0x83},
|
|
|
|
{0x00, 0x05, 0xF3},
|
|
|
|
{0x01, 0x56, 0x03},
|
|
|
|
{0x02, 0xa6, 0x03},
|
|
|
|
{0x00, 0x06, 0x03},
|
|
|
|
{0x00, 0x06, 0x03}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2013-05-27 13:09:52 +00:00
|
|
|
static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = {
|
2014-07-12 10:30:00 +00:00
|
|
|
{0x01, 0x99, 0x94},
|
|
|
|
{0x02, 0x44, 0x44},
|
|
|
|
{0x02, 0xee, 0xe4},
|
|
|
|
{0x03, 0x99, 0x94},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0xee, 0xe4},
|
|
|
|
{0x01, 0x99, 0x94},
|
|
|
|
{0x02, 0x44, 0x44},
|
|
|
|
{0x02, 0xee, 0xe4},
|
|
|
|
{0x03, 0x99, 0x94},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0xee, 0xe4},
|
|
|
|
{0x01, 0x99, 0x94},
|
|
|
|
{0x03, 0x33, 0x34},
|
|
|
|
{0x00, 0x44, 0x44}, /* channel = 15 Tf = 4915MHz */
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x00, 0x44, 0x44},
|
|
|
|
{0x01, 0x55, 0x54},
|
|
|
|
{0x01, 0x55, 0x54},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x00, 0x00, 0x04},
|
|
|
|
{0x00, 0x00, 0x04},
|
|
|
|
{0x01, 0x55, 0x54},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x00, 0x00, 0x04},
|
|
|
|
{0x01, 0x55, 0x54},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x02, 0xaa, 0xa4},
|
|
|
|
{0x03, 0x00, 0x04},
|
|
|
|
{0x00, 0x55, 0x54},
|
|
|
|
{0x01, 0xaa, 0xa4},
|
|
|
|
{0x03, 0x00, 0x04},
|
|
|
|
{0x03, 0x00, 0x04}
|
|
|
|
};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
|
|
|
/*
|
2012-08-13 12:21:50 +00:00
|
|
|
* Description: Write to IF/RF, by embedded programming
|
2009-06-13 11:38:31 +00:00
|
|
|
*/
|
2014-05-27 20:05:20 +00:00
|
|
|
int vnt_rf_write_embedded(struct vnt_private *priv, u32 data)
|
2009-06-13 11:38:31 +00:00
|
|
|
{
|
2014-05-27 20:05:19 +00:00
|
|
|
u8 reg_data[4];
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2014-07-12 10:30:02 +00:00
|
|
|
data |= (VNT_RF_REG_LEN << 3) | IFREGCTL_REGW;
|
|
|
|
|
2014-05-27 20:05:19 +00:00
|
|
|
reg_data[0] = (u8)data;
|
|
|
|
reg_data[1] = (u8)(data >> 8);
|
|
|
|
reg_data[2] = (u8)(data >> 16);
|
|
|
|
reg_data[3] = (u8)(data >> 24);
|
2012-12-10 22:12:07 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
return vnt_control_out(priv, MESSAGE_TYPE_WRITE_IFRF, 0, 0,
|
|
|
|
ARRAY_SIZE(reg_data), reg_data);
|
2009-06-13 11:38:31 +00:00
|
|
|
}
|
|
|
|
|
2014-05-17 08:50:18 +00:00
|
|
|
static u8 vnt_rf_addpower(struct vnt_private *priv)
|
|
|
|
{
|
2020-04-25 14:15:14 +00:00
|
|
|
int base;
|
2014-07-19 11:30:14 +00:00
|
|
|
s32 rssi = -priv->current_rssi;
|
2014-05-17 08:50:18 +00:00
|
|
|
|
|
|
|
if (!rssi)
|
|
|
|
return 7;
|
|
|
|
|
2020-04-25 14:15:14 +00:00
|
|
|
if (priv->rf_type == RF_VT3226D0)
|
|
|
|
base = -60;
|
|
|
|
else
|
|
|
|
base = -70;
|
|
|
|
|
|
|
|
if (rssi < base)
|
|
|
|
return ((rssi - base + 1) / -5) * 2 + 5;
|
2014-05-17 08:50:18 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-12 10:30:03 +00:00
|
|
|
/* Set Tx power by power level and rate */
|
2020-04-06 19:31:16 +00:00
|
|
|
static int vnt_rf_set_txpower(struct vnt_private *priv, u8 power,
|
|
|
|
struct ieee80211_channel *ch)
|
2009-06-13 11:38:31 +00:00
|
|
|
{
|
2013-05-27 13:03:42 +00:00
|
|
|
u32 power_setting = 0;
|
2020-04-14 15:38:45 +00:00
|
|
|
int ret = 0;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2014-05-17 08:50:18 +00:00
|
|
|
power += vnt_rf_addpower(priv);
|
|
|
|
if (power > VNT_RF_MAX_POWER)
|
|
|
|
power = VNT_RF_MAX_POWER;
|
|
|
|
|
2014-07-20 14:33:18 +00:00
|
|
|
if (priv->power == power)
|
2020-04-14 15:38:45 +00:00
|
|
|
return 0;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2014-07-20 14:33:18 +00:00
|
|
|
priv->power = power;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2014-07-19 11:30:07 +00:00
|
|
|
switch (priv->rf_type) {
|
2013-05-27 13:03:42 +00:00
|
|
|
case RF_AL2230:
|
2020-04-02 20:45:21 +00:00
|
|
|
power_setting = 0x0404090 | (power << 12);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-06 19:31:16 +00:00
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM)
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, 0x0001b400);
|
2013-05-27 13:03:42 +00:00
|
|
|
else
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, 0x0005a400);
|
|
|
|
|
2013-05-27 13:03:42 +00:00
|
|
|
break;
|
|
|
|
case RF_AL2230S:
|
2020-04-02 20:45:21 +00:00
|
|
|
power_setting = 0x0404090 | (power << 12);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-06 19:31:16 +00:00
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, 0x040c1400);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00299b00);
|
2013-05-27 13:03:42 +00:00
|
|
|
} else {
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, 0x0005a400);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00099b00);
|
2013-05-27 13:03:42 +00:00
|
|
|
}
|
2020-04-14 15:38:45 +00:00
|
|
|
|
2013-05-27 13:03:42 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case RF_AIROHA7230:
|
2020-04-06 19:31:16 +00:00
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM)
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, 0x111bb900);
|
2013-05-27 13:03:42 +00:00
|
|
|
else
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, 0x221bb900);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2014-07-05 18:24:21 +00:00
|
|
|
if (power >= AL7230_PWR_IDX_LEN)
|
2020-04-14 15:38:45 +00:00
|
|
|
return -EINVAL;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
|
|
|
/*
|
2016-11-20 20:51:40 +00:00
|
|
|
* 0x080F1B00 for 3 wire control TxGain(D10)
|
|
|
|
* and 0x31 as TX Gain value
|
|
|
|
*/
|
2014-07-12 10:30:02 +00:00
|
|
|
power_setting = 0x080c0b00 | (power << 12);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
2013-05-27 13:03:42 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case RF_VT3226:
|
2014-07-05 18:24:21 +00:00
|
|
|
if (power >= VT3226_PWR_IDX_LEN)
|
2020-04-14 15:38:45 +00:00
|
|
|
return -EINVAL;
|
2014-07-12 10:30:02 +00:00
|
|
|
power_setting = ((0x3f - power) << 20) | (0x17 << 8);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
2013-05-27 13:03:42 +00:00
|
|
|
break;
|
|
|
|
case RF_VT3226D0:
|
2014-07-05 18:24:21 +00:00
|
|
|
if (power >= VT3226_PWR_IDX_LEN)
|
2020-04-14 15:38:45 +00:00
|
|
|
return -EINVAL;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-06 19:31:16 +00:00
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
|
|
|
|
u16 hw_value = ch->hw_value;
|
2014-06-25 20:14:35 +00:00
|
|
|
|
2014-07-12 10:30:02 +00:00
|
|
|
power_setting = ((0x3f - power) << 20) | (0xe07 << 8);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x03c6a200);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2014-06-25 20:14:35 +00:00
|
|
|
dev_dbg(&priv->usb->dev,
|
|
|
|
"%s 11b channel [%d]\n", __func__, hw_value);
|
|
|
|
|
|
|
|
hw_value--;
|
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
if (hw_value < ARRAY_SIZE(vt3226d0_lo_current_table)) {
|
|
|
|
ret = vnt_rf_write_embedded(priv,
|
2014-06-25 20:14:35 +00:00
|
|
|
vt3226d0_lo_current_table[hw_value]);
|
2020-04-14 15:38:45 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, 0x015C0800);
|
2013-01-17 23:19:37 +00:00
|
|
|
} else {
|
2014-05-27 20:05:26 +00:00
|
|
|
dev_dbg(&priv->usb->dev,
|
2017-04-02 20:48:11 +00:00
|
|
|
"@@@@ %s> 11G mode\n", __func__);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2014-07-12 10:30:02 +00:00
|
|
|
power_setting = ((0x3f - power) << 20) | (0x7 << 8);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00C6A200);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x016BC600);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = vnt_rf_write_embedded(priv, 0x00900800);
|
2013-01-17 23:19:37 +00:00
|
|
|
}
|
2020-04-14 15:38:45 +00:00
|
|
|
|
2013-05-27 13:03:42 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case RF_VT3342A0:
|
2014-07-05 18:24:21 +00:00
|
|
|
if (power >= VT3342_PWR_IDX_LEN)
|
2020-04-14 15:38:45 +00:00
|
|
|
return -EINVAL;
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2014-07-12 10:30:02 +00:00
|
|
|
power_setting = ((0x3f - power) << 20) | (0x27 << 8);
|
2013-05-27 13:03:42 +00:00
|
|
|
|
2020-04-14 15:38:45 +00:00
|
|
|
ret = vnt_rf_write_embedded(priv, power_setting);
|
2013-05-27 13:03:42 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return ret;
|
2009-06-13 11:38:31 +00:00
|
|
|
}
|
|
|
|
|
2020-04-06 19:31:16 +00:00
|
|
|
/* Set Tx power by channel number type */
|
|
|
|
int vnt_rf_setpower(struct vnt_private *priv,
|
|
|
|
struct ieee80211_channel *ch)
|
|
|
|
{
|
|
|
|
u16 channel;
|
|
|
|
u8 power = priv->cck_pwr;
|
|
|
|
|
|
|
|
if (!ch)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* set channel number to array number */
|
|
|
|
channel = ch->hw_value - 1;
|
|
|
|
|
|
|
|
if (ch->flags & IEEE80211_CHAN_NO_OFDM) {
|
|
|
|
if (channel < ARRAY_SIZE(priv->cck_pwr_tbl))
|
|
|
|
power = priv->cck_pwr_tbl[channel];
|
|
|
|
} else if (ch->band == NL80211_BAND_5GHZ) {
|
|
|
|
/* remove 14 channels to array size */
|
|
|
|
channel -= 14;
|
|
|
|
|
|
|
|
if (channel < ARRAY_SIZE(priv->ofdm_a_pwr_tbl))
|
|
|
|
power = priv->ofdm_a_pwr_tbl[channel];
|
|
|
|
} else {
|
|
|
|
if (channel < ARRAY_SIZE(priv->ofdm_pwr_tbl))
|
|
|
|
power = priv->ofdm_pwr_tbl[channel];
|
|
|
|
}
|
|
|
|
|
|
|
|
return vnt_rf_set_txpower(priv, power, ch);
|
|
|
|
}
|
|
|
|
|
2014-07-12 10:30:03 +00:00
|
|
|
/* Convert rssi to dbm */
|
2014-05-27 20:05:23 +00:00
|
|
|
void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm)
|
2009-06-13 11:38:31 +00:00
|
|
|
{
|
2016-10-18 00:01:26 +00:00
|
|
|
u8 idx = ((rssi & 0xc0) >> 6) & 0x03;
|
|
|
|
long b = rssi & 0x3f;
|
2013-05-27 13:05:51 +00:00
|
|
|
long a = 0;
|
|
|
|
u8 airoharf[4] = {0, 18, 0, 40};
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2014-07-19 11:30:07 +00:00
|
|
|
switch (priv->rf_type) {
|
2013-05-27 13:05:51 +00:00
|
|
|
case RF_AL2230:
|
|
|
|
case RF_AL2230S:
|
|
|
|
case RF_AIROHA7230:
|
|
|
|
case RF_VT3226:
|
|
|
|
case RF_VT3226D0:
|
|
|
|
case RF_VT3342A0:
|
|
|
|
a = airoharf[idx];
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
*dbm = -1 * (a + b * 2);
|
2009-06-13 11:38:31 +00:00
|
|
|
}
|
|
|
|
|
2019-05-20 16:39:02 +00:00
|
|
|
int vnt_rf_table_download(struct vnt_private *priv)
|
2009-06-13 11:38:31 +00:00
|
|
|
{
|
2020-04-25 15:17:46 +00:00
|
|
|
int ret;
|
2013-05-27 13:07:27 +00:00
|
|
|
u16 length1 = 0, length2 = 0, length3 = 0;
|
|
|
|
u8 *addr1 = NULL, *addr2 = NULL, *addr3 = NULL;
|
2009-06-13 11:38:31 +00:00
|
|
|
|
2014-07-19 11:30:07 +00:00
|
|
|
switch (priv->rf_type) {
|
2013-05-27 13:07:27 +00:00
|
|
|
case RF_AL2230:
|
|
|
|
case RF_AL2230S:
|
|
|
|
length1 = CB_AL2230_INIT_SEQ * 3;
|
|
|
|
length2 = CB_MAX_CHANNEL_24G * 3;
|
|
|
|
length3 = CB_MAX_CHANNEL_24G * 3;
|
2013-05-27 13:09:52 +00:00
|
|
|
addr1 = &al2230_init_table[0][0];
|
|
|
|
addr2 = &al2230_channel_table0[0][0];
|
|
|
|
addr3 = &al2230_channel_table1[0][0];
|
2013-05-27 13:07:27 +00:00
|
|
|
break;
|
|
|
|
case RF_AIROHA7230:
|
|
|
|
length1 = CB_AL7230_INIT_SEQ * 3;
|
|
|
|
length2 = CB_MAX_CHANNEL * 3;
|
|
|
|
length3 = CB_MAX_CHANNEL * 3;
|
2013-05-27 13:09:52 +00:00
|
|
|
addr1 = &al7230_init_table[0][0];
|
|
|
|
addr2 = &al7230_channel_table0[0][0];
|
|
|
|
addr3 = &al7230_channel_table1[0][0];
|
2013-05-27 13:07:27 +00:00
|
|
|
break;
|
|
|
|
case RF_VT3226:
|
|
|
|
length1 = CB_VT3226_INIT_SEQ * 3;
|
|
|
|
length2 = CB_MAX_CHANNEL_24G * 3;
|
|
|
|
length3 = CB_MAX_CHANNEL_24G * 3;
|
2014-05-27 20:05:25 +00:00
|
|
|
addr1 = &vt3226_init_table[0][0];
|
2013-05-27 13:09:52 +00:00
|
|
|
addr2 = &vt3226_channel_table0[0][0];
|
|
|
|
addr3 = &vt3226_channel_table1[0][0];
|
2013-05-27 13:07:27 +00:00
|
|
|
break;
|
|
|
|
case RF_VT3226D0:
|
|
|
|
length1 = CB_VT3226_INIT_SEQ * 3;
|
|
|
|
length2 = CB_MAX_CHANNEL_24G * 3;
|
|
|
|
length3 = CB_MAX_CHANNEL_24G * 3;
|
2014-05-27 20:05:25 +00:00
|
|
|
addr1 = &vt3226d0_init_table[0][0];
|
2013-05-27 13:09:52 +00:00
|
|
|
addr2 = &vt3226_channel_table0[0][0];
|
|
|
|
addr3 = &vt3226_channel_table1[0][0];
|
2013-05-27 13:07:27 +00:00
|
|
|
break;
|
|
|
|
case RF_VT3342A0:
|
|
|
|
length1 = CB_VT3342_INIT_SEQ * 3;
|
|
|
|
length2 = CB_MAX_CHANNEL * 3;
|
|
|
|
length3 = CB_MAX_CHANNEL * 3;
|
2013-05-27 13:09:52 +00:00
|
|
|
addr1 = &vt3342a0_init_table[0][0];
|
|
|
|
addr2 = &vt3342_channel_table0[0][0];
|
|
|
|
addr3 = &vt3342_channel_table1[0][0];
|
2013-05-27 13:07:27 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Init Table */
|
2019-05-20 16:39:02 +00:00
|
|
|
ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
|
2020-04-25 15:17:45 +00:00
|
|
|
MESSAGE_REQUEST_RF_INIT, length1, addr1);
|
2019-05-20 16:39:02 +00:00
|
|
|
if (ret)
|
2020-04-25 15:17:46 +00:00
|
|
|
return ret;
|
2013-05-27 13:07:27 +00:00
|
|
|
|
|
|
|
/* Channel Table 0 */
|
2020-04-25 15:17:47 +00:00
|
|
|
ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
|
|
|
|
MESSAGE_REQUEST_RF_CH0, length2, addr2);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-05-27 13:07:27 +00:00
|
|
|
|
2020-04-25 15:17:47 +00:00
|
|
|
/* Channel Table 1 */
|
|
|
|
ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
|
|
|
|
MESSAGE_REQUEST_RF_CH1, length3, addr3);
|
2013-05-27 13:07:27 +00:00
|
|
|
|
2014-07-19 11:30:07 +00:00
|
|
|
if (priv->rf_type == RF_AIROHA7230) {
|
2013-05-27 13:07:27 +00:00
|
|
|
length1 = CB_AL7230_INIT_SEQ * 3;
|
|
|
|
length2 = CB_MAX_CHANNEL * 3;
|
2016-02-26 12:57:05 +00:00
|
|
|
addr1 = &al7230_init_table_amode[0][0];
|
|
|
|
addr2 = &al7230_channel_table2[0][0];
|
2013-05-27 13:07:27 +00:00
|
|
|
|
|
|
|
/* Init Table 2 */
|
2019-05-20 16:39:02 +00:00
|
|
|
ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
|
2020-04-25 15:17:45 +00:00
|
|
|
MESSAGE_REQUEST_RF_INIT2, length1, addr1);
|
2019-05-20 16:39:02 +00:00
|
|
|
if (ret)
|
2020-04-25 15:17:46 +00:00
|
|
|
return ret;
|
2013-05-27 13:07:27 +00:00
|
|
|
|
2020-04-25 15:17:47 +00:00
|
|
|
/* Channel Table 2 */
|
|
|
|
ret = vnt_control_out_blocks(priv, VNT_REG_BLOCK_SIZE,
|
|
|
|
MESSAGE_REQUEST_RF_CH2, length2,
|
|
|
|
addr2);
|
2013-05-27 13:07:27 +00:00
|
|
|
}
|
2019-05-20 16:39:02 +00:00
|
|
|
|
2020-04-25 15:17:47 +00:00
|
|
|
return ret;
|
2009-06-13 11:38:31 +00:00
|
|
|
}
|