2017-09-12 19:58:20 +00:00
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef _CORE_TYPES_H_
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#define _CORE_TYPES_H_
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#include "dc.h"
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2017-03-21 22:17:12 +00:00
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#include "dce_calcs.h"
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2017-06-15 20:27:42 +00:00
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#include "dcn_calcs.h"
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2017-09-12 19:58:20 +00:00
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#include "ddc_service_types.h"
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#include "dc_bios_types.h"
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2017-06-15 20:27:42 +00:00
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#include "mem_input.h"
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2017-08-03 14:20:52 +00:00
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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2017-06-15 20:27:42 +00:00
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#include "mpc.h"
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2017-08-03 14:20:52 +00:00
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#endif
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#include "dwb.h"
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2017-09-12 19:58:20 +00:00
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#define MAX_CLOCK_SOURCES 7
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2017-07-27 13:55:38 +00:00
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void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
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2017-09-12 19:58:20 +00:00
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uint32_t controller_id);
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#include "grph_object_id.h"
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#include "link_encoder.h"
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#include "stream_encoder.h"
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#include "clock_source.h"
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#include "audio.h"
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#include "hw_sequencer_types.h"
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2017-08-13 17:50:52 +00:00
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#include "dm_pp_smu.h"
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2017-09-12 19:58:20 +00:00
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/************ link *****************/
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struct link_init_data {
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2017-08-01 19:00:25 +00:00
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const struct dc *dc;
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2017-09-12 19:58:20 +00:00
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struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
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uint32_t connector_index; /* this will be mapped to the HPD pins */
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uint32_t link_index; /* this is mapped to DAL display_index
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TODO: remove it when DC is complete. */
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};
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2017-07-23 00:05:20 +00:00
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struct dc_link *link_create(const struct link_init_data *init_params);
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void link_destroy(struct dc_link **link);
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2017-09-12 19:58:20 +00:00
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enum dc_status dc_link_validate_mode_timing(
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2017-07-27 13:33:33 +00:00
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const struct dc_stream_state *stream,
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2017-07-23 00:05:20 +00:00
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struct dc_link *link,
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2017-09-12 19:58:20 +00:00
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const struct dc_crtc_timing *timing);
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2017-07-23 00:05:20 +00:00
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void core_link_resume(struct dc_link *link);
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2017-09-12 19:58:20 +00:00
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void core_link_enable_stream(struct pipe_ctx *pipe_ctx);
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void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
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2017-07-17 20:04:02 +00:00
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void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
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2017-09-12 19:58:20 +00:00
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/********** DAL Core*********************/
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2016-12-02 19:48:04 +00:00
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#include "display_clock.h"
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2017-09-12 19:58:20 +00:00
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#include "transform.h"
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struct resource_pool;
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struct validate_context;
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struct resource_context;
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struct resource_funcs {
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void (*destroy)(struct resource_pool **pool);
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struct link_encoder *(*link_enc_create)(
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const struct encoder_init_data *init);
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enum dc_status (*validate_guaranteed)(
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2017-08-01 19:00:25 +00:00
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struct dc *dc,
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2017-07-27 13:33:33 +00:00
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struct dc_stream_state *stream,
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2017-09-12 19:58:20 +00:00
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struct validate_context *context);
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2017-02-24 19:19:40 +00:00
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bool (*validate_bandwidth)(
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2017-08-01 19:00:25 +00:00
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struct dc *dc,
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2017-09-12 19:58:20 +00:00
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struct validate_context *context);
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2017-07-31 15:29:25 +00:00
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enum dc_status (*validate_global)(
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struct dc *dc,
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struct validate_context *context);
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2017-09-12 19:58:20 +00:00
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struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
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2017-03-14 16:30:29 +00:00
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struct validate_context *context,
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2017-04-22 18:17:51 +00:00
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const struct resource_pool *pool,
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2017-07-27 13:33:33 +00:00
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struct dc_stream_state *stream);
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2017-07-31 15:29:25 +00:00
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2017-07-27 13:24:04 +00:00
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enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state);
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2017-07-31 15:29:25 +00:00
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enum dc_status (*add_stream_to_ctx)(
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struct dc *dc,
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struct validate_context *new_ctx,
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struct dc_stream_state *dc_stream);
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2017-09-12 19:58:20 +00:00
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};
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struct audio_support{
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bool dp_audio;
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bool hdmi_audio_on_dongle;
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bool hdmi_audio_native;
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};
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2017-01-23 16:49:24 +00:00
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#define NO_UNDERLAY_PIPE -1
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2017-09-12 19:58:20 +00:00
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struct resource_pool {
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struct mem_input *mis[MAX_PIPES];
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struct input_pixel_processor *ipps[MAX_PIPES];
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struct transform *transforms[MAX_PIPES];
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struct output_pixel_processor *opps[MAX_PIPES];
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struct timing_generator *timing_generators[MAX_PIPES];
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struct stream_encoder *stream_enc[MAX_PIPES * 2];
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2017-08-20 18:25:19 +00:00
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2017-07-21 21:46:50 +00:00
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struct mpc *mpc;
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2017-08-13 17:50:52 +00:00
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struct pp_smu_funcs_rv *pp_smu;
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2017-08-20 18:25:19 +00:00
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struct pp_smu_display_requirement_rv pp_smu_req;
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2017-09-12 19:58:20 +00:00
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2017-08-03 14:20:52 +00:00
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struct dwbc *dwbc[MAX_DWB_PIPES];
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2017-09-12 19:58:20 +00:00
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unsigned int pipe_count;
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unsigned int underlay_pipe_index;
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unsigned int stream_enc_count;
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2017-03-03 18:44:35 +00:00
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unsigned int ref_clock_inKhz;
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2017-09-12 19:58:20 +00:00
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/*
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* reserved clock source for DP
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*/
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struct clock_source *dp_clock_source;
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struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
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unsigned int clk_src_count;
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struct audio *audios[MAX_PIPES];
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unsigned int audio_count;
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struct audio_support audio_support;
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struct display_clock *display_clock;
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struct irq_service *irqs;
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2017-01-23 21:55:20 +00:00
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struct abm *abm;
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struct dmcu *dmcu;
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2017-09-12 19:58:20 +00:00
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const struct resource_funcs *funcs;
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const struct resource_caps *res_cap;
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};
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2017-07-30 15:43:06 +00:00
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struct stream_resource {
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2017-07-30 17:55:28 +00:00
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struct output_pixel_processor *opp;
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2017-07-30 17:59:26 +00:00
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struct timing_generator *tg;
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2017-07-30 18:36:12 +00:00
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struct stream_encoder *stream_enc;
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2017-07-30 18:59:17 +00:00
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struct audio *audio;
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2017-07-30 19:17:43 +00:00
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struct pixel_clk_params pix_clk_params;
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2017-07-30 19:58:26 +00:00
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struct encoder_info_frame encoder_info_frame;
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2017-07-30 15:43:06 +00:00
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};
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struct plane_resource {
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2017-07-30 15:51:21 +00:00
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struct scaler_data scl_data;
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2017-07-30 15:55:55 +00:00
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struct mem_input *mi;
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struct input_pixel_processor *ipp;
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struct transform *xfm;
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2017-07-30 15:43:06 +00:00
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};
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2017-09-12 19:58:20 +00:00
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struct pipe_ctx {
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2017-07-27 13:55:38 +00:00
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struct dc_plane_state *plane_state;
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2017-07-27 13:33:33 +00:00
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struct dc_stream_state *stream;
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2017-09-12 19:58:20 +00:00
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2017-07-30 15:43:06 +00:00
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struct plane_resource plane_res;
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struct stream_resource stream_res;
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2017-09-12 19:58:20 +00:00
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struct display_clock *dis_clk;
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struct clock_source *clock_source;
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struct pll_settings pll_settings;
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uint8_t pipe_idx;
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struct pipe_ctx *top_pipe;
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struct pipe_ctx *bottom_pipe;
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2017-06-01 22:35:54 +00:00
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2017-06-15 20:27:42 +00:00
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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struct _vcs_dpi_display_dlg_regs_st dlg_regs;
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struct _vcs_dpi_display_ttu_regs_st ttu_regs;
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struct _vcs_dpi_display_rq_regs_st rq_regs;
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struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
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#endif
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2017-08-03 14:20:52 +00:00
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struct dwbc *dwbc;
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2017-09-12 19:58:20 +00:00
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};
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struct resource_context {
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struct pipe_ctx pipe_ctx[MAX_PIPES];
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bool is_stream_enc_acquired[MAX_PIPES * 2];
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bool is_audio_acquired[MAX_PIPES];
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uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
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uint8_t dp_clock_source_ref_count;
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2017-05-02 21:29:48 +00:00
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};
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struct dce_bw_output {
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bool cpuc_state_change_enable;
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bool cpup_state_change_enable;
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bool stutter_mode_enable;
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bool nbp_state_change_enable;
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bool all_displays_in_sync;
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struct dce_watermarks urgent_wm_ns[MAX_PIPES];
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struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
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struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
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int sclk_khz;
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int sclk_deep_sleep_khz;
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int yclk_khz;
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int dispclk_khz;
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int blackout_recovery_time_us;
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};
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struct dcn_bw_clocks {
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int dispclk_khz;
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bool dppclk_div;
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int dcfclk_khz;
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int dcfclk_deep_sleep_khz;
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int fclk_khz;
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int dram_ccm_us;
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int min_active_dram_ccm_us;
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};
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struct dcn_bw_output {
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struct dcn_bw_clocks cur_clk;
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struct dcn_bw_clocks calc_clk;
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struct dcn_watermark_set watermarks;
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};
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union bw_context {
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struct dcn_bw_output dcn;
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struct dce_bw_output dce;
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};
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2017-09-12 19:58:20 +00:00
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struct validate_context {
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2017-07-27 13:33:33 +00:00
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struct dc_stream_state *streams[MAX_PIPES];
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2016-12-29 20:27:12 +00:00
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struct dc_stream_status stream_status[MAX_PIPES];
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uint8_t stream_count;
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2017-09-12 19:58:20 +00:00
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struct resource_context res_ctx;
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/* The output from BW and WM calculations. */
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2017-05-02 21:29:48 +00:00
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union bw_context bw;
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2016-12-05 23:03:04 +00:00
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/* Note: these are big structures, do *not* put on stack! */
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2017-09-12 19:58:20 +00:00
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struct dm_pp_display_configuration pp_display_cfg;
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2017-06-15 20:27:42 +00:00
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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struct dcn_bw_internal_vars dcn_bw_vars;
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#endif
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2017-07-11 18:41:51 +00:00
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2017-07-31 21:10:44 +00:00
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atomic_t ref_count;
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2017-09-12 19:58:20 +00:00
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};
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#endif /* _CORE_TYPES_H_ */
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