2020-10-13 14:45:52 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common LiteX header providing
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* helper functions for accessing CSRs.
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*
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* Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
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*/
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#ifndef _LINUX_LITEX_H
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#define _LINUX_LITEX_H
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/compiler_types.h>
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/*
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* The parameters below are true for LiteX SoCs configured for 8-bit CSR Bus,
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* 32-bit aligned.
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*
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* Supporting other configurations will require extending the logic in this
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* header and in the LiteX SoC controller driver.
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*/
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#define LITEX_REG_SIZE 0x4
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#define LITEX_SUBREG_SIZE 0x1
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#define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8)
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#define WRITE_LITEX_SUBREGISTER(val, base_offset, subreg_id) \
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writel((u32 __force)cpu_to_le32(val), base_offset + (LITEX_REG_SIZE * subreg_id))
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#define READ_LITEX_SUBREGISTER(base_offset, subreg_id) \
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le32_to_cpu((__le32 __force)readl(base_offset + (LITEX_REG_SIZE * subreg_id)))
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2021-01-12 17:31:40 +00:00
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/*
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* LiteX SoC Generator, depending on the configuration, can split a single
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* logical CSR (Control&Status Register) into a series of consecutive physical
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* registers.
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*
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* For example, in the configuration with 8-bit CSR Bus, 32-bit aligned (the
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* default one for 32-bit CPUs) a 32-bit logical CSR will be generated as four
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* 32-bit physical registers, each one containing one byte of meaningful data.
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*
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* For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
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*
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* The purpose of `litex_set_reg`/`litex_get_reg` is to implement the logic
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* of writing to/reading from the LiteX CSR in a single place that can be
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* then reused by all LiteX drivers.
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*/
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/**
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* litex_set_reg() - Writes the value to the LiteX CSR (Control&Status Register)
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* @reg: Address of the CSR
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* @reg_size: The width of the CSR expressed in the number of bytes
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* @val: Value to be written to the CSR
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*
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* In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
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* a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
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* each one containing one byte of meaningful data.
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*
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* This function splits a single possibly multi-byte write into a series of
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* single-byte writes with a proper offset.
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*/
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static inline void litex_set_reg(void __iomem *reg, ulong reg_size, ulong val)
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{
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ulong shifted_data, shift, i;
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for (i = 0; i < reg_size; ++i) {
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shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
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shifted_data = val >> shift;
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WRITE_LITEX_SUBREGISTER(shifted_data, reg, i);
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}
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}
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/**
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* litex_get_reg() - Reads the value of the LiteX CSR (Control&Status Register)
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* @reg: Address of the CSR
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* @reg_size: The width of the CSR expressed in the number of bytes
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*
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* Return: Value read from the CSR
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*
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* In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
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* a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
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* each one containing one byte of meaningful data.
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*
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* This function generates a series of single-byte reads with a proper offset
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* and joins their results into a single multi-byte value.
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*/
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static inline ulong litex_get_reg(void __iomem *reg, ulong reg_size)
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{
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ulong shifted_data, shift, i;
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ulong result = 0;
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for (i = 0; i < reg_size; ++i) {
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shifted_data = READ_LITEX_SUBREGISTER(reg, i);
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shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
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result |= (shifted_data << shift);
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}
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return result;
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}
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2020-10-13 14:45:52 +00:00
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static inline void litex_write8(void __iomem *reg, u8 val)
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{
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WRITE_LITEX_SUBREGISTER(val, reg, 0);
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}
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static inline void litex_write16(void __iomem *reg, u16 val)
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{
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WRITE_LITEX_SUBREGISTER(val >> 8, reg, 0);
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WRITE_LITEX_SUBREGISTER(val, reg, 1);
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}
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static inline void litex_write32(void __iomem *reg, u32 val)
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{
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WRITE_LITEX_SUBREGISTER(val >> 24, reg, 0);
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WRITE_LITEX_SUBREGISTER(val >> 16, reg, 1);
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WRITE_LITEX_SUBREGISTER(val >> 8, reg, 2);
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WRITE_LITEX_SUBREGISTER(val, reg, 3);
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}
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static inline void litex_write64(void __iomem *reg, u64 val)
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{
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WRITE_LITEX_SUBREGISTER(val >> 56, reg, 0);
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WRITE_LITEX_SUBREGISTER(val >> 48, reg, 1);
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WRITE_LITEX_SUBREGISTER(val >> 40, reg, 2);
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WRITE_LITEX_SUBREGISTER(val >> 32, reg, 3);
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WRITE_LITEX_SUBREGISTER(val >> 24, reg, 4);
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WRITE_LITEX_SUBREGISTER(val >> 16, reg, 5);
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WRITE_LITEX_SUBREGISTER(val >> 8, reg, 6);
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WRITE_LITEX_SUBREGISTER(val, reg, 7);
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}
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static inline u8 litex_read8(void __iomem *reg)
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{
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return READ_LITEX_SUBREGISTER(reg, 0);
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}
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static inline u16 litex_read16(void __iomem *reg)
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{
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return (READ_LITEX_SUBREGISTER(reg, 0) << 8)
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| (READ_LITEX_SUBREGISTER(reg, 1));
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}
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static inline u32 litex_read32(void __iomem *reg)
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{
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return (READ_LITEX_SUBREGISTER(reg, 0) << 24)
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| (READ_LITEX_SUBREGISTER(reg, 1) << 16)
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| (READ_LITEX_SUBREGISTER(reg, 2) << 8)
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| (READ_LITEX_SUBREGISTER(reg, 3));
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}
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static inline u64 litex_read64(void __iomem *reg)
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{
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return ((u64)READ_LITEX_SUBREGISTER(reg, 0) << 56)
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| ((u64)READ_LITEX_SUBREGISTER(reg, 1) << 48)
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| ((u64)READ_LITEX_SUBREGISTER(reg, 2) << 40)
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| ((u64)READ_LITEX_SUBREGISTER(reg, 3) << 32)
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| ((u64)READ_LITEX_SUBREGISTER(reg, 4) << 24)
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| ((u64)READ_LITEX_SUBREGISTER(reg, 5) << 16)
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| ((u64)READ_LITEX_SUBREGISTER(reg, 6) << 8)
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| ((u64)READ_LITEX_SUBREGISTER(reg, 7));
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}
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#endif /* _LINUX_LITEX_H */
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