linux-stable/drivers/gpu/drm/i915/display/intel_bw.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2019 Intel Corporation
 */

#ifndef __INTEL_BW_H__
#define __INTEL_BW_H__

#include <drm/drm_atomic.h>

#include "intel_display.h"

struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;

struct intel_bw_state {
	struct drm_private_state base;

	unsigned int data_rate[I915_MAX_PIPES];
	u8 num_active_planes[I915_MAX_PIPES];
};

#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)

void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
			  const struct intel_crtc_state *crtc_state);

#endif /* __INTEL_BW_H__ */
drm/i915: Make sure we have enough memory bandwidth on ICL ICL has so many planes that it can easily exceed the maximum effective memory bandwidth of the system. We must therefore check that we don't exceed that limit. The algorithm is very magic number heavy and lacks sufficient explanation for now. We also have no sane way to query the memory clock and timings, so we must rely on a combination of raw readout from the memory controller and hardcoded assumptions. The memory controller values obviously change as the system jumps between the different SAGV points, so we try to stabilize it first by disabling SAGV for the duration of the readout. The utilized bandwidth is tracked via a device wide atomic private object. That is actually not robust because we can't afford to enforce strict global ordering between the pipes. Thus I think I'll need to change this to simply chop up the available bandwidth between all the active pipes. Each pipe can then do whatever it wants as long as it doesn't exceed its budget. That scheme will also require that we assume that any number of planes could be active at any time. TODO: make it robust and deal with all the open questions v2: Sleep longer after disabling SAGV v3: Poll for the dclk to get raised (seen it take 250ms!) If the system has 2133MT/s memory then we pointlessly wait one full second :( v4: Use the new pcode interface to get the qgv points rather that using hardcoded numbers v5: Move the pcode stuff into intel_bw.c (Matt) s/intel_sagv_info/intel_qgv_info/ Do the NV12/P010 as per spec for now (Matt) s/IS_ICELAKE/IS_GEN11/ v6: Ignore bandwidth limits if the pcode query fails Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Clint Taylor <Clinton.A.Taylor@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190524153614.32410-1-ville.syrjala@linux.intel.com 2019-05-24 15:36:14 +00:00			`/* SPDX-License-Identifier: MIT */`
			`/*`
			`* Copyright © 2019 Intel Corporation`
			`*/`

			`#ifndef __INTEL_BW_H__`
			`#define __INTEL_BW_H__`

			`#include <drm/drm_atomic.h>`

			`#include "intel_display.h"`

			`struct drm_i915_private;`
			`struct intel_atomic_state;`
			`struct intel_crtc_state;`

			`struct intel_bw_state {`
			`struct drm_private_state base;`

			`unsigned int data_rate[I915_MAX_PIPES];`
			`u8 num_active_planes[I915_MAX_PIPES];`
			`};`

			`#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)`

			`void intel_bw_init_hw(struct drm_i915_private *dev_priv);`
			`int intel_bw_init(struct drm_i915_private *dev_priv);`
			`int intel_bw_atomic_check(struct intel_atomic_state *state);`
			`void intel_bw_crtc_update(struct intel_bw_state *bw_state,`
			`const struct intel_crtc_state *crtc_state);`

			`#endif /* __INTEL_BW_H__ */`