2009-12-17 23:27:20 +00:00
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/*
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* Freescale eSDHC controller driver.
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*
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2011-09-09 12:05:46 +00:00
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* Copyright (c) 2007, 2010 Freescale Semiconductor, Inc.
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2009-12-17 23:27:20 +00:00
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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2011-07-03 19:15:51 +00:00
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#include <linux/module.h>
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2009-12-17 23:27:20 +00:00
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#include <linux/mmc/host.h>
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2011-05-27 15:48:14 +00:00
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#include "sdhci-pltfm.h"
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2010-10-15 10:21:03 +00:00
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#include "sdhci-esdhc.h"
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2009-12-17 23:27:20 +00:00
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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2011-09-09 12:05:46 +00:00
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int base = reg & ~0x3;
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int shift = (reg & 0x2) * 8;
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2009-12-17 23:27:20 +00:00
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if (unlikely(reg == SDHCI_HOST_VERSION))
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2011-09-09 12:05:46 +00:00
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ret = in_be32(host->ioaddr + base) & 0xffff;
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2009-12-17 23:27:20 +00:00
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else
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2011-09-09 12:05:46 +00:00
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ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
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return ret;
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}
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static u8 esdhc_readb(struct sdhci_host *host, int reg)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
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2012-01-13 07:02:01 +00:00
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/*
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* "DMA select" locates at offset 0x28 in SD specification, but on
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* P5020 or P3041, it locates at 0x29.
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*/
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if (reg == SDHCI_HOST_CONTROL) {
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u32 dma_bits;
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dma_bits = in_be32(host->ioaddr + reg);
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
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/* fixup the result */
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ret &= ~SDHCI_CTRL_DMA_MASK;
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ret |= dma_bits;
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}
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2009-12-17 23:27:20 +00:00
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return ret;
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}
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static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (reg == SDHCI_BLOCK_SIZE) {
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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}
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sdhci_be32bs_writew(host, val, reg);
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}
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static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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2012-01-13 07:02:01 +00:00
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/*
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* "DMA select" location is offset 0x28 in SD specification, but on
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* P5020 or P3041, it's located at 0x29.
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*/
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if (reg == SDHCI_HOST_CONTROL) {
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u32 dma_bits;
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
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clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
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dma_bits);
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val &= ~SDHCI_CTRL_DMA_MASK;
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val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
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}
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2009-12-17 23:27:20 +00:00
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
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if (reg == SDHCI_HOST_CONTROL)
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val &= ~ESDHC_HOST_CONTROL_RES;
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sdhci_be32bs_writeb(host, val, reg);
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}
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2010-10-15 10:21:03 +00:00
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static int esdhc_of_enable_dma(struct sdhci_host *host)
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2009-12-17 23:27:20 +00:00
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{
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setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
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return 0;
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}
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2010-10-15 10:21:03 +00:00
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static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
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2009-12-17 23:27:20 +00:00
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{
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2011-07-20 21:13:36 +00:00
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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2009-12-17 23:27:20 +00:00
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2011-07-20 21:13:36 +00:00
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return pltfm_host->clock;
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2009-12-17 23:27:20 +00:00
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}
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2010-10-15 10:21:03 +00:00
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static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
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2009-12-17 23:27:20 +00:00
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{
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2011-07-20 21:13:36 +00:00
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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2009-12-17 23:27:20 +00:00
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2011-07-20 21:13:36 +00:00
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return pltfm_host->clock / 256 / 16;
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2009-12-17 23:27:20 +00:00
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}
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2011-07-20 21:13:36 +00:00
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static struct sdhci_ops sdhci_esdhc_ops = {
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.read_l = sdhci_be32bs_readl,
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.read_w = esdhc_readw,
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2011-09-09 12:05:46 +00:00
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.read_b = esdhc_readb,
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2011-07-20 21:13:36 +00:00
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.write_l = sdhci_be32bs_writel,
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.write_w = esdhc_writew,
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.write_b = esdhc_writeb,
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.set_clock = esdhc_set_clock,
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.enable_dma = esdhc_of_enable_dma,
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.get_max_clock = esdhc_of_get_max_clock,
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.get_min_clock = esdhc_of_get_min_clock,
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};
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2011-05-27 15:48:14 +00:00
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static struct sdhci_pltfm_data sdhci_esdhc_pdata = {
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2011-02-26 13:44:40 +00:00
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/* card detection could be handled via GPIO */
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2011-03-21 05:22:13 +00:00
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.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
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| SDHCI_QUIRK_NO_CARD_NO_RESET,
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2011-07-20 21:13:36 +00:00
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.ops = &sdhci_esdhc_ops,
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2009-12-17 23:27:20 +00:00
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};
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2011-05-27 15:48:14 +00:00
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static int __devinit sdhci_esdhc_probe(struct platform_device *pdev)
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{
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return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
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}
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static int __devexit sdhci_esdhc_remove(struct platform_device *pdev)
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{
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return sdhci_pltfm_unregister(pdev);
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}
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static const struct of_device_id sdhci_esdhc_of_match[] = {
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{ .compatible = "fsl,mpc8379-esdhc" },
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{ .compatible = "fsl,mpc8536-esdhc" },
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{ .compatible = "fsl,esdhc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
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static struct platform_driver sdhci_esdhc_driver = {
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.driver = {
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.name = "sdhci-esdhc",
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.owner = THIS_MODULE,
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.of_match_table = sdhci_esdhc_of_match,
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2011-11-03 10:09:45 +00:00
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.pm = SDHCI_PLTFM_PMOPS,
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2011-05-27 15:48:14 +00:00
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},
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.probe = sdhci_esdhc_probe,
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.remove = __devexit_p(sdhci_esdhc_remove),
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};
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2011-11-26 04:55:43 +00:00
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module_platform_driver(sdhci_esdhc_driver);
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2011-05-27 15:48:14 +00:00
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MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
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MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
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"Anton Vorontsov <avorontsov@ru.mvista.com>");
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MODULE_LICENSE("GPL v2");
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