2005-04-16 22:20:36 +00:00
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/*
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* PXA250/210 Power Management Routines
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*
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* Original code for the SA11x0:
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* Modified for the PXA250 by Nicolas Pitre:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License.
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*/
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#include <linux/init.h>
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2005-11-06 15:03:23 +00:00
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#include <linux/module.h>
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2005-04-16 22:20:36 +00:00
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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2008-08-04 09:41:28 +00:00
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#include <asm/arch/hardware.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/memory.h>
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#include <asm/system.h>
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2005-11-06 15:03:23 +00:00
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#include <asm/arch/pm.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/lubbock.h>
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#include <asm/mach/time.h>
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2007-07-18 10:38:45 +00:00
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struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
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static unsigned long *sleep_save;
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2005-04-16 22:20:36 +00:00
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2005-11-06 15:03:23 +00:00
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int pxa_pm_enter(suspend_state_t state)
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2005-04-16 22:20:36 +00:00
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{
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2007-07-18 10:38:45 +00:00
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unsigned long sleep_save_checksum = 0, checksum = 0;
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2005-04-16 22:20:36 +00:00
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int i;
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#ifdef CONFIG_IWMMXT
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/* force any iWMMXt context to ram **/
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[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)
Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch. Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.
CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.
This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.' This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.
These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 17:51:14 +00:00
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if (elf_hwcap & HWCAP_IWMMXT)
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iwmmxt_task_disable(NULL);
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2005-04-16 22:20:36 +00:00
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#endif
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2008-01-14 07:50:54 +00:00
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/* skip registers saving for standby */
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if (state != PM_SUSPEND_STANDBY) {
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pxa_cpu_pm_fns->save(sleep_save);
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/* before sleeping, calculate and save a checksum */
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2008-05-02 20:17:06 +00:00
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for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
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2008-01-14 07:50:54 +00:00
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sleep_save_checksum += sleep_save[i];
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}
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2005-04-16 22:20:36 +00:00
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/* *** go zzz *** */
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2007-07-18 10:38:45 +00:00
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pxa_cpu_pm_fns->enter(state);
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2005-06-19 17:39:33 +00:00
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cpu_init();
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2008-01-14 07:50:54 +00:00
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if (state != PM_SUSPEND_STANDBY) {
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/* after sleeping, validate the checksum */
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2008-05-02 20:17:06 +00:00
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for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
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2008-01-14 07:50:54 +00:00
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checksum += sleep_save[i];
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2005-04-16 22:20:36 +00:00
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2008-01-14 07:50:54 +00:00
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/* if invalid, display message and wait for a hardware reset */
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if (checksum != sleep_save_checksum) {
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2005-04-16 22:20:36 +00:00
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#ifdef CONFIG_ARCH_LUBBOCK
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2008-01-14 07:50:54 +00:00
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LUB_HEXLED = 0xbadbadc5;
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2005-04-16 22:20:36 +00:00
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#endif
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2008-01-14 07:50:54 +00:00
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while (1)
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pxa_cpu_pm_fns->enter(state);
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}
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pxa_cpu_pm_fns->restore(sleep_save);
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2005-04-16 22:20:36 +00:00
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}
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2007-07-18 10:38:45 +00:00
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pr_debug("*** made it back from resume\n");
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2005-04-16 22:20:36 +00:00
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return 0;
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}
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2005-11-06 15:03:23 +00:00
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EXPORT_SYMBOL_GPL(pxa_pm_enter);
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2005-04-16 22:20:36 +00:00
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unsigned long sleep_phys_sp(void *sp)
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{
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return virt_to_phys(sp);
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}
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2007-07-18 10:38:45 +00:00
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static int pxa_pm_valid(suspend_state_t state)
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{
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if (pxa_cpu_pm_fns)
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return pxa_cpu_pm_fns->valid(state);
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return -EINVAL;
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}
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2007-10-18 10:04:40 +00:00
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static struct platform_suspend_ops pxa_pm_ops = {
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2007-07-18 10:38:45 +00:00
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.valid = pxa_pm_valid,
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.enter = pxa_pm_enter,
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};
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static int __init pxa_pm_init(void)
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{
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if (!pxa_cpu_pm_fns) {
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printk(KERN_ERR "no valid pxa_cpu_pm_fns defined\n");
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return -EINVAL;
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}
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2008-05-02 20:17:06 +00:00
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sleep_save = kmalloc(pxa_cpu_pm_fns->save_count * sizeof(unsigned long),
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GFP_KERNEL);
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2007-07-18 10:38:45 +00:00
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if (!sleep_save) {
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printk(KERN_ERR "failed to alloc memory for pm save\n");
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return -ENOMEM;
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}
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2007-10-18 10:04:40 +00:00
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suspend_set_ops(&pxa_pm_ops);
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2007-07-18 10:38:45 +00:00
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return 0;
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}
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device_initcall(pxa_pm_init);
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