License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2008-10-23 05:26:29 +00:00
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#ifndef _ASM_X86_PGTABLE_H
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#define _ASM_X86_PGTABLE_H
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2008-01-30 12:32:55 +00:00
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2017-07-17 21:10:07 +00:00
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#include <linux/mem_encrypt.h>
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2009-02-09 10:57:45 +00:00
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#include <asm/page.h>
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2009-02-09 02:46:18 +00:00
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#include <asm/pgtable_types.h>
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2008-09-23 21:00:36 +00:00
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2008-12-18 19:41:31 +00:00
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/*
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* Macro to mark a page protection value as UC-
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*/
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2014-11-03 13:01:53 +00:00
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#define pgprot_noncached(prot) \
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((boot_cpu_data.x86 > 3) \
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? (__pgprot(pgprot_val(prot) | \
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cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \
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2008-12-18 19:41:31 +00:00
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: (prot))
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2008-01-30 12:32:56 +00:00
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#ifndef __ASSEMBLY__
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2021-11-02 16:52:24 +00:00
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#include <linux/spinlock.h>
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2009-11-23 23:12:07 +00:00
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#include <asm/x86_init.h>
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2021-06-23 12:02:05 +00:00
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#include <asm/pkru.h>
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2019-04-03 16:41:48 +00:00
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#include <asm/fpu/api.h>
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2022-02-22 18:57:40 +00:00
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#include <asm/coco.h>
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2020-04-07 03:05:33 +00:00
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#include <asm-generic/pgtable_uffd.h>
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2022-01-14 22:06:41 +00:00
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#include <linux/page_table_check.h>
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2009-11-23 23:12:07 +00:00
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2017-07-17 21:10:11 +00:00
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extern pgd_t early_top_pgt[PTRS_PER_PGD];
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2020-09-07 13:15:36 +00:00
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bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd);
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2017-07-17 21:10:11 +00:00
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2023-05-16 19:57:29 +00:00
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struct seq_file;
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2020-02-04 01:36:11 +00:00
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void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm);
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2020-02-04 01:36:16 +00:00
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void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm,
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bool user);
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2015-10-05 16:55:20 +00:00
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void ptdump_walk_pgd_level_checkwx(void);
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2018-08-08 11:16:40 +00:00
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void ptdump_walk_user_pgd_level_checkwx(void);
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2015-10-05 16:55:20 +00:00
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2022-02-22 18:57:40 +00:00
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/*
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* Macros to add or remove encryption attribute
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*/
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#define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot)))
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#define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot)))
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2015-10-05 16:55:20 +00:00
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#ifdef CONFIG_DEBUG_WX
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2018-08-08 11:16:40 +00:00
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#define debug_checkwx() ptdump_walk_pgd_level_checkwx()
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#define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx()
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2015-10-05 16:55:20 +00:00
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#else
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2018-08-08 11:16:40 +00:00
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#define debug_checkwx() do { } while (0)
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#define debug_checkwx_user() do { } while (0)
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2015-10-05 16:55:20 +00:00
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#endif
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2014-01-18 11:48:14 +00:00
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2008-01-30 12:32:58 +00:00
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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2013-08-05 22:02:43 +00:00
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extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
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__visible;
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2019-04-29 16:51:29 +00:00
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#define ZERO_PAGE(vaddr) ((void)(vaddr),virt_to_page(empty_zero_page))
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2008-01-30 12:32:58 +00:00
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2008-01-30 12:34:11 +00:00
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extern spinlock_t pgd_lock;
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extern struct list_head pgd_list;
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2008-01-30 12:32:58 +00:00
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2010-09-21 19:01:51 +00:00
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extern struct mm_struct *pgd_page_get_mm(struct page *page);
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2017-07-17 21:10:07 +00:00
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extern pmdval_t early_pmd_flags;
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2018-08-28 07:40:25 +00:00
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#ifdef CONFIG_PARAVIRT_XXL
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2009-02-11 18:20:05 +00:00
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#include <asm/paravirt.h>
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2018-08-28 07:40:25 +00:00
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#else /* !CONFIG_PARAVIRT_XXL */
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2009-02-11 18:20:05 +00:00
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#define set_pte(ptep, pte) native_set_pte(ptep, pte)
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#define set_pte_atomic(ptep, pte) \
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native_set_pte_atomic(ptep, pte)
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#define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd)
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2017-03-17 18:55:15 +00:00
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#ifndef __PAGETABLE_P4D_FOLDED
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2009-02-11 18:20:05 +00:00
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#define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd)
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2018-05-18 10:35:24 +00:00
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#define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0)
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2009-02-11 18:20:05 +00:00
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#endif
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2017-03-17 18:55:15 +00:00
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#ifndef set_p4d
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# define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d)
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#endif
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#ifndef __PAGETABLE_PUD_FOLDED
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#define p4d_clear(p4d) native_p4d_clear(p4d)
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#endif
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2009-02-11 18:20:05 +00:00
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#ifndef set_pud
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# define set_pud(pudp, pud) native_set_pud(pudp, pud)
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#endif
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2017-03-16 23:40:24 +00:00
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#ifndef __PAGETABLE_PUD_FOLDED
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2009-02-11 18:20:05 +00:00
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#define pud_clear(pud) native_pud_clear(pud)
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#endif
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#define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep)
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#define pmd_clear(pmd) native_pmd_clear(pmd)
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#define pgd_val(x) native_pgd_val(x)
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#define __pgd(x) native_make_pgd(x)
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2017-03-17 18:55:15 +00:00
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#ifndef __PAGETABLE_P4D_FOLDED
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#define p4d_val(x) native_p4d_val(x)
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#define __p4d(x) native_make_p4d(x)
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#endif
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2009-02-11 18:20:05 +00:00
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#ifndef __PAGETABLE_PUD_FOLDED
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#define pud_val(x) native_pud_val(x)
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#define __pud(x) native_make_pud(x)
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#endif
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#ifndef __PAGETABLE_PMD_FOLDED
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#define pmd_val(x) native_pmd_val(x)
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#define __pmd(x) native_make_pmd(x)
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#endif
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#define pte_val(x) native_pte_val(x)
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#define __pte(x) native_make_pte(x)
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2009-02-18 19:18:57 +00:00
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#define arch_end_context_switch(prev) do {} while(0)
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2018-08-28 07:40:23 +00:00
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#endif /* CONFIG_PARAVIRT_XXL */
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2009-02-11 18:20:05 +00:00
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2008-01-30 12:32:56 +00:00
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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2008-03-23 08:03:12 +00:00
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static inline int pte_dirty(pte_t pte)
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{
|
2008-05-26 22:31:06 +00:00
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return pte_flags(pte) & _PAGE_DIRTY;
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2008-03-23 08:03:12 +00:00
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}
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static inline int pte_young(pte_t pte)
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{
|
2008-05-26 22:31:06 +00:00
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return pte_flags(pte) & _PAGE_ACCESSED;
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2008-03-23 08:03:12 +00:00
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}
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2014-12-10 23:44:36 +00:00
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static inline int pmd_dirty(pmd_t pmd)
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{
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return pmd_flags(pmd) & _PAGE_DIRTY;
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}
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2008-03-23 08:03:12 +00:00
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2022-11-30 22:49:41 +00:00
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#define pmd_young pmd_young
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2011-01-13 23:47:01 +00:00
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static inline int pmd_young(pmd_t pmd)
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{
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return pmd_flags(pmd) & _PAGE_ACCESSED;
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}
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2017-02-24 22:57:02 +00:00
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static inline int pud_dirty(pud_t pud)
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{
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return pud_flags(pud) & _PAGE_DIRTY;
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}
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static inline int pud_young(pud_t pud)
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{
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return pud_flags(pud) & _PAGE_ACCESSED;
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}
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2008-03-23 08:03:12 +00:00
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static inline int pte_write(pte_t pte)
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{
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2008-05-26 22:31:06 +00:00
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return pte_flags(pte) & _PAGE_RW;
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2008-03-23 08:03:12 +00:00
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}
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static inline int pte_huge(pte_t pte)
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{
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2008-05-26 22:31:06 +00:00
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return pte_flags(pte) & _PAGE_PSE;
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2008-01-30 12:32:56 +00:00
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}
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2008-03-23 08:03:12 +00:00
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static inline int pte_global(pte_t pte)
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{
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2008-05-26 22:31:06 +00:00
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return pte_flags(pte) & _PAGE_GLOBAL;
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2008-03-23 08:03:12 +00:00
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}
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static inline int pte_exec(pte_t pte)
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{
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2008-05-26 22:31:06 +00:00
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return !(pte_flags(pte) & _PAGE_NX);
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2008-03-23 08:03:12 +00:00
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}
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mm: introduce pte_special pte bit
s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory
model (which is more dynamic than most). Instead, they had proposed to
implement it with an additional path through vm_normal_page(), using a bit in
the pte to determine whether or not the page should be refcounted:
vm_normal_page()
{
...
if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
if (vma->vm_flags & VM_MIXEDMAP) {
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
#else
if (!pfn_valid(pfn))
return NULL;
#endif
goto out;
}
...
}
This is fine, however if we are allowed to use a bit in the pte to determine
refcountedness, we can use that to _completely_ replace all the vma based
schemes. So instead of adding more cases to the already complex vma-based
scheme, we can have a clearly seperate and simple pte-based scheme (and get
slightly better code generation in the process):
vm_normal_page()
{
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
return pte_page(pte);
#else
...
#endif
}
And finally, we may rather make this concept usable by any architecture rather
than making it s390 only, so implement a new type of pte state for this.
Unfortunately the old vma based code must stay, because some architectures may
not be able to spare pte bits. This makes vm_normal_page a little bit more
ugly than we would like, but the 2 cases are clearly seperate.
So introduce a pte_special pte state, and use it in mm/memory.c. It is
currently a noop for all architectures, so this doesn't actually result in any
compiled code changes to mm/memory.o.
BTW:
I haven't put vm_normal_page() into arch code as-per an earlier suggestion.
The reason is that, regardless of where vm_normal_page is actually
implemented, the *abstraction* is still exactly the same. Also, while it
depends on whether the architecture has pte_special or not, that is the
only two possible cases, and it really isn't an arch specific function --
the role of the arch code should be to provide primitive functions and
accessors with which to build the core code; pte_special does that. We do
not want architectures to know or care about vm_normal_page itself, and
we definitely don't want them being able to invent something new there
out of sight of mm/ code. If we made vm_normal_page an arch function, then
we have to make vm_insert_mixed (next patch) an arch function too. So I
don't think moving it to arch code fundamentally improves any abstractions,
while it does practically make the code more difficult to follow, for both
mm and arch developers, and easier to misuse.
[akpm@linux-foundation.org: build fix]
Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: Carsten Otte <cotte@de.ibm.com>
Cc: Jared Hulbert <jaredeh@gmail.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-28 09:13:00 +00:00
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static inline int pte_special(pte_t pte)
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{
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2015-02-12 22:58:38 +00:00
|
|
|
return pte_flags(pte) & _PAGE_SPECIAL;
|
mm: introduce pte_special pte bit
s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory
model (which is more dynamic than most). Instead, they had proposed to
implement it with an additional path through vm_normal_page(), using a bit in
the pte to determine whether or not the page should be refcounted:
vm_normal_page()
{
...
if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
if (vma->vm_flags & VM_MIXEDMAP) {
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
#else
if (!pfn_valid(pfn))
return NULL;
#endif
goto out;
}
...
}
This is fine, however if we are allowed to use a bit in the pte to determine
refcountedness, we can use that to _completely_ replace all the vma based
schemes. So instead of adding more cases to the already complex vma-based
scheme, we can have a clearly seperate and simple pte-based scheme (and get
slightly better code generation in the process):
vm_normal_page()
{
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
return pte_page(pte);
#else
...
#endif
}
And finally, we may rather make this concept usable by any architecture rather
than making it s390 only, so implement a new type of pte state for this.
Unfortunately the old vma based code must stay, because some architectures may
not be able to spare pte bits. This makes vm_normal_page a little bit more
ugly than we would like, but the 2 cases are clearly seperate.
So introduce a pte_special pte state, and use it in mm/memory.c. It is
currently a noop for all architectures, so this doesn't actually result in any
compiled code changes to mm/memory.o.
BTW:
I haven't put vm_normal_page() into arch code as-per an earlier suggestion.
The reason is that, regardless of where vm_normal_page is actually
implemented, the *abstraction* is still exactly the same. Also, while it
depends on whether the architecture has pte_special or not, that is the
only two possible cases, and it really isn't an arch specific function --
the role of the arch code should be to provide primitive functions and
accessors with which to build the core code; pte_special does that. We do
not want architectures to know or care about vm_normal_page itself, and
we definitely don't want them being able to invent something new there
out of sight of mm/ code. If we made vm_normal_page an arch function, then
we have to make vm_insert_mixed (next patch) an arch function too. So I
don't think moving it to arch code fundamentally improves any abstractions,
while it does practically make the code more difficult to follow, for both
mm and arch developers, and easier to misuse.
[akpm@linux-foundation.org: build fix]
Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: Carsten Otte <cotte@de.ibm.com>
Cc: Jared Hulbert <jaredeh@gmail.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-28 09:13:00 +00:00
|
|
|
}
|
|
|
|
|
2018-06-13 22:48:24 +00:00
|
|
|
/* Entries that were set to PROT_NONE are inverted */
|
|
|
|
|
|
|
|
static inline u64 protnone_mask(u64 val);
|
|
|
|
|
2008-09-09 15:42:45 +00:00
|
|
|
static inline unsigned long pte_pfn(pte_t pte)
|
|
|
|
{
|
2018-06-27 15:46:50 +00:00
|
|
|
phys_addr_t pfn = pte_val(pte);
|
2018-06-13 22:48:24 +00:00
|
|
|
pfn ^= protnone_mask(pfn);
|
|
|
|
return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT;
|
2008-09-09 15:42:45 +00:00
|
|
|
}
|
|
|
|
|
2009-06-27 06:35:15 +00:00
|
|
|
static inline unsigned long pmd_pfn(pmd_t pmd)
|
|
|
|
{
|
2018-06-27 15:46:50 +00:00
|
|
|
phys_addr_t pfn = pmd_val(pmd);
|
2018-06-13 22:48:24 +00:00
|
|
|
pfn ^= protnone_mask(pfn);
|
|
|
|
return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT;
|
2009-06-27 06:35:15 +00:00
|
|
|
}
|
|
|
|
|
2013-02-11 14:52:36 +00:00
|
|
|
static inline unsigned long pud_pfn(pud_t pud)
|
|
|
|
{
|
2018-06-27 15:46:50 +00:00
|
|
|
phys_addr_t pfn = pud_val(pud);
|
2018-06-13 22:48:24 +00:00
|
|
|
pfn ^= protnone_mask(pfn);
|
|
|
|
return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT;
|
2013-02-11 14:52:36 +00:00
|
|
|
}
|
|
|
|
|
2017-03-13 14:33:04 +00:00
|
|
|
static inline unsigned long p4d_pfn(p4d_t p4d)
|
|
|
|
{
|
|
|
|
return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT;
|
|
|
|
}
|
|
|
|
|
2017-07-17 21:10:06 +00:00
|
|
|
static inline unsigned long pgd_pfn(pgd_t pgd)
|
|
|
|
{
|
|
|
|
return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT;
|
|
|
|
}
|
|
|
|
|
2020-02-04 01:35:41 +00:00
|
|
|
#define p4d_leaf p4d_large
|
2017-03-13 14:33:04 +00:00
|
|
|
static inline int p4d_large(p4d_t p4d)
|
|
|
|
{
|
|
|
|
/* No 512 GiB pages yet */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-09-09 15:42:45 +00:00
|
|
|
#define pte_page(pte) pfn_to_page(pte_pfn(pte))
|
|
|
|
|
2020-02-04 01:35:41 +00:00
|
|
|
#define pmd_leaf pmd_large
|
2008-03-23 08:03:12 +00:00
|
|
|
static inline int pmd_large(pmd_t pte)
|
|
|
|
{
|
2012-10-08 23:33:27 +00:00
|
|
|
return pmd_flags(pte) & _PAGE_PSE;
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
2020-06-04 10:22:07 +00:00
|
|
|
/* NOTE: when predicate huge page, consider also pmd_devmap, or use pmd_large */
|
2011-01-13 23:47:01 +00:00
|
|
|
static inline int pmd_trans_huge(pmd_t pmd)
|
|
|
|
{
|
2016-01-16 00:56:52 +00:00
|
|
|
return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE;
|
2011-01-13 23:47:01 +00:00
|
|
|
}
|
2011-01-13 23:47:09 +00:00
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
|
|
|
|
static inline int pud_trans_huge(pud_t pud)
|
|
|
|
{
|
|
|
|
return (pud_val(pud) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
arch: fix has_transparent_hugepage()
I've just discovered that the useful-sounding has_transparent_hugepage()
is actually an architecture-dependent minefield: on some arches it only
builds if CONFIG_TRANSPARENT_HUGEPAGE=y, on others it's also there when
not, but on some of those (arm and arm64) it then gives the wrong
answer; and on mips alone it's marked __init, which would crash if
called later (but so far it has not been called later).
Straighten this out: make it available to all configs, with a sensible
default in asm-generic/pgtable.h, removing its definitions from those
arches (arc, arm, arm64, sparc, tile) which are served by the default,
adding #define has_transparent_hugepage has_transparent_hugepage to
those (mips, powerpc, s390, x86) which need to override the default at
runtime, and removing the __init from mips (but maybe that kind of code
should be avoided after init: set a static variable the first time it's
called).
Signed-off-by: Hugh Dickins <hughd@google.com>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Andres Lagar-Cavilla <andreslc@google.com>
Cc: Yang Shi <yang.shi@linaro.org>
Cc: Ning Qu <quning@gmail.com>
Cc: Mel Gorman <mgorman@techsingularity.net>
Cc: Konstantin Khlebnikov <koct9i@gmail.com>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Vineet Gupta <vgupta@synopsys.com> [arch/arc]
Acked-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> [arch/s390]
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-20 00:13:00 +00:00
|
|
|
#define has_transparent_hugepage has_transparent_hugepage
|
2011-01-13 23:47:09 +00:00
|
|
|
static inline int has_transparent_hugepage(void)
|
|
|
|
{
|
2016-03-29 15:42:03 +00:00
|
|
|
return boot_cpu_has(X86_FEATURE_PSE);
|
2011-01-13 23:47:09 +00:00
|
|
|
}
|
2016-01-16 00:56:52 +00:00
|
|
|
|
2019-07-16 23:30:47 +00:00
|
|
|
#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP
|
2016-01-16 00:56:52 +00:00
|
|
|
static inline int pmd_devmap(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return !!(pmd_val(pmd) & _PAGE_DEVMAP);
|
|
|
|
}
|
2017-02-24 22:57:02 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
|
|
|
|
static inline int pud_devmap(pud_t pud)
|
|
|
|
{
|
|
|
|
return !!(pud_val(pud) & _PAGE_DEVMAP);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline int pud_devmap(pud_t pud)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
2017-06-06 11:31:20 +00:00
|
|
|
|
|
|
|
static inline int pgd_devmap(pgd_t pgd)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2016-01-16 00:56:52 +00:00
|
|
|
#endif
|
2011-01-13 23:47:01 +00:00
|
|
|
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
|
|
|
|
2009-01-22 22:24:22 +00:00
|
|
|
static inline pte_t pte_set_flags(pte_t pte, pteval_t set)
|
|
|
|
{
|
|
|
|
pteval_t v = native_pte_val(pte);
|
|
|
|
|
|
|
|
return native_make_pte(v | set);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear)
|
|
|
|
{
|
|
|
|
pteval_t v = native_pte_val(pte);
|
|
|
|
|
|
|
|
return native_make_pte(v & ~clear);
|
|
|
|
}
|
|
|
|
|
2022-12-14 20:15:33 +00:00
|
|
|
static inline pte_t pte_wrprotect(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_clear_flags(pte, _PAGE_RW);
|
|
|
|
}
|
|
|
|
|
2020-04-07 03:05:33 +00:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
|
|
|
|
static inline int pte_uffd_wp(pte_t pte)
|
|
|
|
{
|
2022-11-14 00:04:47 +00:00
|
|
|
bool wp = pte_flags(pte) & _PAGE_UFFD_WP;
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_VM
|
|
|
|
/*
|
|
|
|
* Having write bit for wr-protect-marked present ptes is fatal,
|
|
|
|
* because it means the uffd-wp bit will be ignored and write will
|
|
|
|
* just go through.
|
|
|
|
*
|
|
|
|
* Use any chance of pgtable walking to verify this (e.g., when
|
|
|
|
* page swapped out or being migrated for all purposes). It means
|
|
|
|
* something is already wrong. Tell the admin even before the
|
|
|
|
* process crashes. We also nail it with wrong pgtable setup.
|
|
|
|
*/
|
|
|
|
WARN_ON_ONCE(wp && pte_write(pte));
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return wp;
|
2020-04-07 03:05:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkuffd_wp(pte_t pte)
|
|
|
|
{
|
2022-12-14 20:15:33 +00:00
|
|
|
return pte_wrprotect(pte_set_flags(pte, _PAGE_UFFD_WP));
|
2020-04-07 03:05:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_clear_uffd_wp(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_clear_flags(pte, _PAGE_UFFD_WP);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
|
|
|
|
|
2008-03-23 08:03:12 +00:00
|
|
|
static inline pte_t pte_mkclean(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_clear_flags(pte, _PAGE_DIRTY);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkold(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_clear_flags(pte, _PAGE_ACCESSED);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkexec(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_clear_flags(pte, _PAGE_NX);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkdirty(pte_t pte)
|
|
|
|
{
|
mm: soft-dirty bits for user memory changes tracking
The soft-dirty is a bit on a PTE which helps to track which pages a task
writes to. In order to do this tracking one should
1. Clear soft-dirty bits from PTEs ("echo 4 > /proc/PID/clear_refs)
2. Wait some time.
3. Read soft-dirty bits (55'th in /proc/PID/pagemap2 entries)
To do this tracking, the writable bit is cleared from PTEs when the
soft-dirty bit is. Thus, after this, when the task tries to modify a
page at some virtual address the #PF occurs and the kernel sets the
soft-dirty bit on the respective PTE.
Note, that although all the task's address space is marked as r/o after
the soft-dirty bits clear, the #PF-s that occur after that are processed
fast. This is so, since the pages are still mapped to physical memory,
and thus all the kernel does is finds this fact out and puts back
writable, dirty and soft-dirty bits on the PTE.
Another thing to note, is that when mremap moves PTEs they are marked
with soft-dirty as well, since from the user perspective mremap modifies
the virtual memory at mremap's new address.
Signed-off-by: Pavel Emelyanov <xemul@parallels.com>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Cc: Glauber Costa <glommer@parallels.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: KOSAKI Motohiro <kosaki.motohiro@gmail.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-03 22:01:20 +00:00
|
|
|
return pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkyoung(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_set_flags(pte, _PAGE_ACCESSED);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkwrite(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_set_flags(pte, _PAGE_RW);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkhuge(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_set_flags(pte, _PAGE_PSE);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_clrhuge(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_clear_flags(pte, _PAGE_PSE);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_mkglobal(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_set_flags(pte, _PAGE_GLOBAL);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_clrglobal(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_clear_flags(pte, _PAGE_GLOBAL);
|
2008-03-23 08:03:12 +00:00
|
|
|
}
|
2008-01-30 12:32:56 +00:00
|
|
|
|
mm: introduce pte_special pte bit
s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory
model (which is more dynamic than most). Instead, they had proposed to
implement it with an additional path through vm_normal_page(), using a bit in
the pte to determine whether or not the page should be refcounted:
vm_normal_page()
{
...
if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
if (vma->vm_flags & VM_MIXEDMAP) {
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
#else
if (!pfn_valid(pfn))
return NULL;
#endif
goto out;
}
...
}
This is fine, however if we are allowed to use a bit in the pte to determine
refcountedness, we can use that to _completely_ replace all the vma based
schemes. So instead of adding more cases to the already complex vma-based
scheme, we can have a clearly seperate and simple pte-based scheme (and get
slightly better code generation in the process):
vm_normal_page()
{
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
return pte_page(pte);
#else
...
#endif
}
And finally, we may rather make this concept usable by any architecture rather
than making it s390 only, so implement a new type of pte state for this.
Unfortunately the old vma based code must stay, because some architectures may
not be able to spare pte bits. This makes vm_normal_page a little bit more
ugly than we would like, but the 2 cases are clearly seperate.
So introduce a pte_special pte state, and use it in mm/memory.c. It is
currently a noop for all architectures, so this doesn't actually result in any
compiled code changes to mm/memory.o.
BTW:
I haven't put vm_normal_page() into arch code as-per an earlier suggestion.
The reason is that, regardless of where vm_normal_page is actually
implemented, the *abstraction* is still exactly the same. Also, while it
depends on whether the architecture has pte_special or not, that is the
only two possible cases, and it really isn't an arch specific function --
the role of the arch code should be to provide primitive functions and
accessors with which to build the core code; pte_special does that. We do
not want architectures to know or care about vm_normal_page itself, and
we definitely don't want them being able to invent something new there
out of sight of mm/ code. If we made vm_normal_page an arch function, then
we have to make vm_insert_mixed (next patch) an arch function too. So I
don't think moving it to arch code fundamentally improves any abstractions,
while it does practically make the code more difficult to follow, for both
mm and arch developers, and easier to misuse.
[akpm@linux-foundation.org: build fix]
Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: Carsten Otte <cotte@de.ibm.com>
Cc: Jared Hulbert <jaredeh@gmail.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-28 09:13:00 +00:00
|
|
|
static inline pte_t pte_mkspecial(pte_t pte)
|
|
|
|
{
|
2009-01-22 22:24:22 +00:00
|
|
|
return pte_set_flags(pte, _PAGE_SPECIAL);
|
mm: introduce pte_special pte bit
s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory
model (which is more dynamic than most). Instead, they had proposed to
implement it with an additional path through vm_normal_page(), using a bit in
the pte to determine whether or not the page should be refcounted:
vm_normal_page()
{
...
if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
if (vma->vm_flags & VM_MIXEDMAP) {
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
#else
if (!pfn_valid(pfn))
return NULL;
#endif
goto out;
}
...
}
This is fine, however if we are allowed to use a bit in the pte to determine
refcountedness, we can use that to _completely_ replace all the vma based
schemes. So instead of adding more cases to the already complex vma-based
scheme, we can have a clearly seperate and simple pte-based scheme (and get
slightly better code generation in the process):
vm_normal_page()
{
#ifdef s390
if (!mixedmap_refcount_pte(pte))
return NULL;
return pte_page(pte);
#else
...
#endif
}
And finally, we may rather make this concept usable by any architecture rather
than making it s390 only, so implement a new type of pte state for this.
Unfortunately the old vma based code must stay, because some architectures may
not be able to spare pte bits. This makes vm_normal_page a little bit more
ugly than we would like, but the 2 cases are clearly seperate.
So introduce a pte_special pte state, and use it in mm/memory.c. It is
currently a noop for all architectures, so this doesn't actually result in any
compiled code changes to mm/memory.o.
BTW:
I haven't put vm_normal_page() into arch code as-per an earlier suggestion.
The reason is that, regardless of where vm_normal_page is actually
implemented, the *abstraction* is still exactly the same. Also, while it
depends on whether the architecture has pte_special or not, that is the
only two possible cases, and it really isn't an arch specific function --
the role of the arch code should be to provide primitive functions and
accessors with which to build the core code; pte_special does that. We do
not want architectures to know or care about vm_normal_page itself, and
we definitely don't want them being able to invent something new there
out of sight of mm/ code. If we made vm_normal_page an arch function, then
we have to make vm_insert_mixed (next patch) an arch function too. So I
don't think moving it to arch code fundamentally improves any abstractions,
while it does practically make the code more difficult to follow, for both
mm and arch developers, and easier to misuse.
[akpm@linux-foundation.org: build fix]
Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: Carsten Otte <cotte@de.ibm.com>
Cc: Jared Hulbert <jaredeh@gmail.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-28 09:13:00 +00:00
|
|
|
}
|
|
|
|
|
2016-01-16 00:56:40 +00:00
|
|
|
static inline pte_t pte_mkdevmap(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP);
|
|
|
|
}
|
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set)
|
|
|
|
{
|
|
|
|
pmdval_t v = native_pmd_val(pmd);
|
|
|
|
|
2018-02-19 14:48:11 +00:00
|
|
|
return native_make_pmd(v | set);
|
2011-01-13 23:47:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear)
|
|
|
|
{
|
|
|
|
pmdval_t v = native_pmd_val(pmd);
|
|
|
|
|
2018-02-19 14:48:11 +00:00
|
|
|
return native_make_pmd(v & ~clear);
|
2011-01-13 23:47:01 +00:00
|
|
|
}
|
|
|
|
|
2022-12-14 20:15:33 +00:00
|
|
|
static inline pmd_t pmd_wrprotect(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_clear_flags(pmd, _PAGE_RW);
|
|
|
|
}
|
|
|
|
|
2020-04-07 03:05:33 +00:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
|
|
|
|
static inline int pmd_uffd_wp(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_flags(pmd) & _PAGE_UFFD_WP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
|
|
|
|
{
|
2022-12-14 20:15:33 +00:00
|
|
|
return pmd_wrprotect(pmd_set_flags(pmd, _PAGE_UFFD_WP));
|
2020-04-07 03:05:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_clear_flags(pmd, _PAGE_UFFD_WP);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
|
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
static inline pmd_t pmd_mkold(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_clear_flags(pmd, _PAGE_ACCESSED);
|
|
|
|
}
|
|
|
|
|
2016-01-16 00:55:20 +00:00
|
|
|
static inline pmd_t pmd_mkclean(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_clear_flags(pmd, _PAGE_DIRTY);
|
|
|
|
}
|
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
static inline pmd_t pmd_mkdirty(pmd_t pmd)
|
|
|
|
{
|
mm: soft-dirty bits for user memory changes tracking
The soft-dirty is a bit on a PTE which helps to track which pages a task
writes to. In order to do this tracking one should
1. Clear soft-dirty bits from PTEs ("echo 4 > /proc/PID/clear_refs)
2. Wait some time.
3. Read soft-dirty bits (55'th in /proc/PID/pagemap2 entries)
To do this tracking, the writable bit is cleared from PTEs when the
soft-dirty bit is. Thus, after this, when the task tries to modify a
page at some virtual address the #PF occurs and the kernel sets the
soft-dirty bit on the respective PTE.
Note, that although all the task's address space is marked as r/o after
the soft-dirty bits clear, the #PF-s that occur after that are processed
fast. This is so, since the pages are still mapped to physical memory,
and thus all the kernel does is finds this fact out and puts back
writable, dirty and soft-dirty bits on the PTE.
Another thing to note, is that when mremap moves PTEs they are marked
with soft-dirty as well, since from the user perspective mremap modifies
the virtual memory at mremap's new address.
Signed-off-by: Pavel Emelyanov <xemul@parallels.com>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Cc: Glauber Costa <glommer@parallels.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: KOSAKI Motohiro <kosaki.motohiro@gmail.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-03 22:01:20 +00:00
|
|
|
return pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
|
2011-01-13 23:47:01 +00:00
|
|
|
}
|
|
|
|
|
2016-01-16 00:56:43 +00:00
|
|
|
static inline pmd_t pmd_mkdevmap(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_set_flags(pmd, _PAGE_DEVMAP);
|
|
|
|
}
|
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
static inline pmd_t pmd_mkhuge(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_set_flags(pmd, _PAGE_PSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_mkyoung(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_set_flags(pmd, _PAGE_ACCESSED);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_mkwrite(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_set_flags(pmd, _PAGE_RW);
|
|
|
|
}
|
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
static inline pud_t pud_set_flags(pud_t pud, pudval_t set)
|
|
|
|
{
|
|
|
|
pudval_t v = native_pud_val(pud);
|
|
|
|
|
2018-02-19 14:48:11 +00:00
|
|
|
return native_make_pud(v | set);
|
2017-02-24 22:57:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear)
|
|
|
|
{
|
|
|
|
pudval_t v = native_pud_val(pud);
|
|
|
|
|
2018-02-19 14:48:11 +00:00
|
|
|
return native_make_pud(v & ~clear);
|
2017-02-24 22:57:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_mkold(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_clear_flags(pud, _PAGE_ACCESSED);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_mkclean(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_clear_flags(pud, _PAGE_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_wrprotect(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_clear_flags(pud, _PAGE_RW);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_mkdirty(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_mkdevmap(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_set_flags(pud, _PAGE_DEVMAP);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_mkhuge(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_set_flags(pud, _PAGE_PSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_mkyoung(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_set_flags(pud, _PAGE_ACCESSED);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pud_t pud_mkwrite(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_set_flags(pud, _PAGE_RW);
|
|
|
|
}
|
|
|
|
|
2014-06-04 23:08:16 +00:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
|
mm: soft-dirty bits for user memory changes tracking
The soft-dirty is a bit on a PTE which helps to track which pages a task
writes to. In order to do this tracking one should
1. Clear soft-dirty bits from PTEs ("echo 4 > /proc/PID/clear_refs)
2. Wait some time.
3. Read soft-dirty bits (55'th in /proc/PID/pagemap2 entries)
To do this tracking, the writable bit is cleared from PTEs when the
soft-dirty bit is. Thus, after this, when the task tries to modify a
page at some virtual address the #PF occurs and the kernel sets the
soft-dirty bit on the respective PTE.
Note, that although all the task's address space is marked as r/o after
the soft-dirty bits clear, the #PF-s that occur after that are processed
fast. This is so, since the pages are still mapped to physical memory,
and thus all the kernel does is finds this fact out and puts back
writable, dirty and soft-dirty bits on the PTE.
Another thing to note, is that when mremap moves PTEs they are marked
with soft-dirty as well, since from the user perspective mremap modifies
the virtual memory at mremap's new address.
Signed-off-by: Pavel Emelyanov <xemul@parallels.com>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Cc: Glauber Costa <glommer@parallels.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: KOSAKI Motohiro <kosaki.motohiro@gmail.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-03 22:01:20 +00:00
|
|
|
static inline int pte_soft_dirty(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_flags(pte) & _PAGE_SOFT_DIRTY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pmd_soft_dirty(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_flags(pmd) & _PAGE_SOFT_DIRTY;
|
|
|
|
}
|
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
static inline int pud_soft_dirty(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_flags(pud) & _PAGE_SOFT_DIRTY;
|
|
|
|
}
|
|
|
|
|
mm: soft-dirty bits for user memory changes tracking
The soft-dirty is a bit on a PTE which helps to track which pages a task
writes to. In order to do this tracking one should
1. Clear soft-dirty bits from PTEs ("echo 4 > /proc/PID/clear_refs)
2. Wait some time.
3. Read soft-dirty bits (55'th in /proc/PID/pagemap2 entries)
To do this tracking, the writable bit is cleared from PTEs when the
soft-dirty bit is. Thus, after this, when the task tries to modify a
page at some virtual address the #PF occurs and the kernel sets the
soft-dirty bit on the respective PTE.
Note, that although all the task's address space is marked as r/o after
the soft-dirty bits clear, the #PF-s that occur after that are processed
fast. This is so, since the pages are still mapped to physical memory,
and thus all the kernel does is finds this fact out and puts back
writable, dirty and soft-dirty bits on the PTE.
Another thing to note, is that when mremap moves PTEs they are marked
with soft-dirty as well, since from the user perspective mremap modifies
the virtual memory at mremap's new address.
Signed-off-by: Pavel Emelyanov <xemul@parallels.com>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Cc: Glauber Costa <glommer@parallels.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: KOSAKI Motohiro <kosaki.motohiro@gmail.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-03 22:01:20 +00:00
|
|
|
static inline pte_t pte_mksoft_dirty(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_set_flags(pte, _PAGE_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
static inline pud_t pud_mksoft_dirty(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_set_flags(pud, _PAGE_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
2015-04-22 12:20:47 +00:00
|
|
|
static inline pte_t pte_clear_soft_dirty(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_clear_flags(pte, _PAGE_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
static inline pud_t pud_clear_soft_dirty(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_clear_flags(pud, _PAGE_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
2014-06-04 23:08:16 +00:00
|
|
|
#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
|
|
|
|
|
2009-02-05 02:33:38 +00:00
|
|
|
/*
|
|
|
|
* Mask out unsupported bits in a present pgprot. Non-present pgprots
|
|
|
|
* can use those bits for other purposes, so leave them be.
|
|
|
|
*/
|
|
|
|
static inline pgprotval_t massage_pgprot(pgprot_t pgprot)
|
|
|
|
{
|
|
|
|
pgprotval_t protval = pgprot_val(pgprot);
|
|
|
|
|
|
|
|
if (protval & _PAGE_PRESENT)
|
|
|
|
protval &= __supported_pte_mask;
|
|
|
|
|
|
|
|
return protval;
|
|
|
|
}
|
|
|
|
|
2018-04-06 20:55:09 +00:00
|
|
|
static inline pgprotval_t check_pgprot(pgprot_t pgprot)
|
|
|
|
{
|
|
|
|
pgprotval_t massaged_val = massage_pgprot(pgprot);
|
|
|
|
|
|
|
|
/* mmdebug.h can not be included here because of dependencies */
|
|
|
|
#ifdef CONFIG_DEBUG_VM
|
|
|
|
WARN_ONCE(pgprot_val(pgprot) != massaged_val,
|
|
|
|
"attempted to set unsupported pgprot: %016llx "
|
|
|
|
"bits: %016llx supported: %016llx\n",
|
|
|
|
(u64)pgprot_val(pgprot),
|
|
|
|
(u64)pgprot_val(pgprot) ^ massaged_val,
|
|
|
|
(u64)__supported_pte_mask);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return massaged_val;
|
|
|
|
}
|
|
|
|
|
2008-01-30 12:32:57 +00:00
|
|
|
static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
|
|
|
|
{
|
2018-06-27 15:46:50 +00:00
|
|
|
phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT;
|
2018-06-13 22:48:24 +00:00
|
|
|
pfn ^= protnone_mask(pgprot_val(pgprot));
|
|
|
|
pfn &= PTE_PFN_MASK;
|
|
|
|
return __pte(pfn | check_pgprot(pgprot));
|
2008-01-30 12:32:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
|
|
|
|
{
|
2018-06-27 15:46:50 +00:00
|
|
|
phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT;
|
2018-06-13 22:48:24 +00:00
|
|
|
pfn ^= protnone_mask(pgprot_val(pgprot));
|
|
|
|
pfn &= PHYSICAL_PMD_PAGE_MASK;
|
|
|
|
return __pmd(pfn | check_pgprot(pgprot));
|
2008-01-30 12:32:57 +00:00
|
|
|
}
|
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot)
|
|
|
|
{
|
2018-06-27 15:46:50 +00:00
|
|
|
phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT;
|
2018-06-13 22:48:24 +00:00
|
|
|
pfn ^= protnone_mask(pgprot_val(pgprot));
|
|
|
|
pfn &= PHYSICAL_PUD_PAGE_MASK;
|
|
|
|
return __pud(pfn | check_pgprot(pgprot));
|
2017-02-24 22:57:02 +00:00
|
|
|
}
|
|
|
|
|
2020-06-03 23:03:45 +00:00
|
|
|
static inline pmd_t pmd_mkinvalid(pmd_t pmd)
|
2018-08-07 22:09:37 +00:00
|
|
|
{
|
|
|
|
return pfn_pmd(pmd_pfn(pmd),
|
|
|
|
__pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE)));
|
|
|
|
}
|
|
|
|
|
2018-06-13 22:48:24 +00:00
|
|
|
static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask);
|
|
|
|
|
2008-01-30 12:32:57 +00:00
|
|
|
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|
|
|
{
|
2018-06-13 22:48:24 +00:00
|
|
|
pteval_t val = pte_val(pte), oldval = val;
|
2008-01-30 12:32:57 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Chop off the NX bit (if present), and add the NX portion of
|
|
|
|
* the newprot (if present):
|
|
|
|
*/
|
2008-05-14 23:05:51 +00:00
|
|
|
val &= _PAGE_CHG_MASK;
|
2018-04-06 20:55:09 +00:00
|
|
|
val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK;
|
2018-06-13 22:48:24 +00:00
|
|
|
val = flip_protnone_guard(oldval, val, PTE_PFN_MASK);
|
2008-01-30 12:32:57 +00:00
|
|
|
return __pte(val);
|
|
|
|
}
|
|
|
|
|
2011-01-13 23:47:02 +00:00
|
|
|
static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
|
|
|
|
{
|
2018-06-13 22:48:24 +00:00
|
|
|
pmdval_t val = pmd_val(pmd), oldval = val;
|
2011-01-13 23:47:02 +00:00
|
|
|
|
|
|
|
val &= _HPAGE_CHG_MASK;
|
2018-04-06 20:55:09 +00:00
|
|
|
val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK;
|
2018-06-13 22:48:24 +00:00
|
|
|
val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK);
|
2011-01-13 23:47:02 +00:00
|
|
|
return __pmd(val);
|
|
|
|
}
|
|
|
|
|
2020-03-04 11:45:26 +00:00
|
|
|
/*
|
|
|
|
* mprotect needs to preserve PAT and encryption bits when updating
|
|
|
|
* vm_page_prot
|
|
|
|
*/
|
2008-05-14 23:05:51 +00:00
|
|
|
#define pgprot_modify pgprot_modify
|
|
|
|
static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
|
|
|
|
{
|
|
|
|
pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK;
|
2020-03-04 11:45:26 +00:00
|
|
|
pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK;
|
2008-05-14 23:05:51 +00:00
|
|
|
return __pgprot(preservebits | addbits);
|
|
|
|
}
|
|
|
|
|
2015-09-17 18:24:18 +00:00
|
|
|
#define pte_pgprot(x) __pgprot(pte_flags(x))
|
|
|
|
#define pmd_pgprot(x) __pgprot(pmd_flags(x))
|
|
|
|
#define pud_pgprot(x) __pgprot(pud_flags(x))
|
2017-03-17 18:55:15 +00:00
|
|
|
#define p4d_pgprot(x) __pgprot(p4d_flags(x))
|
2008-01-30 12:33:51 +00:00
|
|
|
|
2009-02-05 02:33:38 +00:00
|
|
|
#define canon_pgprot(p) __pgprot(massage_pgprot(p))
|
2008-01-30 12:33:53 +00:00
|
|
|
|
x86, pat: Allow ISA memory range uncacheable mapping requests
Max Vozeler reported:
> Bug 13877 - bogl-term broken with CONFIG_X86_PAT=y, works with =n
>
> strace of bogl-term:
> 814 mmap2(NULL, 65536, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0)
> = -1 EAGAIN (Resource temporarily unavailable)
> 814 write(2, "bogl: mmaping /dev/fb0: Resource temporarily unavailable\n",
> 57) = 57
PAT code maps the ISA memory range as WB in the PAT attribute, so that
fixed range MTRR registers define the actual memory type (UC/WC/WT etc).
But the upper level is_new_memtype_allowed() API checks are failing,
as the request here is for UC and the return tracked type is WB (Tracked type is
WB as MTRR type for this legacy range potentially will be different for each
4k page).
Fix is_new_memtype_allowed() by always succeeding the ISA address range
checks, as the null PAT (WB) and def MTRR fixed range register settings
satisfy the memory type needs of the applications that map the ISA address
range.
Reported-and-Tested-by: Max Vozeler <xam@debian.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-08-17 20:23:50 +00:00
|
|
|
static inline int is_new_memtype_allowed(u64 paddr, unsigned long size,
|
2014-11-03 13:01:53 +00:00
|
|
|
enum page_cache_mode pcm,
|
|
|
|
enum page_cache_mode new_pcm)
|
2009-01-10 00:13:10 +00:00
|
|
|
{
|
x86, pat: Allow ISA memory range uncacheable mapping requests
Max Vozeler reported:
> Bug 13877 - bogl-term broken with CONFIG_X86_PAT=y, works with =n
>
> strace of bogl-term:
> 814 mmap2(NULL, 65536, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0)
> = -1 EAGAIN (Resource temporarily unavailable)
> 814 write(2, "bogl: mmaping /dev/fb0: Resource temporarily unavailable\n",
> 57) = 57
PAT code maps the ISA memory range as WB in the PAT attribute, so that
fixed range MTRR registers define the actual memory type (UC/WC/WT etc).
But the upper level is_new_memtype_allowed() API checks are failing,
as the request here is for UC and the return tracked type is WB (Tracked type is
WB as MTRR type for this legacy range potentially will be different for each
4k page).
Fix is_new_memtype_allowed() by always succeeding the ISA address range
checks, as the null PAT (WB) and def MTRR fixed range register settings
satisfy the memory type needs of the applications that map the ISA address
range.
Reported-and-Tested-by: Max Vozeler <xam@debian.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-08-17 20:23:50 +00:00
|
|
|
/*
|
2009-11-23 23:12:07 +00:00
|
|
|
* PAT type is always WB for untracked ranges, so no need to check.
|
x86, pat: Allow ISA memory range uncacheable mapping requests
Max Vozeler reported:
> Bug 13877 - bogl-term broken with CONFIG_X86_PAT=y, works with =n
>
> strace of bogl-term:
> 814 mmap2(NULL, 65536, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0)
> = -1 EAGAIN (Resource temporarily unavailable)
> 814 write(2, "bogl: mmaping /dev/fb0: Resource temporarily unavailable\n",
> 57) = 57
PAT code maps the ISA memory range as WB in the PAT attribute, so that
fixed range MTRR registers define the actual memory type (UC/WC/WT etc).
But the upper level is_new_memtype_allowed() API checks are failing,
as the request here is for UC and the return tracked type is WB (Tracked type is
WB as MTRR type for this legacy range potentially will be different for each
4k page).
Fix is_new_memtype_allowed() by always succeeding the ISA address range
checks, as the null PAT (WB) and def MTRR fixed range register settings
satisfy the memory type needs of the applications that map the ISA address
range.
Reported-and-Tested-by: Max Vozeler <xam@debian.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-08-17 20:23:50 +00:00
|
|
|
*/
|
2009-11-23 22:49:20 +00:00
|
|
|
if (x86_platform.is_untracked_pat_range(paddr, paddr + size))
|
x86, pat: Allow ISA memory range uncacheable mapping requests
Max Vozeler reported:
> Bug 13877 - bogl-term broken with CONFIG_X86_PAT=y, works with =n
>
> strace of bogl-term:
> 814 mmap2(NULL, 65536, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0)
> = -1 EAGAIN (Resource temporarily unavailable)
> 814 write(2, "bogl: mmaping /dev/fb0: Resource temporarily unavailable\n",
> 57) = 57
PAT code maps the ISA memory range as WB in the PAT attribute, so that
fixed range MTRR registers define the actual memory type (UC/WC/WT etc).
But the upper level is_new_memtype_allowed() API checks are failing,
as the request here is for UC and the return tracked type is WB (Tracked type is
WB as MTRR type for this legacy range potentially will be different for each
4k page).
Fix is_new_memtype_allowed() by always succeeding the ISA address range
checks, as the null PAT (WB) and def MTRR fixed range register settings
satisfy the memory type needs of the applications that map the ISA address
range.
Reported-and-Tested-by: Max Vozeler <xam@debian.org>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-08-17 20:23:50 +00:00
|
|
|
return 1;
|
|
|
|
|
2009-01-10 00:13:10 +00:00
|
|
|
/*
|
|
|
|
* Certain new memtypes are not allowed with certain
|
|
|
|
* requested memtype:
|
|
|
|
* - request is uncached, return cannot be write-back
|
|
|
|
* - request is write-combine, return cannot be write-back
|
2015-06-04 16:55:14 +00:00
|
|
|
* - request is write-through, return cannot be write-back
|
|
|
|
* - request is write-through, return cannot be write-combine
|
2009-01-10 00:13:10 +00:00
|
|
|
*/
|
2014-11-03 13:01:53 +00:00
|
|
|
if ((pcm == _PAGE_CACHE_MODE_UC_MINUS &&
|
|
|
|
new_pcm == _PAGE_CACHE_MODE_WB) ||
|
|
|
|
(pcm == _PAGE_CACHE_MODE_WC &&
|
2015-06-04 16:55:14 +00:00
|
|
|
new_pcm == _PAGE_CACHE_MODE_WB) ||
|
|
|
|
(pcm == _PAGE_CACHE_MODE_WT &&
|
|
|
|
new_pcm == _PAGE_CACHE_MODE_WB) ||
|
|
|
|
(pcm == _PAGE_CACHE_MODE_WT &&
|
|
|
|
new_pcm == _PAGE_CACHE_MODE_WC)) {
|
2009-01-10 00:13:10 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2009-02-24 02:57:21 +00:00
|
|
|
pmd_t *populate_extra_pmd(unsigned long vaddr);
|
|
|
|
pte_t *populate_extra_pte(unsigned long vaddr);
|
2018-07-18 09:40:56 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
|
|
pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Take a PGD location (pgdp) and a pgd value that needs to be set there.
|
|
|
|
* Populates the user and returns the resulting PGD that must be set in
|
|
|
|
* the kernel copy of the page tables.
|
|
|
|
*/
|
|
|
|
static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd)
|
|
|
|
{
|
|
|
|
if (!static_cpu_has(X86_FEATURE_PTI))
|
|
|
|
return pgd;
|
|
|
|
return __pti_set_user_pgtbl(pgdp, pgd);
|
|
|
|
}
|
|
|
|
#else /* CONFIG_PAGE_TABLE_ISOLATION */
|
|
|
|
static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd)
|
|
|
|
{
|
|
|
|
return pgd;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PAGE_TABLE_ISOLATION */
|
|
|
|
|
2008-01-30 12:32:56 +00:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
2018-07-18 09:40:56 +00:00
|
|
|
|
2007-10-11 09:20:03 +00:00
|
|
|
#ifdef CONFIG_X86_32
|
2012-10-02 17:01:25 +00:00
|
|
|
# include <asm/pgtable_32.h>
|
2007-10-11 09:20:03 +00:00
|
|
|
#else
|
2012-10-02 17:01:25 +00:00
|
|
|
# include <asm/pgtable_64.h>
|
2007-10-11 09:20:03 +00:00
|
|
|
#endif
|
2008-01-30 12:32:55 +00:00
|
|
|
|
2009-02-05 19:30:54 +00:00
|
|
|
#ifndef __ASSEMBLY__
|
2009-02-05 19:30:55 +00:00
|
|
|
#include <linux/mm_types.h>
|
2013-09-11 21:22:47 +00:00
|
|
|
#include <linux/mmdebug.h>
|
2013-01-22 21:24:31 +00:00
|
|
|
#include <linux/log2.h>
|
2017-03-21 07:17:25 +00:00
|
|
|
#include <asm/fixmap.h>
|
2009-02-05 19:30:54 +00:00
|
|
|
|
2009-02-05 19:30:43 +00:00
|
|
|
static inline int pte_none(pte_t pte)
|
|
|
|
{
|
2016-07-08 00:19:12 +00:00
|
|
|
return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK));
|
2009-02-05 19:30:43 +00:00
|
|
|
}
|
|
|
|
|
2009-02-05 19:30:44 +00:00
|
|
|
#define __HAVE_ARCH_PTE_SAME
|
|
|
|
static inline int pte_same(pte_t a, pte_t b)
|
|
|
|
{
|
|
|
|
return a.pte == b.pte;
|
|
|
|
}
|
|
|
|
|
2009-02-05 19:30:45 +00:00
|
|
|
static inline int pte_present(pte_t a)
|
2014-06-04 23:06:30 +00:00
|
|
|
{
|
|
|
|
return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE);
|
|
|
|
}
|
|
|
|
|
2019-07-16 23:30:47 +00:00
|
|
|
#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP
|
2016-01-16 00:56:55 +00:00
|
|
|
static inline int pte_devmap(pte_t a)
|
|
|
|
{
|
|
|
|
return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-10-09 13:31:12 +00:00
|
|
|
#define pte_accessible pte_accessible
|
mm: fix TLB flush race between migration, and change_protection_range
There are a few subtle races, between change_protection_range (used by
mprotect and change_prot_numa) on one side, and NUMA page migration and
compaction on the other side.
The basic race is that there is a time window between when the PTE gets
made non-present (PROT_NONE or NUMA), and the TLB is flushed.
During that time, a CPU may continue writing to the page.
This is fine most of the time, however compaction or the NUMA migration
code may come in, and migrate the page away.
When that happens, the CPU may continue writing, through the cached
translation, to what is no longer the current memory location of the
process.
This only affects x86, which has a somewhat optimistic pte_accessible.
All other architectures appear to be safe, and will either always flush,
or flush whenever there is a valid mapping, even with no permissions
(SPARC).
The basic race looks like this:
CPU A CPU B CPU C
load TLB entry
make entry PTE/PMD_NUMA
fault on entry
read/write old page
start migrating page
change PTE/PMD to new page
read/write old page [*]
flush TLB
reload TLB from new entry
read/write new page
lose data
[*] the old page may belong to a new user at this point!
The obvious fix is to flush remote TLB entries, by making sure that
pte_accessible aware of the fact that PROT_NONE and PROT_NUMA memory may
still be accessible if there is a TLB flush pending for the mm.
This should fix both NUMA migration and compaction.
[mgorman@suse.de: fix build]
Signed-off-by: Rik van Riel <riel@redhat.com>
Signed-off-by: Mel Gorman <mgorman@suse.de>
Cc: Alex Thorlton <athorlton@sgi.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-12-19 01:08:44 +00:00
|
|
|
static inline bool pte_accessible(struct mm_struct *mm, pte_t a)
|
2012-10-09 13:31:12 +00:00
|
|
|
{
|
mm: fix TLB flush race between migration, and change_protection_range
There are a few subtle races, between change_protection_range (used by
mprotect and change_prot_numa) on one side, and NUMA page migration and
compaction on the other side.
The basic race is that there is a time window between when the PTE gets
made non-present (PROT_NONE or NUMA), and the TLB is flushed.
During that time, a CPU may continue writing to the page.
This is fine most of the time, however compaction or the NUMA migration
code may come in, and migrate the page away.
When that happens, the CPU may continue writing, through the cached
translation, to what is no longer the current memory location of the
process.
This only affects x86, which has a somewhat optimistic pte_accessible.
All other architectures appear to be safe, and will either always flush,
or flush whenever there is a valid mapping, even with no permissions
(SPARC).
The basic race looks like this:
CPU A CPU B CPU C
load TLB entry
make entry PTE/PMD_NUMA
fault on entry
read/write old page
start migrating page
change PTE/PMD to new page
read/write old page [*]
flush TLB
reload TLB from new entry
read/write new page
lose data
[*] the old page may belong to a new user at this point!
The obvious fix is to flush remote TLB entries, by making sure that
pte_accessible aware of the fact that PROT_NONE and PROT_NUMA memory may
still be accessible if there is a TLB flush pending for the mm.
This should fix both NUMA migration and compaction.
[mgorman@suse.de: fix build]
Signed-off-by: Rik van Riel <riel@redhat.com>
Signed-off-by: Mel Gorman <mgorman@suse.de>
Cc: Alex Thorlton <athorlton@sgi.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-12-19 01:08:44 +00:00
|
|
|
if (pte_flags(a) & _PAGE_PRESENT)
|
|
|
|
return true;
|
|
|
|
|
2015-02-12 22:58:32 +00:00
|
|
|
if ((pte_flags(a) & _PAGE_PROTNONE) &&
|
2022-01-14 22:06:10 +00:00
|
|
|
atomic_read(&mm->tlb_flush_pending))
|
mm: fix TLB flush race between migration, and change_protection_range
There are a few subtle races, between change_protection_range (used by
mprotect and change_prot_numa) on one side, and NUMA page migration and
compaction on the other side.
The basic race is that there is a time window between when the PTE gets
made non-present (PROT_NONE or NUMA), and the TLB is flushed.
During that time, a CPU may continue writing to the page.
This is fine most of the time, however compaction or the NUMA migration
code may come in, and migrate the page away.
When that happens, the CPU may continue writing, through the cached
translation, to what is no longer the current memory location of the
process.
This only affects x86, which has a somewhat optimistic pte_accessible.
All other architectures appear to be safe, and will either always flush,
or flush whenever there is a valid mapping, even with no permissions
(SPARC).
The basic race looks like this:
CPU A CPU B CPU C
load TLB entry
make entry PTE/PMD_NUMA
fault on entry
read/write old page
start migrating page
change PTE/PMD to new page
read/write old page [*]
flush TLB
reload TLB from new entry
read/write new page
lose data
[*] the old page may belong to a new user at this point!
The obvious fix is to flush remote TLB entries, by making sure that
pte_accessible aware of the fact that PROT_NONE and PROT_NUMA memory may
still be accessible if there is a TLB flush pending for the mm.
This should fix both NUMA migration and compaction.
[mgorman@suse.de: fix build]
Signed-off-by: Rik van Riel <riel@redhat.com>
Signed-off-by: Mel Gorman <mgorman@suse.de>
Cc: Alex Thorlton <athorlton@sgi.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-12-19 01:08:44 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
2012-10-09 13:31:12 +00:00
|
|
|
}
|
|
|
|
|
2009-02-05 19:30:50 +00:00
|
|
|
static inline int pmd_present(pmd_t pmd)
|
|
|
|
{
|
2012-10-08 23:33:27 +00:00
|
|
|
/*
|
|
|
|
* Checking for _PAGE_PSE is needed too because
|
|
|
|
* split_huge_page will temporarily clear the present bit (but
|
|
|
|
* the _PAGE_PSE flag will remain set at all times while the
|
|
|
|
* _PAGE_PRESENT bit is clear).
|
|
|
|
*/
|
2015-02-12 22:58:32 +00:00
|
|
|
return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE);
|
2009-02-05 19:30:50 +00:00
|
|
|
}
|
|
|
|
|
2015-02-12 22:58:19 +00:00
|
|
|
#ifdef CONFIG_NUMA_BALANCING
|
|
|
|
/*
|
|
|
|
* These work without NUMA balancing but the kernel does not care. See the
|
2020-06-09 04:32:38 +00:00
|
|
|
* comment in include/linux/pgtable.h
|
2015-02-12 22:58:19 +00:00
|
|
|
*/
|
|
|
|
static inline int pte_protnone(pte_t pte)
|
|
|
|
{
|
2015-02-19 13:06:53 +00:00
|
|
|
return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT))
|
|
|
|
== _PAGE_PROTNONE;
|
2015-02-12 22:58:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pmd_protnone(pmd_t pmd)
|
|
|
|
{
|
2015-02-19 13:06:53 +00:00
|
|
|
return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT))
|
|
|
|
== _PAGE_PROTNONE;
|
2015-02-12 22:58:19 +00:00
|
|
|
}
|
|
|
|
#endif /* CONFIG_NUMA_BALANCING */
|
|
|
|
|
2009-02-05 19:30:51 +00:00
|
|
|
static inline int pmd_none(pmd_t pmd)
|
|
|
|
{
|
|
|
|
/* Only check low word on 32-bit platforms, since it might be
|
|
|
|
out of sync with upper half. */
|
2016-07-08 00:19:12 +00:00
|
|
|
unsigned long val = native_pmd_val(pmd);
|
|
|
|
return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0;
|
2009-02-05 19:30:51 +00:00
|
|
|
}
|
|
|
|
|
2009-02-05 19:30:59 +00:00
|
|
|
static inline unsigned long pmd_page_vaddr(pmd_t pmd)
|
|
|
|
{
|
2015-09-17 18:24:17 +00:00
|
|
|
return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd));
|
2009-02-05 19:30:59 +00:00
|
|
|
}
|
|
|
|
|
2009-02-09 10:42:57 +00:00
|
|
|
/*
|
|
|
|
* Currently stuck as a macro due to indirect forward reference to
|
|
|
|
* linux/mmzone.h's __section_mem_map_addr() definition:
|
|
|
|
*/
|
2017-07-17 21:10:06 +00:00
|
|
|
#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
|
2009-02-05 19:31:00 +00:00
|
|
|
|
2009-02-05 19:31:05 +00:00
|
|
|
/*
|
|
|
|
* Conversion functions: convert a page and protection to a page entry,
|
|
|
|
* and a page entry and page directory to the page they refer to.
|
|
|
|
*
|
|
|
|
* (Currently stuck as a macro because of indirect forward reference
|
|
|
|
* to linux/mm.h:page_to_nid())
|
|
|
|
*/
|
|
|
|
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
|
|
|
|
|
2009-02-05 19:31:11 +00:00
|
|
|
static inline int pmd_bad(pmd_t pmd)
|
|
|
|
{
|
2022-09-18 07:59:59 +00:00
|
|
|
return (pmd_flags(pmd) & ~(_PAGE_USER | _PAGE_ACCESSED)) !=
|
|
|
|
(_KERNPG_TABLE & ~_PAGE_ACCESSED);
|
2009-02-05 19:31:11 +00:00
|
|
|
}
|
|
|
|
|
2009-02-05 19:31:12 +00:00
|
|
|
static inline unsigned long pages_to_mb(unsigned long npg)
|
|
|
|
{
|
|
|
|
return npg >> (20 - PAGE_SHIFT);
|
|
|
|
}
|
|
|
|
|
2015-04-14 22:46:14 +00:00
|
|
|
#if CONFIG_PGTABLE_LEVELS > 2
|
2009-02-05 19:31:13 +00:00
|
|
|
static inline int pud_none(pud_t pud)
|
|
|
|
{
|
2016-07-08 00:19:12 +00:00
|
|
|
return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0;
|
2009-02-05 19:31:13 +00:00
|
|
|
}
|
|
|
|
|
2009-02-05 19:30:48 +00:00
|
|
|
static inline int pud_present(pud_t pud)
|
|
|
|
{
|
2009-02-05 19:31:16 +00:00
|
|
|
return pud_flags(pud) & _PAGE_PRESENT;
|
2009-02-05 19:30:48 +00:00
|
|
|
}
|
2009-02-05 19:30:53 +00:00
|
|
|
|
2021-07-08 01:09:53 +00:00
|
|
|
static inline pmd_t *pud_pgtable(pud_t pud)
|
2009-02-05 19:30:53 +00:00
|
|
|
{
|
2021-07-08 01:09:53 +00:00
|
|
|
return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud));
|
2009-02-05 19:30:53 +00:00
|
|
|
}
|
2009-02-05 19:30:55 +00:00
|
|
|
|
2009-02-09 10:42:57 +00:00
|
|
|
/*
|
|
|
|
* Currently stuck as a macro due to indirect forward reference to
|
|
|
|
* linux/mmzone.h's __section_mem_map_addr() definition:
|
|
|
|
*/
|
2017-07-17 21:10:06 +00:00
|
|
|
#define pud_page(pud) pfn_to_page(pud_pfn(pud))
|
2009-02-05 19:31:02 +00:00
|
|
|
|
2020-02-04 01:35:41 +00:00
|
|
|
#define pud_leaf pud_large
|
2009-02-05 19:31:08 +00:00
|
|
|
static inline int pud_large(pud_t pud)
|
|
|
|
{
|
2009-02-09 08:09:52 +00:00
|
|
|
return (pud_val(pud) & (_PAGE_PSE | _PAGE_PRESENT)) ==
|
2009-02-05 19:31:08 +00:00
|
|
|
(_PAGE_PSE | _PAGE_PRESENT);
|
|
|
|
}
|
2009-02-05 19:31:10 +00:00
|
|
|
|
|
|
|
static inline int pud_bad(pud_t pud)
|
|
|
|
{
|
2009-02-05 19:31:16 +00:00
|
|
|
return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0;
|
2009-02-05 19:31:10 +00:00
|
|
|
}
|
2009-02-09 08:09:52 +00:00
|
|
|
#else
|
2020-02-04 01:35:41 +00:00
|
|
|
#define pud_leaf pud_large
|
2009-02-09 08:09:52 +00:00
|
|
|
static inline int pud_large(pud_t pud)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2015-04-14 22:46:14 +00:00
|
|
|
#endif /* CONFIG_PGTABLE_LEVELS > 2 */
|
2009-02-05 19:30:48 +00:00
|
|
|
|
2017-03-17 18:55:15 +00:00
|
|
|
#if CONFIG_PGTABLE_LEVELS > 3
|
|
|
|
static inline int p4d_none(p4d_t p4d)
|
|
|
|
{
|
|
|
|
return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int p4d_present(p4d_t p4d)
|
|
|
|
{
|
|
|
|
return p4d_flags(p4d) & _PAGE_PRESENT;
|
|
|
|
}
|
|
|
|
|
2021-07-08 01:09:56 +00:00
|
|
|
static inline pud_t *p4d_pgtable(p4d_t p4d)
|
2017-03-17 18:55:15 +00:00
|
|
|
{
|
2021-07-08 01:09:56 +00:00
|
|
|
return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d));
|
2017-03-17 18:55:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Currently stuck as a macro due to indirect forward reference to
|
|
|
|
* linux/mmzone.h's __section_mem_map_addr() definition:
|
|
|
|
*/
|
2017-07-17 21:10:06 +00:00
|
|
|
#define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d))
|
2017-03-17 18:55:15 +00:00
|
|
|
|
|
|
|
static inline int p4d_bad(p4d_t p4d)
|
|
|
|
{
|
2017-12-04 14:07:38 +00:00
|
|
|
unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER;
|
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
|
|
|
|
ignore_flags |= _PAGE_NX;
|
|
|
|
|
|
|
|
return (p4d_flags(p4d) & ~ignore_flags) != 0;
|
2017-03-17 18:55:15 +00:00
|
|
|
}
|
|
|
|
#endif /* CONFIG_PGTABLE_LEVELS > 3 */
|
|
|
|
|
2017-03-13 14:33:04 +00:00
|
|
|
static inline unsigned long p4d_index(unsigned long address)
|
|
|
|
{
|
|
|
|
return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1);
|
|
|
|
}
|
|
|
|
|
2017-03-17 18:55:15 +00:00
|
|
|
#if CONFIG_PGTABLE_LEVELS > 4
|
2009-02-05 19:30:49 +00:00
|
|
|
static inline int pgd_present(pgd_t pgd)
|
|
|
|
{
|
2018-05-18 10:35:24 +00:00
|
|
|
if (!pgtable_l5_enabled())
|
2018-02-14 18:25:40 +00:00
|
|
|
return 1;
|
2009-02-05 19:31:16 +00:00
|
|
|
return pgd_flags(pgd) & _PAGE_PRESENT;
|
2009-02-05 19:30:49 +00:00
|
|
|
}
|
2009-02-05 19:30:52 +00:00
|
|
|
|
|
|
|
static inline unsigned long pgd_page_vaddr(pgd_t pgd)
|
|
|
|
{
|
|
|
|
return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK);
|
|
|
|
}
|
2009-02-05 19:30:56 +00:00
|
|
|
|
2009-02-09 10:42:57 +00:00
|
|
|
/*
|
|
|
|
* Currently stuck as a macro due to indirect forward reference to
|
|
|
|
* linux/mmzone.h's __section_mem_map_addr() definition:
|
|
|
|
*/
|
2017-07-17 21:10:06 +00:00
|
|
|
#define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd))
|
2009-02-05 19:30:57 +00:00
|
|
|
|
|
|
|
/* to find an entry in a page-table-directory. */
|
2018-06-26 10:03:41 +00:00
|
|
|
static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address)
|
2009-02-05 19:30:58 +00:00
|
|
|
{
|
2018-05-18 10:35:24 +00:00
|
|
|
if (!pgtable_l5_enabled())
|
2018-02-14 18:25:40 +00:00
|
|
|
return (p4d_t *)pgd;
|
2017-03-17 18:55:15 +00:00
|
|
|
return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address);
|
2009-02-05 19:30:58 +00:00
|
|
|
}
|
2009-02-05 19:31:09 +00:00
|
|
|
|
|
|
|
static inline int pgd_bad(pgd_t pgd)
|
|
|
|
{
|
2017-12-04 14:07:38 +00:00
|
|
|
unsigned long ignore_flags = _PAGE_USER;
|
|
|
|
|
2018-05-18 10:35:24 +00:00
|
|
|
if (!pgtable_l5_enabled())
|
2018-02-14 18:25:40 +00:00
|
|
|
return 0;
|
|
|
|
|
2017-12-04 14:07:38 +00:00
|
|
|
if (IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
|
|
|
|
ignore_flags |= _PAGE_NX;
|
|
|
|
|
|
|
|
return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE;
|
2009-02-05 19:31:09 +00:00
|
|
|
}
|
2009-02-05 19:31:14 +00:00
|
|
|
|
|
|
|
static inline int pgd_none(pgd_t pgd)
|
|
|
|
{
|
2018-05-18 10:35:24 +00:00
|
|
|
if (!pgtable_l5_enabled())
|
2018-02-14 18:25:40 +00:00
|
|
|
return 0;
|
2016-07-08 00:19:12 +00:00
|
|
|
/*
|
|
|
|
* There is no need to do a workaround for the KNL stray
|
|
|
|
* A/D bit erratum here. PGDs only point to page tables
|
|
|
|
* except on 32-bit non-PAE which is not supported on
|
|
|
|
* KNL.
|
|
|
|
*/
|
2009-02-05 19:31:17 +00:00
|
|
|
return !native_pgd_val(pgd);
|
2009-02-05 19:31:14 +00:00
|
|
|
}
|
2017-03-17 18:55:15 +00:00
|
|
|
#endif /* CONFIG_PGTABLE_LEVELS > 4 */
|
2009-02-05 19:30:49 +00:00
|
|
|
|
2008-01-30 12:32:56 +00:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
2008-03-17 23:37:13 +00:00
|
|
|
#define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET)
|
|
|
|
#define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY)
|
|
|
|
|
2008-01-30 12:32:58 +00:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
2009-04-10 18:33:10 +00:00
|
|
|
extern int direct_gbpages;
|
2012-11-17 03:38:41 +00:00
|
|
|
void init_mem_mapping(void);
|
2012-11-17 03:38:58 +00:00
|
|
|
void early_alloc_pgt_buf(void);
|
2017-01-28 11:45:40 +00:00
|
|
|
extern void memblock_find_dma_reserve(void);
|
2019-04-26 23:22:46 +00:00
|
|
|
void __init poking_init(void);
|
2020-04-10 21:33:24 +00:00
|
|
|
unsigned long init_memory_mapping(unsigned long start,
|
|
|
|
unsigned long end, pgprot_t prot);
|
2020-06-06 12:37:43 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
extern pgd_t trampoline_pgd_entry;
|
2016-06-22 00:47:01 +00:00
|
|
|
#endif
|
|
|
|
|
2008-01-30 12:32:58 +00:00
|
|
|
/* local pte updates need not use xchg for locking */
|
|
|
|
static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
|
|
|
|
{
|
|
|
|
pte_t res = *ptep;
|
|
|
|
|
|
|
|
/* Pure native function needs no input for mm, addr */
|
|
|
|
native_pte_clear(NULL, 0, ptep);
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp)
|
|
|
|
{
|
|
|
|
pmd_t res = *pmdp;
|
|
|
|
|
|
|
|
native_pmd_clear(pmdp);
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp)
|
|
|
|
{
|
|
|
|
pud_t res = *pudp;
|
|
|
|
|
|
|
|
native_pud_clear(pudp);
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2020-08-15 10:06:40 +00:00
|
|
|
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|
|
|
pte_t *ptep, pte_t pte)
|
2008-01-30 12:32:58 +00:00
|
|
|
{
|
2023-08-02 15:13:30 +00:00
|
|
|
page_table_check_ptes_set(mm, ptep, pte, 1);
|
2020-08-15 10:06:40 +00:00
|
|
|
set_pte(ptep, pte);
|
2008-01-30 12:32:58 +00:00
|
|
|
}
|
|
|
|
|
2017-09-04 10:25:27 +00:00
|
|
|
static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
|
|
|
|
pmd_t *pmdp, pmd_t pmd)
|
2011-01-13 23:46:35 +00:00
|
|
|
{
|
2023-07-13 17:26:35 +00:00
|
|
|
page_table_check_pmd_set(mm, pmdp, pmd);
|
2019-02-10 07:40:56 +00:00
|
|
|
set_pmd(pmdp, pmd);
|
2011-01-13 23:46:35 +00:00
|
|
|
}
|
|
|
|
|
2017-09-04 10:25:27 +00:00
|
|
|
static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
|
|
|
|
pud_t *pudp, pud_t pud)
|
2017-02-24 22:57:02 +00:00
|
|
|
{
|
2023-07-13 17:26:36 +00:00
|
|
|
page_table_check_pud_set(mm, pudp, pud);
|
2017-02-24 22:57:02 +00:00
|
|
|
native_set_pud(pudp, pud);
|
|
|
|
}
|
|
|
|
|
2008-01-30 12:32:58 +00:00
|
|
|
/*
|
|
|
|
* We only update the dirty/accessed state if we set
|
|
|
|
* the dirty bit by hand in the kernel, since the hardware
|
|
|
|
* will do the accessed bit for us, and we don't want to
|
|
|
|
* race with other CPU's that might be updating the dirty
|
|
|
|
* bit at the same time.
|
|
|
|
*/
|
2008-06-25 04:18:57 +00:00
|
|
|
struct vm_area_struct;
|
|
|
|
|
2008-01-30 12:32:58 +00:00
|
|
|
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
2008-03-17 23:37:03 +00:00
|
|
|
extern int ptep_set_access_flags(struct vm_area_struct *vma,
|
|
|
|
unsigned long address, pte_t *ptep,
|
|
|
|
pte_t entry, int dirty);
|
2008-01-30 12:32:58 +00:00
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
2008-03-17 23:37:04 +00:00
|
|
|
extern int ptep_test_and_clear_young(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, pte_t *ptep);
|
2008-01-30 12:32:58 +00:00
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
|
2008-03-17 23:37:05 +00:00
|
|
|
extern int ptep_clear_flush_young(struct vm_area_struct *vma,
|
|
|
|
unsigned long address, pte_t *ptep);
|
2008-01-30 12:32:58 +00:00
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
2008-03-23 08:03:12 +00:00
|
|
|
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
|
|
|
|
pte_t *ptep)
|
2008-01-30 12:32:58 +00:00
|
|
|
{
|
|
|
|
pte_t pte = native_ptep_get_and_clear(ptep);
|
2023-07-13 17:26:31 +00:00
|
|
|
page_table_check_pte_clear(mm, pte);
|
2008-01-30 12:32:58 +00:00
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
|
2008-03-23 08:03:12 +00:00
|
|
|
static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
|
|
|
|
unsigned long addr, pte_t *ptep,
|
|
|
|
int full)
|
2008-01-30 12:32:58 +00:00
|
|
|
{
|
|
|
|
pte_t pte;
|
|
|
|
if (full) {
|
|
|
|
/*
|
|
|
|
* Full address destruction in progress; paravirt does not
|
|
|
|
* care about updates and native needs no locking
|
|
|
|
*/
|
|
|
|
pte = native_local_ptep_get_and_clear(ptep);
|
2023-07-13 17:26:31 +00:00
|
|
|
page_table_check_pte_clear(mm, pte);
|
2008-01-30 12:32:58 +00:00
|
|
|
} else {
|
|
|
|
pte = ptep_get_and_clear(mm, addr, ptep);
|
|
|
|
}
|
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
|
2008-03-23 08:03:12 +00:00
|
|
|
static inline void ptep_set_wrprotect(struct mm_struct *mm,
|
|
|
|
unsigned long addr, pte_t *ptep)
|
2008-01-30 12:32:58 +00:00
|
|
|
{
|
2008-01-30 12:32:58 +00:00
|
|
|
clear_bit(_PAGE_BIT_RW, (unsigned long *)&ptep->pte);
|
2008-01-30 12:32:58 +00:00
|
|
|
}
|
|
|
|
|
2023-03-06 16:15:48 +00:00
|
|
|
#define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0)
|
x86, mm: Avoid unnecessary TLB flush
In x86, access and dirty bits are set automatically by CPU when CPU accesses
memory. When we go into the code path of below flush_tlb_fix_spurious_fault(),
we already set dirty bit for pte and don't need flush tlb. This might mean
tlb entry in some CPUs hasn't dirty bit set, but this doesn't matter. When
the CPUs do page write, they will automatically check the bit and no software
involved.
On the other hand, flush tlb in below position is harmful. Test creates CPU
number of threads, each thread writes to a same but random address in same vma
range and we measure the total time. Under a 4 socket system, original time is
1.96s, while with the patch, the time is 0.8s. Under a 2 socket system, there is
20% time cut too. perf shows a lot of time are taking to send ipi/handle ipi for
tlb flush.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
LKML-Reference: <20100816011655.GA362@sli10-desk.sh.intel.com>
Acked-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: Andrea Archangeli <aarcange@redhat.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2010-08-16 01:16:55 +00:00
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
|
|
|
|
extern int pmdp_set_access_flags(struct vm_area_struct *vma,
|
|
|
|
unsigned long address, pmd_t *pmdp,
|
|
|
|
pmd_t entry, int dirty);
|
2017-02-24 22:57:02 +00:00
|
|
|
extern int pudp_set_access_flags(struct vm_area_struct *vma,
|
|
|
|
unsigned long address, pud_t *pudp,
|
|
|
|
pud_t entry, int dirty);
|
2011-01-13 23:47:01 +00:00
|
|
|
|
|
|
|
#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
|
|
|
|
extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, pmd_t *pmdp);
|
2017-02-24 22:57:02 +00:00
|
|
|
extern int pudp_test_and_clear_young(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, pud_t *pudp);
|
2011-01-13 23:47:01 +00:00
|
|
|
|
|
|
|
#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
|
|
|
|
extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
|
|
|
|
unsigned long address, pmd_t *pmdp);
|
|
|
|
|
|
|
|
|
2017-11-30 00:10:10 +00:00
|
|
|
#define pmd_write pmd_write
|
2011-01-13 23:47:01 +00:00
|
|
|
static inline int pmd_write(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_flags(pmd) & _PAGE_RW;
|
|
|
|
}
|
|
|
|
|
2015-06-24 23:57:44 +00:00
|
|
|
#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
|
|
|
|
static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr,
|
2011-01-13 23:47:01 +00:00
|
|
|
pmd_t *pmdp)
|
|
|
|
{
|
2022-01-14 22:06:41 +00:00
|
|
|
pmd_t pmd = native_pmdp_get_and_clear(pmdp);
|
|
|
|
|
2023-07-13 17:26:32 +00:00
|
|
|
page_table_check_pmd_clear(mm, pmd);
|
2022-01-14 22:06:41 +00:00
|
|
|
|
|
|
|
return pmd;
|
2011-01-13 23:47:01 +00:00
|
|
|
}
|
|
|
|
|
2017-02-24 22:57:02 +00:00
|
|
|
#define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
|
|
|
|
static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
|
|
|
|
unsigned long addr, pud_t *pudp)
|
|
|
|
{
|
2022-01-14 22:06:41 +00:00
|
|
|
pud_t pud = native_pudp_get_and_clear(pudp);
|
|
|
|
|
2023-07-13 17:26:33 +00:00
|
|
|
page_table_check_pud_clear(mm, pud);
|
2022-01-14 22:06:41 +00:00
|
|
|
|
|
|
|
return pud;
|
2017-02-24 22:57:02 +00:00
|
|
|
}
|
|
|
|
|
2011-01-13 23:47:01 +00:00
|
|
|
#define __HAVE_ARCH_PMDP_SET_WRPROTECT
|
|
|
|
static inline void pmdp_set_wrprotect(struct mm_struct *mm,
|
|
|
|
unsigned long addr, pmd_t *pmdp)
|
|
|
|
{
|
|
|
|
clear_bit(_PAGE_BIT_RW, (unsigned long *)pmdp);
|
|
|
|
}
|
|
|
|
|
2017-11-30 00:10:06 +00:00
|
|
|
#define pud_write pud_write
|
|
|
|
static inline int pud_write(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_flags(pud) & _PAGE_RW;
|
|
|
|
}
|
|
|
|
|
2018-02-01 00:18:13 +00:00
|
|
|
#ifndef pmdp_establish
|
|
|
|
#define pmdp_establish pmdp_establish
|
|
|
|
static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
|
|
|
|
unsigned long address, pmd_t *pmdp, pmd_t pmd)
|
|
|
|
{
|
2023-07-13 17:26:35 +00:00
|
|
|
page_table_check_pmd_set(vma->vm_mm, pmdp, pmd);
|
2018-02-01 00:18:13 +00:00
|
|
|
if (IS_ENABLED(CONFIG_SMP)) {
|
|
|
|
return xchg(pmdp, pmd);
|
|
|
|
} else {
|
|
|
|
pmd_t old = *pmdp;
|
2018-09-02 18:14:50 +00:00
|
|
|
WRITE_ONCE(*pmdp, pmd);
|
2018-02-01 00:18:13 +00:00
|
|
|
return old;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2022-05-10 01:20:50 +00:00
|
|
|
|
|
|
|
#define __HAVE_ARCH_PMDP_INVALIDATE_AD
|
|
|
|
extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma,
|
|
|
|
unsigned long address, pmd_t *pmdp);
|
|
|
|
|
2018-07-18 09:40:57 +00:00
|
|
|
/*
|
|
|
|
* Page table pages are page-aligned. The lower half of the top
|
|
|
|
* level is used for userspace and the top half for the kernel.
|
|
|
|
*
|
|
|
|
* Returns true for parts of the PGD that map userspace and
|
|
|
|
* false for the parts that map the kernel.
|
|
|
|
*/
|
|
|
|
static inline bool pgdp_maps_userspace(void *__ptr)
|
|
|
|
{
|
|
|
|
unsigned long ptr = (unsigned long)__ptr;
|
|
|
|
|
|
|
|
return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START);
|
|
|
|
}
|
|
|
|
|
2020-02-04 01:35:41 +00:00
|
|
|
#define pgd_leaf pgd_large
|
2018-07-18 09:40:57 +00:00
|
|
|
static inline int pgd_large(pgd_t pgd) { return 0; }
|
2018-02-01 00:18:13 +00:00
|
|
|
|
2018-07-18 09:40:55 +00:00
|
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
|
|
/*
|
|
|
|
* All top-level PAGE_TABLE_ISOLATION page tables are order-1 pages
|
|
|
|
* (8k-aligned and 8k in size). The kernel one is at the beginning 4k and
|
|
|
|
* the user one is in the last 4k. To switch between them, you
|
|
|
|
* just need to flip the 12th bit in their addresses.
|
|
|
|
*/
|
|
|
|
#define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This generates better code than the inline assembly in
|
|
|
|
* __set_bit().
|
|
|
|
*/
|
|
|
|
static inline void *ptr_set_bit(void *ptr, int bit)
|
|
|
|
{
|
|
|
|
unsigned long __ptr = (unsigned long)ptr;
|
|
|
|
|
|
|
|
__ptr |= BIT(bit);
|
|
|
|
return (void *)__ptr;
|
|
|
|
}
|
|
|
|
static inline void *ptr_clear_bit(void *ptr, int bit)
|
|
|
|
{
|
|
|
|
unsigned long __ptr = (unsigned long)ptr;
|
|
|
|
|
|
|
|
__ptr &= ~BIT(bit);
|
|
|
|
return (void *)__ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp)
|
|
|
|
{
|
|
|
|
return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp)
|
|
|
|
{
|
|
|
|
return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp)
|
|
|
|
{
|
|
|
|
return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp)
|
|
|
|
{
|
|
|
|
return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PAGE_TABLE_ISOLATION */
|
|
|
|
|
2008-03-17 23:37:14 +00:00
|
|
|
/*
|
|
|
|
* clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
|
|
|
|
*
|
2021-03-18 14:28:01 +00:00
|
|
|
* dst - pointer to pgd range anywhere on a pgd page
|
2008-03-17 23:37:14 +00:00
|
|
|
* src - ""
|
|
|
|
* count - the number of pgds to copy.
|
|
|
|
*
|
|
|
|
* dst and src can be on the same page, but the range must not overlap,
|
|
|
|
* and must not cross a page boundary.
|
|
|
|
*/
|
|
|
|
static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
|
|
|
|
{
|
2017-12-04 14:07:40 +00:00
|
|
|
memcpy(dst, src, count * sizeof(pgd_t));
|
|
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
|
|
if (!static_cpu_has(X86_FEATURE_PTI))
|
|
|
|
return;
|
|
|
|
/* Clone the user space pgd as well */
|
|
|
|
memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src),
|
|
|
|
count * sizeof(pgd_t));
|
|
|
|
#endif
|
2008-03-17 23:37:14 +00:00
|
|
|
}
|
|
|
|
|
2013-01-22 21:24:31 +00:00
|
|
|
#define PTE_SHIFT ilog2(PTRS_PER_PTE)
|
|
|
|
static inline int page_level_shift(enum pg_level level)
|
|
|
|
{
|
|
|
|
return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT;
|
|
|
|
}
|
|
|
|
static inline unsigned long page_level_size(enum pg_level level)
|
|
|
|
{
|
|
|
|
return 1UL << page_level_shift(level);
|
|
|
|
}
|
|
|
|
static inline unsigned long page_level_mask(enum pg_level level)
|
|
|
|
{
|
|
|
|
return ~(page_level_size(level) - 1);
|
|
|
|
}
|
2008-03-17 23:37:14 +00:00
|
|
|
|
2012-12-18 20:22:18 +00:00
|
|
|
/*
|
|
|
|
* The x86 doesn't have any external MMU info: the kernel page
|
|
|
|
* tables contain all the necessary information.
|
|
|
|
*/
|
|
|
|
static inline void update_mmu_cache(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, pte_t *ptep)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, pmd_t *pmd)
|
|
|
|
{
|
|
|
|
}
|
2017-02-24 22:57:02 +00:00
|
|
|
static inline void update_mmu_cache_pud(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, pud_t *pud)
|
|
|
|
{
|
|
|
|
}
|
2022-05-10 01:20:46 +00:00
|
|
|
static inline pte_t pte_swp_mkexclusive(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_set_flags(pte, _PAGE_SWP_EXCLUSIVE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pte_swp_exclusive(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_swp_clear_exclusive(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_clear_flags(pte, _PAGE_SWP_EXCLUSIVE);
|
|
|
|
}
|
2008-03-17 23:37:14 +00:00
|
|
|
|
2014-06-04 23:08:16 +00:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
|
2013-09-11 21:22:47 +00:00
|
|
|
static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pte_swp_soft_dirty(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY);
|
|
|
|
}
|
2017-09-08 23:11:04 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
|
|
|
|
static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pmd_swp_soft_dirty(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY);
|
|
|
|
}
|
|
|
|
#endif
|
2014-06-04 23:08:16 +00:00
|
|
|
#endif
|
2013-09-11 21:22:47 +00:00
|
|
|
|
2020-04-07 03:05:33 +00:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
|
|
|
|
static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_set_flags(pte, _PAGE_SWP_UFFD_WP);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pte_swp_uffd_wp(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_flags(pte) & _PAGE_SWP_UFFD_WP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
|
|
|
|
{
|
|
|
|
return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP);
|
|
|
|
}
|
2020-04-07 03:05:57 +00:00
|
|
|
|
|
|
|
static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pmd_swp_uffd_wp(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP);
|
|
|
|
}
|
2020-04-07 03:05:33 +00:00
|
|
|
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
|
|
|
|
|
mm/gup, x86/mm/pkeys: Check VMAs and PTEs for protection keys
Today, for normal faults and page table walks, we check the VMA
and/or PTE to ensure that it is compatible with the action. For
instance, if we get a write fault on a non-writeable VMA, we
SIGSEGV.
We try to do the same thing for protection keys. Basically, we
try to make sure that if a user does this:
mprotect(ptr, size, PROT_NONE);
*ptr = foo;
they see the same effects with protection keys when they do this:
mprotect(ptr, size, PROT_READ|PROT_WRITE);
set_pkey(ptr, size, 4);
wrpkru(0xffffff3f); // access disable pkey 4
*ptr = foo;
The state to do that checking is in the VMA, but we also
sometimes have to do it on the page tables only, like when doing
a get_user_pages_fast() where we have no VMA.
We add two functions and expose them to generic code:
arch_pte_access_permitted(pte_flags, write)
arch_vma_access_permitted(vma, write)
These are, of course, backed up in x86 arch code with checks
against the PTE or VMA's protection key.
But, there are also cases where we do not want to respect
protection keys. When we ptrace(), for instance, we do not want
to apply the tracer's PKRU permissions to the PTEs from the
process being traced.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Boaz Harrosh <boaz@plexistor.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Dave Hansen <dave@sr71.net>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: David Hildenbrand <dahi@linux.vnet.ibm.com>
Cc: David Vrabel <david.vrabel@citrix.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Dominik Dingel <dingel@linux.vnet.ibm.com>
Cc: Dominik Vogt <vogt@linux.vnet.ibm.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Hugh Dickins <hughd@google.com>
Cc: Jason Low <jason.low2@hp.com>
Cc: Jerome Marchand <jmarchan@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Matthew Wilcox <willy@linux.intel.com>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Mikulas Patocka <mpatocka@redhat.com>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@redhat.com>
Cc: Sasha Levin <sasha.levin@oracle.com>
Cc: Shachar Raindel <raindel@mellanox.com>
Cc: Stephen Smalley <sds@tycho.nsa.gov>
Cc: Toshi Kani <toshi.kani@hpe.com>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: linux-arch@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org
Cc: linux-s390@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Link: http://lkml.kernel.org/r/20160212210219.14D5D715@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-02-12 21:02:19 +00:00
|
|
|
static inline u16 pte_flags_pkey(unsigned long pte_flags)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
|
|
|
|
/* ifdef to avoid doing 59-bit shift on 32-bit values */
|
|
|
|
return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0;
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-06-06 11:31:20 +00:00
|
|
|
static inline bool __pkru_allows_pkey(u16 pkey, bool write)
|
|
|
|
{
|
|
|
|
u32 pkru = read_pkru();
|
|
|
|
|
|
|
|
if (!__pkru_allows_read(pkru, pkey))
|
|
|
|
return false;
|
|
|
|
if (write && !__pkru_allows_write(pkru, pkey))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'pteval' can come from a PTE, PMD or PUD. We only check
|
|
|
|
* _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the
|
|
|
|
* same value on all 3 types.
|
|
|
|
*/
|
|
|
|
static inline bool __pte_access_permitted(unsigned long pteval, bool write)
|
|
|
|
{
|
|
|
|
unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER;
|
|
|
|
|
|
|
|
if (write)
|
|
|
|
need_pte_bits |= _PAGE_RW;
|
|
|
|
|
|
|
|
if ((pteval & need_pte_bits) != need_pte_bits)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return __pkru_allows_pkey(pte_flags_pkey(pteval), write);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pte_access_permitted pte_access_permitted
|
|
|
|
static inline bool pte_access_permitted(pte_t pte, bool write)
|
|
|
|
{
|
|
|
|
return __pte_access_permitted(pte_val(pte), write);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pmd_access_permitted pmd_access_permitted
|
|
|
|
static inline bool pmd_access_permitted(pmd_t pmd, bool write)
|
|
|
|
{
|
|
|
|
return __pte_access_permitted(pmd_val(pmd), write);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define pud_access_permitted pud_access_permitted
|
|
|
|
static inline bool pud_access_permitted(pud_t pud, bool write)
|
|
|
|
{
|
|
|
|
return __pte_access_permitted(pud_val(pud), write);
|
|
|
|
}
|
|
|
|
|
2018-06-13 22:48:27 +00:00
|
|
|
#define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1
|
|
|
|
extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot);
|
|
|
|
|
|
|
|
static inline bool arch_has_pfn_modify_check(void)
|
|
|
|
{
|
|
|
|
return boot_cpu_has_bug(X86_BUG_L1TF);
|
|
|
|
}
|
|
|
|
|
mm: x86, arm64: add arch_has_hw_pte_young()
Patch series "Multi-Gen LRU Framework", v14.
What's new
==========
1. OpenWrt, in addition to Android, Arch Linux Zen, Armbian, ChromeOS,
Liquorix, post-factum and XanMod, is now shipping MGLRU on 5.15.
2. Fixed long-tailed direct reclaim latency seen on high-memory (TBs)
machines. The old direct reclaim backoff, which tries to enforce a
minimum fairness among all eligible memcgs, over-swapped by about
(total_mem>>DEF_PRIORITY)-nr_to_reclaim. The new backoff, which
pulls the plug on swapping once the target is met, trades some
fairness for curtailed latency:
https://lore.kernel.org/r/20220918080010.2920238-10-yuzhao@google.com/
3. Fixed minior build warnings and conflicts. More comments and nits.
TLDR
====
The current page reclaim is too expensive in terms of CPU usage and it
often makes poor choices about what to evict. This patchset offers an
alternative solution that is performant, versatile and
straightforward.
Patchset overview
=================
The design and implementation overview is in patch 14:
https://lore.kernel.org/r/20220918080010.2920238-15-yuzhao@google.com/
01. mm: x86, arm64: add arch_has_hw_pte_young()
02. mm: x86: add CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG
Take advantage of hardware features when trying to clear the accessed
bit in many PTEs.
03. mm/vmscan.c: refactor shrink_node()
04. Revert "include/linux/mm_inline.h: fold __update_lru_size() into
its sole caller"
Minor refactors to improve readability for the following patches.
05. mm: multi-gen LRU: groundwork
Adds the basic data structure and the functions that insert pages to
and remove pages from the multi-gen LRU (MGLRU) lists.
06. mm: multi-gen LRU: minimal implementation
A minimal implementation without optimizations.
07. mm: multi-gen LRU: exploit locality in rmap
Exploits spatial locality to improve efficiency when using the rmap.
08. mm: multi-gen LRU: support page table walks
Further exploits spatial locality by optionally scanning page tables.
09. mm: multi-gen LRU: optimize multiple memcgs
Optimizes the overall performance for multiple memcgs running mixed
types of workloads.
10. mm: multi-gen LRU: kill switch
Adds a kill switch to enable or disable MGLRU at runtime.
11. mm: multi-gen LRU: thrashing prevention
12. mm: multi-gen LRU: debugfs interface
Provide userspace with features like thrashing prevention, working set
estimation and proactive reclaim.
13. mm: multi-gen LRU: admin guide
14. mm: multi-gen LRU: design doc
Add an admin guide and a design doc.
Benchmark results
=================
Independent lab results
-----------------------
Based on the popularity of searches [01] and the memory usage in
Google's public cloud, the most popular open-source memory-hungry
applications, in alphabetical order, are:
Apache Cassandra Memcached
Apache Hadoop MongoDB
Apache Spark PostgreSQL
MariaDB (MySQL) Redis
An independent lab evaluated MGLRU with the most widely used benchmark
suites for the above applications. They posted 960 data points along
with kernel metrics and perf profiles collected over more than 500
hours of total benchmark time. Their final reports show that, with 95%
confidence intervals (CIs), the above applications all performed
significantly better for at least part of their benchmark matrices.
On 5.14:
1. Apache Spark [02] took 95% CIs [9.28, 11.19]% and [12.20, 14.93]%
less wall time to sort three billion random integers, respectively,
under the medium- and the high-concurrency conditions, when
overcommitting memory. There were no statistically significant
changes in wall time for the rest of the benchmark matrix.
2. MariaDB [03] achieved 95% CIs [5.24, 10.71]% and [20.22, 25.97]%
more transactions per minute (TPM), respectively, under the medium-
and the high-concurrency conditions, when overcommitting memory.
There were no statistically significant changes in TPM for the rest
of the benchmark matrix.
3. Memcached [04] achieved 95% CIs [23.54, 32.25]%, [20.76, 41.61]%
and [21.59, 30.02]% more operations per second (OPS), respectively,
for sequential access, random access and Gaussian (distribution)
access, when THP=always; 95% CIs [13.85, 15.97]% and
[23.94, 29.92]% more OPS, respectively, for random access and
Gaussian access, when THP=never. There were no statistically
significant changes in OPS for the rest of the benchmark matrix.
4. MongoDB [05] achieved 95% CIs [2.23, 3.44]%, [6.97, 9.73]% and
[2.16, 3.55]% more operations per second (OPS), respectively, for
exponential (distribution) access, random access and Zipfian
(distribution) access, when underutilizing memory; 95% CIs
[8.83, 10.03]%, [21.12, 23.14]% and [5.53, 6.46]% more OPS,
respectively, for exponential access, random access and Zipfian
access, when overcommitting memory.
On 5.15:
5. Apache Cassandra [06] achieved 95% CIs [1.06, 4.10]%, [1.94, 5.43]%
and [4.11, 7.50]% more operations per second (OPS), respectively,
for exponential (distribution) access, random access and Zipfian
(distribution) access, when swap was off; 95% CIs [0.50, 2.60]%,
[6.51, 8.77]% and [3.29, 6.75]% more OPS, respectively, for
exponential access, random access and Zipfian access, when swap was
on.
6. Apache Hadoop [07] took 95% CIs [5.31, 9.69]% and [2.02, 7.86]%
less average wall time to finish twelve parallel TeraSort jobs,
respectively, under the medium- and the high-concurrency
conditions, when swap was on. There were no statistically
significant changes in average wall time for the rest of the
benchmark matrix.
7. PostgreSQL [08] achieved 95% CI [1.75, 6.42]% more transactions per
minute (TPM) under the high-concurrency condition, when swap was
off; 95% CIs [12.82, 18.69]% and [22.70, 46.86]% more TPM,
respectively, under the medium- and the high-concurrency
conditions, when swap was on. There were no statistically
significant changes in TPM for the rest of the benchmark matrix.
8. Redis [09] achieved 95% CIs [0.58, 5.94]%, [6.55, 14.58]% and
[11.47, 19.36]% more total operations per second (OPS),
respectively, for sequential access, random access and Gaussian
(distribution) access, when THP=always; 95% CIs [1.27, 3.54]%,
[10.11, 14.81]% and [8.75, 13.64]% more total OPS, respectively,
for sequential access, random access and Gaussian access, when
THP=never.
Our lab results
---------------
To supplement the above results, we ran the following benchmark suites
on 5.16-rc7 and found no regressions [10].
fs_fio_bench_hdd_mq pft
fs_lmbench pgsql-hammerdb
fs_parallelio redis
fs_postmark stream
hackbench sysbenchthread
kernbench tpcc_spark
memcached unixbench
multichase vm-scalability
mutilate will-it-scale
nginx
[01] https://trends.google.com
[02] https://lore.kernel.org/r/20211102002002.92051-1-bot@edi.works/
[03] https://lore.kernel.org/r/20211009054315.47073-1-bot@edi.works/
[04] https://lore.kernel.org/r/20211021194103.65648-1-bot@edi.works/
[05] https://lore.kernel.org/r/20211109021346.50266-1-bot@edi.works/
[06] https://lore.kernel.org/r/20211202062806.80365-1-bot@edi.works/
[07] https://lore.kernel.org/r/20211209072416.33606-1-bot@edi.works/
[08] https://lore.kernel.org/r/20211218071041.24077-1-bot@edi.works/
[09] https://lore.kernel.org/r/20211122053248.57311-1-bot@edi.works/
[10] https://lore.kernel.org/r/20220104202247.2903702-1-yuzhao@google.com/
Read-world applications
=======================
Third-party testimonials
------------------------
Konstantin reported [11]:
I have Archlinux with 8G RAM + zswap + swap. While developing, I
have lots of apps opened such as multiple LSP-servers for different
langs, chats, two browsers, etc... Usually, my system gets quickly
to a point of SWAP-storms, where I have to kill LSP-servers,
restart browsers to free memory, etc, otherwise the system lags
heavily and is barely usable.
1.5 day ago I migrated from 5.11.15 kernel to 5.12 + the LRU
patchset, and I started up by opening lots of apps to create memory
pressure, and worked for a day like this. Till now I had not a
single SWAP-storm, and mind you I got 3.4G in SWAP. I was never
getting to the point of 3G in SWAP before without a single
SWAP-storm.
Vaibhav from IBM reported [12]:
In a synthetic MongoDB Benchmark, seeing an average of ~19%
throughput improvement on POWER10(Radix MMU + 64K Page Size) with
MGLRU patches on top of 5.16 kernel for MongoDB + YCSB across
three different request distributions, namely, Exponential, Uniform
and Zipfan.
Shuang from U of Rochester reported [13]:
With the MGLRU, fio achieved 95% CIs [38.95, 40.26]%, [4.12, 6.64]%
and [9.26, 10.36]% higher throughput, respectively, for random
access, Zipfian (distribution) access and Gaussian (distribution)
access, when the average number of jobs per CPU is 1; 95% CIs
[42.32, 49.15]%, [9.44, 9.89]% and [20.99, 22.86]% higher
throughput, respectively, for random access, Zipfian access and
Gaussian access, when the average number of jobs per CPU is 2.
Daniel from Michigan Tech reported [14]:
With Memcached allocating ~100GB of byte-addressable Optante,
performance improvement in terms of throughput (measured as queries
per second) was about 10% for a series of workloads.
Large-scale deployments
-----------------------
We've rolled out MGLRU to tens of millions of ChromeOS users and
about a million Android users. Google's fleetwide profiling [15] shows
an overall 40% decrease in kswapd CPU usage, in addition to
improvements in other UX metrics, e.g., an 85% decrease in the number
of low-memory kills at the 75th percentile and an 18% decrease in
app launch time at the 50th percentile.
The downstream kernels that have been using MGLRU include:
1. Android [16]
2. Arch Linux Zen [17]
3. Armbian [18]
4. ChromeOS [19]
5. Liquorix [20]
6. OpenWrt [21]
7. post-factum [22]
8. XanMod [23]
[11] https://lore.kernel.org/r/140226722f2032c86301fbd326d91baefe3d7d23.camel@yandex.ru/
[12] https://lore.kernel.org/r/87czj3mux0.fsf@vajain21.in.ibm.com/
[13] https://lore.kernel.org/r/20220105024423.26409-1-szhai2@cs.rochester.edu/
[14] https://lore.kernel.org/r/CA+4-3vksGvKd18FgRinxhqHetBS1hQekJE2gwco8Ja-bJWKtFw@mail.gmail.com/
[15] https://dl.acm.org/doi/10.1145/2749469.2750392
[16] https://android.com
[17] https://archlinux.org
[18] https://armbian.com
[19] https://chromium.org
[20] https://liquorix.net
[21] https://openwrt.org
[22] https://codeberg.org/pf-kernel
[23] https://xanmod.org
Summary
=======
The facts are:
1. The independent lab results and the real-world applications
indicate substantial improvements; there are no known regressions.
2. Thrashing prevention, working set estimation and proactive reclaim
work out of the box; there are no equivalent solutions.
3. There is a lot of new code; no smaller changes have been
demonstrated similar effects.
Our options, accordingly, are:
1. Given the amount of evidence, the reported improvements will likely
materialize for a wide range of workloads.
2. Gauging the interest from the past discussions, the new features
will likely be put to use for both personal computers and data
centers.
3. Based on Google's track record, the new code will likely be well
maintained in the long term. It'd be more difficult if not
impossible to achieve similar effects with other approaches.
This patch (of 14):
Some architectures automatically set the accessed bit in PTEs, e.g., x86
and arm64 v8.2. On architectures that do not have this capability,
clearing the accessed bit in a PTE usually triggers a page fault following
the TLB miss of this PTE (to emulate the accessed bit).
Being aware of this capability can help make better decisions, e.g.,
whether to spread the work out over a period of time to reduce bursty page
faults when trying to clear the accessed bit in many PTEs.
Note that theoretically this capability can be unreliable, e.g.,
hotplugged CPUs might be different from builtin ones. Therefore it should
not be used in architecture-independent code that involves correctness,
e.g., to determine whether TLB flushes are required (in combination with
the accessed bit).
Link: https://lkml.kernel.org/r/20220918080010.2920238-1-yuzhao@google.com
Link: https://lkml.kernel.org/r/20220918080010.2920238-2-yuzhao@google.com
Signed-off-by: Yu Zhao <yuzhao@google.com>
Reviewed-by: Barry Song <baohua@kernel.org>
Acked-by: Brian Geffon <bgeffon@google.com>
Acked-by: Jan Alexander Steffens (heftig) <heftig@archlinux.org>
Acked-by: Oleksandr Natalenko <oleksandr@natalenko.name>
Acked-by: Steven Barrett <steven@liquorix.net>
Acked-by: Suleiman Souhlal <suleiman@google.com>
Acked-by: Will Deacon <will@kernel.org>
Tested-by: Daniel Byrne <djbyrne@mtu.edu>
Tested-by: Donald Carr <d@chaos-reins.com>
Tested-by: Holger Hoffstätte <holger@applied-asynchrony.com>
Tested-by: Konstantin Kharlamov <Hi-Angel@yandex.ru>
Tested-by: Shuang Zhai <szhai2@cs.rochester.edu>
Tested-by: Sofia Trinh <sofia.trinh@edi.works>
Tested-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Hillf Danton <hdanton@sina.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Michael Larabel <Michael@MichaelLarabel.com>
Cc: Michal Hocko <mhocko@kernel.org>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tejun Heo <tj@kernel.org>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: Miaohe Lin <linmiaohe@huawei.com>
Cc: Mike Rapoport <rppt@linux.ibm.com>
Cc: Qi Zheng <zhengqi.arch@bytedance.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2022-09-18 07:59:58 +00:00
|
|
|
#define arch_has_hw_pte_young arch_has_hw_pte_young
|
|
|
|
static inline bool arch_has_hw_pte_young(void)
|
2019-10-11 14:09:38 +00:00
|
|
|
{
|
mm: x86, arm64: add arch_has_hw_pte_young()
Patch series "Multi-Gen LRU Framework", v14.
What's new
==========
1. OpenWrt, in addition to Android, Arch Linux Zen, Armbian, ChromeOS,
Liquorix, post-factum and XanMod, is now shipping MGLRU on 5.15.
2. Fixed long-tailed direct reclaim latency seen on high-memory (TBs)
machines. The old direct reclaim backoff, which tries to enforce a
minimum fairness among all eligible memcgs, over-swapped by about
(total_mem>>DEF_PRIORITY)-nr_to_reclaim. The new backoff, which
pulls the plug on swapping once the target is met, trades some
fairness for curtailed latency:
https://lore.kernel.org/r/20220918080010.2920238-10-yuzhao@google.com/
3. Fixed minior build warnings and conflicts. More comments and nits.
TLDR
====
The current page reclaim is too expensive in terms of CPU usage and it
often makes poor choices about what to evict. This patchset offers an
alternative solution that is performant, versatile and
straightforward.
Patchset overview
=================
The design and implementation overview is in patch 14:
https://lore.kernel.org/r/20220918080010.2920238-15-yuzhao@google.com/
01. mm: x86, arm64: add arch_has_hw_pte_young()
02. mm: x86: add CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG
Take advantage of hardware features when trying to clear the accessed
bit in many PTEs.
03. mm/vmscan.c: refactor shrink_node()
04. Revert "include/linux/mm_inline.h: fold __update_lru_size() into
its sole caller"
Minor refactors to improve readability for the following patches.
05. mm: multi-gen LRU: groundwork
Adds the basic data structure and the functions that insert pages to
and remove pages from the multi-gen LRU (MGLRU) lists.
06. mm: multi-gen LRU: minimal implementation
A minimal implementation without optimizations.
07. mm: multi-gen LRU: exploit locality in rmap
Exploits spatial locality to improve efficiency when using the rmap.
08. mm: multi-gen LRU: support page table walks
Further exploits spatial locality by optionally scanning page tables.
09. mm: multi-gen LRU: optimize multiple memcgs
Optimizes the overall performance for multiple memcgs running mixed
types of workloads.
10. mm: multi-gen LRU: kill switch
Adds a kill switch to enable or disable MGLRU at runtime.
11. mm: multi-gen LRU: thrashing prevention
12. mm: multi-gen LRU: debugfs interface
Provide userspace with features like thrashing prevention, working set
estimation and proactive reclaim.
13. mm: multi-gen LRU: admin guide
14. mm: multi-gen LRU: design doc
Add an admin guide and a design doc.
Benchmark results
=================
Independent lab results
-----------------------
Based on the popularity of searches [01] and the memory usage in
Google's public cloud, the most popular open-source memory-hungry
applications, in alphabetical order, are:
Apache Cassandra Memcached
Apache Hadoop MongoDB
Apache Spark PostgreSQL
MariaDB (MySQL) Redis
An independent lab evaluated MGLRU with the most widely used benchmark
suites for the above applications. They posted 960 data points along
with kernel metrics and perf profiles collected over more than 500
hours of total benchmark time. Their final reports show that, with 95%
confidence intervals (CIs), the above applications all performed
significantly better for at least part of their benchmark matrices.
On 5.14:
1. Apache Spark [02] took 95% CIs [9.28, 11.19]% and [12.20, 14.93]%
less wall time to sort three billion random integers, respectively,
under the medium- and the high-concurrency conditions, when
overcommitting memory. There were no statistically significant
changes in wall time for the rest of the benchmark matrix.
2. MariaDB [03] achieved 95% CIs [5.24, 10.71]% and [20.22, 25.97]%
more transactions per minute (TPM), respectively, under the medium-
and the high-concurrency conditions, when overcommitting memory.
There were no statistically significant changes in TPM for the rest
of the benchmark matrix.
3. Memcached [04] achieved 95% CIs [23.54, 32.25]%, [20.76, 41.61]%
and [21.59, 30.02]% more operations per second (OPS), respectively,
for sequential access, random access and Gaussian (distribution)
access, when THP=always; 95% CIs [13.85, 15.97]% and
[23.94, 29.92]% more OPS, respectively, for random access and
Gaussian access, when THP=never. There were no statistically
significant changes in OPS for the rest of the benchmark matrix.
4. MongoDB [05] achieved 95% CIs [2.23, 3.44]%, [6.97, 9.73]% and
[2.16, 3.55]% more operations per second (OPS), respectively, for
exponential (distribution) access, random access and Zipfian
(distribution) access, when underutilizing memory; 95% CIs
[8.83, 10.03]%, [21.12, 23.14]% and [5.53, 6.46]% more OPS,
respectively, for exponential access, random access and Zipfian
access, when overcommitting memory.
On 5.15:
5. Apache Cassandra [06] achieved 95% CIs [1.06, 4.10]%, [1.94, 5.43]%
and [4.11, 7.50]% more operations per second (OPS), respectively,
for exponential (distribution) access, random access and Zipfian
(distribution) access, when swap was off; 95% CIs [0.50, 2.60]%,
[6.51, 8.77]% and [3.29, 6.75]% more OPS, respectively, for
exponential access, random access and Zipfian access, when swap was
on.
6. Apache Hadoop [07] took 95% CIs [5.31, 9.69]% and [2.02, 7.86]%
less average wall time to finish twelve parallel TeraSort jobs,
respectively, under the medium- and the high-concurrency
conditions, when swap was on. There were no statistically
significant changes in average wall time for the rest of the
benchmark matrix.
7. PostgreSQL [08] achieved 95% CI [1.75, 6.42]% more transactions per
minute (TPM) under the high-concurrency condition, when swap was
off; 95% CIs [12.82, 18.69]% and [22.70, 46.86]% more TPM,
respectively, under the medium- and the high-concurrency
conditions, when swap was on. There were no statistically
significant changes in TPM for the rest of the benchmark matrix.
8. Redis [09] achieved 95% CIs [0.58, 5.94]%, [6.55, 14.58]% and
[11.47, 19.36]% more total operations per second (OPS),
respectively, for sequential access, random access and Gaussian
(distribution) access, when THP=always; 95% CIs [1.27, 3.54]%,
[10.11, 14.81]% and [8.75, 13.64]% more total OPS, respectively,
for sequential access, random access and Gaussian access, when
THP=never.
Our lab results
---------------
To supplement the above results, we ran the following benchmark suites
on 5.16-rc7 and found no regressions [10].
fs_fio_bench_hdd_mq pft
fs_lmbench pgsql-hammerdb
fs_parallelio redis
fs_postmark stream
hackbench sysbenchthread
kernbench tpcc_spark
memcached unixbench
multichase vm-scalability
mutilate will-it-scale
nginx
[01] https://trends.google.com
[02] https://lore.kernel.org/r/20211102002002.92051-1-bot@edi.works/
[03] https://lore.kernel.org/r/20211009054315.47073-1-bot@edi.works/
[04] https://lore.kernel.org/r/20211021194103.65648-1-bot@edi.works/
[05] https://lore.kernel.org/r/20211109021346.50266-1-bot@edi.works/
[06] https://lore.kernel.org/r/20211202062806.80365-1-bot@edi.works/
[07] https://lore.kernel.org/r/20211209072416.33606-1-bot@edi.works/
[08] https://lore.kernel.org/r/20211218071041.24077-1-bot@edi.works/
[09] https://lore.kernel.org/r/20211122053248.57311-1-bot@edi.works/
[10] https://lore.kernel.org/r/20220104202247.2903702-1-yuzhao@google.com/
Read-world applications
=======================
Third-party testimonials
------------------------
Konstantin reported [11]:
I have Archlinux with 8G RAM + zswap + swap. While developing, I
have lots of apps opened such as multiple LSP-servers for different
langs, chats, two browsers, etc... Usually, my system gets quickly
to a point of SWAP-storms, where I have to kill LSP-servers,
restart browsers to free memory, etc, otherwise the system lags
heavily and is barely usable.
1.5 day ago I migrated from 5.11.15 kernel to 5.12 + the LRU
patchset, and I started up by opening lots of apps to create memory
pressure, and worked for a day like this. Till now I had not a
single SWAP-storm, and mind you I got 3.4G in SWAP. I was never
getting to the point of 3G in SWAP before without a single
SWAP-storm.
Vaibhav from IBM reported [12]:
In a synthetic MongoDB Benchmark, seeing an average of ~19%
throughput improvement on POWER10(Radix MMU + 64K Page Size) with
MGLRU patches on top of 5.16 kernel for MongoDB + YCSB across
three different request distributions, namely, Exponential, Uniform
and Zipfan.
Shuang from U of Rochester reported [13]:
With the MGLRU, fio achieved 95% CIs [38.95, 40.26]%, [4.12, 6.64]%
and [9.26, 10.36]% higher throughput, respectively, for random
access, Zipfian (distribution) access and Gaussian (distribution)
access, when the average number of jobs per CPU is 1; 95% CIs
[42.32, 49.15]%, [9.44, 9.89]% and [20.99, 22.86]% higher
throughput, respectively, for random access, Zipfian access and
Gaussian access, when the average number of jobs per CPU is 2.
Daniel from Michigan Tech reported [14]:
With Memcached allocating ~100GB of byte-addressable Optante,
performance improvement in terms of throughput (measured as queries
per second) was about 10% for a series of workloads.
Large-scale deployments
-----------------------
We've rolled out MGLRU to tens of millions of ChromeOS users and
about a million Android users. Google's fleetwide profiling [15] shows
an overall 40% decrease in kswapd CPU usage, in addition to
improvements in other UX metrics, e.g., an 85% decrease in the number
of low-memory kills at the 75th percentile and an 18% decrease in
app launch time at the 50th percentile.
The downstream kernels that have been using MGLRU include:
1. Android [16]
2. Arch Linux Zen [17]
3. Armbian [18]
4. ChromeOS [19]
5. Liquorix [20]
6. OpenWrt [21]
7. post-factum [22]
8. XanMod [23]
[11] https://lore.kernel.org/r/140226722f2032c86301fbd326d91baefe3d7d23.camel@yandex.ru/
[12] https://lore.kernel.org/r/87czj3mux0.fsf@vajain21.in.ibm.com/
[13] https://lore.kernel.org/r/20220105024423.26409-1-szhai2@cs.rochester.edu/
[14] https://lore.kernel.org/r/CA+4-3vksGvKd18FgRinxhqHetBS1hQekJE2gwco8Ja-bJWKtFw@mail.gmail.com/
[15] https://dl.acm.org/doi/10.1145/2749469.2750392
[16] https://android.com
[17] https://archlinux.org
[18] https://armbian.com
[19] https://chromium.org
[20] https://liquorix.net
[21] https://openwrt.org
[22] https://codeberg.org/pf-kernel
[23] https://xanmod.org
Summary
=======
The facts are:
1. The independent lab results and the real-world applications
indicate substantial improvements; there are no known regressions.
2. Thrashing prevention, working set estimation and proactive reclaim
work out of the box; there are no equivalent solutions.
3. There is a lot of new code; no smaller changes have been
demonstrated similar effects.
Our options, accordingly, are:
1. Given the amount of evidence, the reported improvements will likely
materialize for a wide range of workloads.
2. Gauging the interest from the past discussions, the new features
will likely be put to use for both personal computers and data
centers.
3. Based on Google's track record, the new code will likely be well
maintained in the long term. It'd be more difficult if not
impossible to achieve similar effects with other approaches.
This patch (of 14):
Some architectures automatically set the accessed bit in PTEs, e.g., x86
and arm64 v8.2. On architectures that do not have this capability,
clearing the accessed bit in a PTE usually triggers a page fault following
the TLB miss of this PTE (to emulate the accessed bit).
Being aware of this capability can help make better decisions, e.g.,
whether to spread the work out over a period of time to reduce bursty page
faults when trying to clear the accessed bit in many PTEs.
Note that theoretically this capability can be unreliable, e.g.,
hotplugged CPUs might be different from builtin ones. Therefore it should
not be used in architecture-independent code that involves correctness,
e.g., to determine whether TLB flushes are required (in combination with
the accessed bit).
Link: https://lkml.kernel.org/r/20220918080010.2920238-1-yuzhao@google.com
Link: https://lkml.kernel.org/r/20220918080010.2920238-2-yuzhao@google.com
Signed-off-by: Yu Zhao <yuzhao@google.com>
Reviewed-by: Barry Song <baohua@kernel.org>
Acked-by: Brian Geffon <bgeffon@google.com>
Acked-by: Jan Alexander Steffens (heftig) <heftig@archlinux.org>
Acked-by: Oleksandr Natalenko <oleksandr@natalenko.name>
Acked-by: Steven Barrett <steven@liquorix.net>
Acked-by: Suleiman Souhlal <suleiman@google.com>
Acked-by: Will Deacon <will@kernel.org>
Tested-by: Daniel Byrne <djbyrne@mtu.edu>
Tested-by: Donald Carr <d@chaos-reins.com>
Tested-by: Holger Hoffstätte <holger@applied-asynchrony.com>
Tested-by: Konstantin Kharlamov <Hi-Angel@yandex.ru>
Tested-by: Shuang Zhai <szhai2@cs.rochester.edu>
Tested-by: Sofia Trinh <sofia.trinh@edi.works>
Tested-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Hillf Danton <hdanton@sina.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Michael Larabel <Michael@MichaelLarabel.com>
Cc: Michal Hocko <mhocko@kernel.org>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tejun Heo <tj@kernel.org>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: Miaohe Lin <linmiaohe@huawei.com>
Cc: Mike Rapoport <rppt@linux.ibm.com>
Cc: Qi Zheng <zhengqi.arch@bytedance.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2022-09-18 07:59:58 +00:00
|
|
|
return true;
|
2019-10-11 14:09:38 +00:00
|
|
|
}
|
|
|
|
|
2022-11-23 06:45:10 +00:00
|
|
|
#ifdef CONFIG_XEN_PV
|
|
|
|
#define arch_has_hw_nonleaf_pmd_young arch_has_hw_nonleaf_pmd_young
|
|
|
|
static inline bool arch_has_hw_nonleaf_pmd_young(void)
|
|
|
|
{
|
|
|
|
return !cpu_feature_enabled(X86_FEATURE_XENPV);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2022-05-13 03:23:06 +00:00
|
|
|
#ifdef CONFIG_PAGE_TABLE_CHECK
|
|
|
|
static inline bool pte_user_accessible_page(pte_t pte)
|
|
|
|
{
|
|
|
|
return (pte_val(pte) & _PAGE_PRESENT) && (pte_val(pte) & _PAGE_USER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pmd_user_accessible_page(pmd_t pmd)
|
|
|
|
{
|
|
|
|
return pmd_leaf(pmd) && (pmd_val(pmd) & _PAGE_PRESENT) && (pmd_val(pmd) & _PAGE_USER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pud_user_accessible_page(pud_t pud)
|
|
|
|
{
|
|
|
|
return pud_leaf(pud) && (pud_val(pud) & _PAGE_PRESENT) && (pud_val(pud) & _PAGE_USER);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2008-01-30 12:32:58 +00:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
2008-10-23 05:26:29 +00:00
|
|
|
#endif /* _ASM_X86_PGTABLE_H */
|