2019-05-29 14:17:58 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2018-06-27 19:26:09 +00:00
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/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
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#include <linux/debugfs.h>
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#include <linux/errno.h>
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#include <linux/mutex.h>
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2020-07-09 11:04:31 +00:00
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#include <linux/pm_opp.h>
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2018-06-27 19:26:09 +00:00
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#include <linux/sort.h>
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#include <linux/clk.h>
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#include <linux/bitmap.h>
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#include "dpu_kms.h"
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#include "dpu_trace.h"
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#include "dpu_crtc.h"
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#include "dpu_core_perf.h"
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/**
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* enum dpu_perf_mode - performance tuning mode
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* @DPU_PERF_MODE_NORMAL: performance controlled by user mode client
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* @DPU_PERF_MODE_MINIMUM: performance bounded by minimum setting
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* @DPU_PERF_MODE_FIXED: performance bounded by fixed setting
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2020-11-23 11:18:49 +00:00
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* @DPU_PERF_MODE_MAX: maximum value, used for error checking
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2018-06-27 19:26:09 +00:00
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*/
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enum dpu_perf_mode {
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DPU_PERF_MODE_NORMAL,
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DPU_PERF_MODE_MINIMUM,
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DPU_PERF_MODE_FIXED,
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DPU_PERF_MODE_MAX
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};
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2020-07-16 11:35:34 +00:00
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/**
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2020-11-23 11:18:49 +00:00
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* _dpu_core_perf_calc_bw() - to calculate BW per crtc
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* @kms: pointer to the dpu_kms
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* @crtc: pointer to a crtc
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2020-07-16 11:35:34 +00:00
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* Return: returns aggregated BW for all planes in crtc.
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*/
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static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
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struct drm_crtc *crtc)
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{
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struct drm_plane *plane;
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struct dpu_plane_state *pstate;
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u64 crtc_plane_bw = 0;
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u32 bw_factor;
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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pstate = to_dpu_plane_state(plane->state);
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if (!pstate)
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continue;
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crtc_plane_bw += pstate->plane_fetch_bw;
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}
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2022-06-02 20:24:44 +00:00
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bw_factor = kms->catalog->perf->bw_inefficiency_factor;
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2020-07-16 11:35:34 +00:00
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if (bw_factor) {
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crtc_plane_bw *= bw_factor;
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do_div(crtc_plane_bw, 100);
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}
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return crtc_plane_bw;
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}
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/**
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* _dpu_core_perf_calc_clk() - to calculate clock per crtc
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2020-11-23 11:18:49 +00:00
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* @kms: pointer to the dpu_kms
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* @crtc: pointer to a crtc
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* @state: pointer to a crtc state
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2020-07-16 11:35:34 +00:00
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* Return: returns max clk for all planes in crtc.
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*/
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static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
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struct drm_crtc *crtc, struct drm_crtc_state *state)
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{
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struct drm_plane *plane;
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struct dpu_plane_state *pstate;
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struct drm_display_mode *mode;
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u64 crtc_clk;
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u32 clk_factor;
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mode = &state->adjusted_mode;
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crtc_clk = mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode);
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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pstate = to_dpu_plane_state(plane->state);
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if (!pstate)
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continue;
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crtc_clk = max(pstate->plane_clk, crtc_clk);
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}
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2022-06-02 20:24:44 +00:00
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clk_factor = kms->catalog->perf->clk_inefficiency_factor;
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2020-07-16 11:35:34 +00:00
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if (clk_factor) {
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crtc_clk *= clk_factor;
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do_div(crtc_clk, 100);
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}
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return crtc_clk;
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}
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2018-06-27 19:26:09 +00:00
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static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
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{
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struct msm_drm_private *priv;
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priv = crtc->dev->dev_private;
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return to_dpu_kms(priv->kms);
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}
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static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
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struct drm_crtc *crtc,
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struct drm_crtc_state *state,
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struct dpu_core_perf_params *perf)
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{
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if (!kms || !kms->catalog || !crtc || !state || !perf) {
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DPU_ERROR("invalid parameters\n");
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return;
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}
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memset(perf, 0, sizeof(struct dpu_core_perf_params));
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2020-07-16 11:35:34 +00:00
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if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
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2019-06-18 20:24:09 +00:00
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perf->bw_ctl = 0;
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perf->max_per_pipe_ib = 0;
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2018-06-27 19:26:09 +00:00
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perf->core_clk_rate = 0;
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} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
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2019-06-18 20:24:09 +00:00
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perf->bw_ctl = kms->perf.fix_core_ab_vote;
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perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
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2018-06-27 19:26:09 +00:00
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perf->core_clk_rate = kms->perf.fix_core_clk_rate;
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2020-07-16 11:35:34 +00:00
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} else {
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perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
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2022-06-02 20:24:44 +00:00
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perf->max_per_pipe_ib = kms->catalog->perf->min_dram_ib;
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2020-07-16 11:35:34 +00:00
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perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
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2018-06-27 19:26:09 +00:00
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}
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2021-04-30 19:31:04 +00:00
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DRM_DEBUG_ATOMIC(
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2019-06-18 20:24:09 +00:00
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"crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
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2018-06-27 19:26:09 +00:00
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crtc->base.id, perf->core_clk_rate,
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2019-06-18 20:24:09 +00:00
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perf->max_per_pipe_ib, perf->bw_ctl);
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2018-06-27 19:26:09 +00:00
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}
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int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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u32 bw, threshold;
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u64 bw_sum_of_intfs = 0;
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enum dpu_crtc_client_type curr_client_type;
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struct dpu_crtc_state *dpu_cstate;
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struct drm_crtc *tmp_crtc;
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struct dpu_kms *kms;
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if (!crtc || !state) {
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DPU_ERROR("invalid crtc\n");
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return -EINVAL;
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}
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kms = _dpu_crtc_get_kms(crtc);
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2019-09-06 19:23:43 +00:00
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if (!kms->catalog) {
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2018-06-27 19:26:09 +00:00
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DPU_ERROR("invalid parameters\n");
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return 0;
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}
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/* we only need bandwidth check on real-time clients (interfaces) */
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if (dpu_crtc_get_client_type(crtc) == NRT_CLIENT)
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return 0;
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dpu_cstate = to_dpu_crtc_state(state);
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/* obtain new values */
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_dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf);
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2019-06-18 20:24:09 +00:00
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bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
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curr_client_type = dpu_crtc_get_client_type(crtc);
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2018-06-27 19:26:09 +00:00
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2019-06-18 20:24:09 +00:00
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drm_for_each_crtc(tmp_crtc, crtc->dev) {
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if (tmp_crtc->enabled &&
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2023-07-30 01:00:56 +00:00
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dpu_crtc_get_client_type(tmp_crtc) == curr_client_type &&
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tmp_crtc != crtc) {
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2019-06-18 20:24:09 +00:00
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struct dpu_crtc_state *tmp_cstate =
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to_dpu_crtc_state(tmp_crtc->state);
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2021-04-30 19:31:04 +00:00
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DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n",
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2019-06-18 20:24:09 +00:00
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tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
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tmp_cstate->bw_control);
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2020-07-16 11:35:34 +00:00
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2019-06-18 20:24:09 +00:00
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bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl;
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2018-06-27 19:26:09 +00:00
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}
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/* convert bandwidth to kb */
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bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
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2021-04-30 19:31:04 +00:00
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DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw);
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2018-06-27 19:26:09 +00:00
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2022-06-02 20:24:44 +00:00
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threshold = kms->catalog->perf->max_bw_high;
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2018-06-27 19:26:09 +00:00
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2021-04-30 19:31:04 +00:00
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DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold);
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2018-06-27 19:26:09 +00:00
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2020-07-16 11:35:34 +00:00
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if (!threshold) {
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2018-06-27 19:26:09 +00:00
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DPU_ERROR("no bandwidth limits specified\n");
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return -E2BIG;
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} else if (bw > threshold) {
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DPU_ERROR("exceeds bandwidth: %ukb > %ukb\n", bw,
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threshold);
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return -E2BIG;
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}
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}
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return 0;
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}
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static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
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2019-06-18 20:24:09 +00:00
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struct drm_crtc *crtc)
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2018-06-27 19:26:09 +00:00
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{
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2019-06-18 20:24:09 +00:00
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struct dpu_core_perf_params perf = { 0 };
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2018-06-27 19:26:09 +00:00
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enum dpu_crtc_client_type curr_client_type
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= dpu_crtc_get_client_type(crtc);
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struct drm_crtc *tmp_crtc;
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struct dpu_crtc_state *dpu_cstate;
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2020-07-16 11:35:34 +00:00
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int i, ret = 0;
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u64 avg_bw;
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2023-07-30 01:00:54 +00:00
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if (!kms->num_paths)
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return 0;
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2018-06-27 19:26:09 +00:00
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drm_for_each_crtc(tmp_crtc, crtc->dev) {
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2018-12-03 22:47:16 +00:00
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if (tmp_crtc->enabled &&
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2018-06-27 19:26:09 +00:00
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curr_client_type ==
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dpu_crtc_get_client_type(tmp_crtc)) {
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dpu_cstate = to_dpu_crtc_state(tmp_crtc->state);
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2019-06-18 20:24:09 +00:00
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perf.max_per_pipe_ib = max(perf.max_per_pipe_ib,
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dpu_cstate->new_perf.max_per_pipe_ib);
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2018-06-27 19:26:09 +00:00
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2020-07-16 11:35:34 +00:00
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perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;
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2021-04-30 19:31:04 +00:00
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DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n",
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2020-07-16 11:35:34 +00:00
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tmp_crtc->base.id,
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dpu_cstate->new_perf.bw_ctl, kms->num_paths);
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2018-06-27 19:26:09 +00:00
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}
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}
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2020-07-16 11:35:34 +00:00
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avg_bw = perf.bw_ctl;
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do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/
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for (i = 0; i < kms->num_paths; i++)
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icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib);
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2018-06-27 19:26:09 +00:00
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return ret;
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}
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/**
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2020-11-23 11:18:49 +00:00
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* dpu_core_perf_crtc_release_bw() - request zero bandwidth
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* @crtc: pointer to a crtc
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2018-06-27 19:26:09 +00:00
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*
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* Function checks a state variable for the crtc, if all pending commit
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* requests are done, meaning no more bandwidth is needed, release
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* bandwidth request.
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*/
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void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
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{
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struct dpu_crtc *dpu_crtc;
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struct dpu_kms *kms;
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if (!crtc) {
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DPU_ERROR("invalid crtc\n");
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return;
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}
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kms = _dpu_crtc_get_kms(crtc);
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2019-09-06 19:23:43 +00:00
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if (!kms->catalog) {
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2018-06-27 19:26:09 +00:00
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DPU_ERROR("invalid kms\n");
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return;
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}
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dpu_crtc = to_dpu_crtc(crtc);
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2019-08-20 23:12:28 +00:00
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if (atomic_dec_return(&kms->bandwidth_ref) > 0)
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2018-06-27 19:26:09 +00:00
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return;
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/* Release the bandwidth */
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if (kms->perf.enable_bw_release) {
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trace_dpu_cmd_release_bw(crtc->base.id);
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2021-04-30 19:31:04 +00:00
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DRM_DEBUG_ATOMIC("Release BW crtc=%d\n", crtc->base.id);
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2019-06-18 20:24:09 +00:00
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dpu_crtc->cur_perf.bw_ctl = 0;
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_dpu_core_perf_crtc_update_bus(kms, crtc);
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2018-06-27 19:26:09 +00:00
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}
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}
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static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
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{
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2023-07-30 01:00:55 +00:00
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u64 clk_rate;
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2018-06-27 19:26:09 +00:00
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struct drm_crtc *crtc;
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struct dpu_crtc_state *dpu_cstate;
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2023-07-30 01:00:55 +00:00
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if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
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return kms->perf.fix_core_clk_rate;
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if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM)
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return kms->perf.max_core_clk_rate;
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2018-06-27 19:26:09 +00:00
|
|
|
drm_for_each_crtc(crtc, kms->dev) {
|
2018-12-03 22:47:16 +00:00
|
|
|
if (crtc->enabled) {
|
2018-06-27 19:26:09 +00:00
|
|
|
dpu_cstate = to_dpu_crtc_state(crtc->state);
|
|
|
|
clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
|
|
|
|
clk_rate);
|
2022-02-17 05:55:25 +00:00
|
|
|
clk_rate = clk_round_rate(kms->perf.core_clk,
|
2018-06-27 19:26:09 +00:00
|
|
|
clk_rate);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return clk_rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
|
|
|
|
int params_changed, bool stop_req)
|
|
|
|
{
|
|
|
|
struct dpu_core_perf_params *new, *old;
|
2019-06-18 20:24:09 +00:00
|
|
|
bool update_bus = false, update_clk = false;
|
2018-06-27 19:26:09 +00:00
|
|
|
u64 clk_rate = 0;
|
|
|
|
struct dpu_crtc *dpu_crtc;
|
|
|
|
struct dpu_crtc_state *dpu_cstate;
|
|
|
|
struct dpu_kms *kms;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!crtc) {
|
|
|
|
DPU_ERROR("invalid crtc\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
kms = _dpu_crtc_get_kms(crtc);
|
2019-09-06 19:23:43 +00:00
|
|
|
if (!kms->catalog) {
|
2018-06-27 19:26:09 +00:00
|
|
|
DPU_ERROR("invalid kms\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dpu_crtc = to_dpu_crtc(crtc);
|
|
|
|
dpu_cstate = to_dpu_crtc_state(crtc->state);
|
|
|
|
|
2021-04-30 19:31:04 +00:00
|
|
|
DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n",
|
2018-06-27 19:26:09 +00:00
|
|
|
crtc->base.id, stop_req, kms->perf.core_clk_rate);
|
|
|
|
|
|
|
|
old = &dpu_crtc->cur_perf;
|
|
|
|
new = &dpu_cstate->new_perf;
|
|
|
|
|
2018-12-03 22:47:16 +00:00
|
|
|
if (crtc->enabled && !stop_req) {
|
2019-06-18 20:24:09 +00:00
|
|
|
/*
|
|
|
|
* cases for bus bandwidth update.
|
|
|
|
* 1. new bandwidth vote - "ab or ib vote" is higher
|
|
|
|
* than current vote for update request.
|
|
|
|
* 2. new bandwidth vote - "ab or ib vote" is lower
|
|
|
|
* than current vote at end of commit or stop.
|
|
|
|
*/
|
|
|
|
if ((params_changed && ((new->bw_ctl > old->bw_ctl) ||
|
|
|
|
(new->max_per_pipe_ib > old->max_per_pipe_ib))) ||
|
|
|
|
(!params_changed && ((new->bw_ctl < old->bw_ctl) ||
|
|
|
|
(new->max_per_pipe_ib < old->max_per_pipe_ib)))) {
|
2021-04-30 19:31:04 +00:00
|
|
|
DRM_DEBUG_ATOMIC("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
|
2019-06-18 20:24:09 +00:00
|
|
|
crtc->base.id, params_changed,
|
|
|
|
new->bw_ctl, old->bw_ctl);
|
|
|
|
old->bw_ctl = new->bw_ctl;
|
|
|
|
old->max_per_pipe_ib = new->max_per_pipe_ib;
|
|
|
|
update_bus = true;
|
2018-06-27 19:26:09 +00:00
|
|
|
}
|
|
|
|
|
2023-07-30 01:00:56 +00:00
|
|
|
if ((params_changed && new->core_clk_rate > old->core_clk_rate) ||
|
|
|
|
(!params_changed && new->core_clk_rate < old->core_clk_rate)) {
|
2018-06-27 19:26:09 +00:00
|
|
|
old->core_clk_rate = new->core_clk_rate;
|
2019-06-18 20:24:09 +00:00
|
|
|
update_clk = true;
|
2018-06-27 19:26:09 +00:00
|
|
|
}
|
|
|
|
} else {
|
2021-04-30 19:31:04 +00:00
|
|
|
DRM_DEBUG_ATOMIC("crtc=%d disable\n", crtc->base.id);
|
2018-06-27 19:26:09 +00:00
|
|
|
memset(old, 0, sizeof(*old));
|
2019-06-18 20:24:09 +00:00
|
|
|
update_bus = true;
|
|
|
|
update_clk = true;
|
2018-06-27 19:26:09 +00:00
|
|
|
}
|
2019-06-18 20:24:09 +00:00
|
|
|
|
|
|
|
trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl,
|
|
|
|
new->core_clk_rate, stop_req, update_bus, update_clk);
|
|
|
|
|
|
|
|
if (update_bus) {
|
|
|
|
ret = _dpu_core_perf_crtc_update_bus(kms, crtc);
|
|
|
|
if (ret) {
|
|
|
|
DPU_ERROR("crtc-%d: failed to update bus bw vote\n",
|
|
|
|
crtc->base.id);
|
|
|
|
return ret;
|
2018-06-27 19:26:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Update the clock after bandwidth vote to ensure
|
|
|
|
* bandwidth is available before clock rate is increased.
|
|
|
|
*/
|
|
|
|
if (update_clk) {
|
|
|
|
clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
|
|
|
|
|
2023-07-30 01:00:55 +00:00
|
|
|
DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
|
|
|
|
|
2018-06-27 19:26:09 +00:00
|
|
|
trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate);
|
|
|
|
|
2022-02-17 05:55:25 +00:00
|
|
|
clk_rate = min(clk_rate, kms->perf.max_core_clk_rate);
|
|
|
|
ret = dev_pm_opp_set_rate(&kms->pdev->dev, clk_rate);
|
2018-06-27 19:26:09 +00:00
|
|
|
if (ret) {
|
2022-02-17 05:55:25 +00:00
|
|
|
DPU_ERROR("failed to set core clock rate %llu\n", clk_rate);
|
2018-06-27 19:26:09 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
kms->perf.core_clk_rate = clk_rate;
|
2021-04-30 19:31:04 +00:00
|
|
|
DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate);
|
2018-06-27 19:26:09 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
|
|
|
|
static ssize_t _dpu_core_perf_mode_write(struct file *file,
|
|
|
|
const char __user *user_buf, size_t count, loff_t *ppos)
|
|
|
|
{
|
|
|
|
struct dpu_core_perf *perf = file->private_data;
|
|
|
|
u32 perf_mode = 0;
|
2018-12-03 22:47:21 +00:00
|
|
|
int ret;
|
2018-06-27 19:26:09 +00:00
|
|
|
|
2018-12-03 22:47:21 +00:00
|
|
|
ret = kstrtouint_from_user(user_buf, count, 0, &perf_mode);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2018-06-27 19:26:09 +00:00
|
|
|
|
|
|
|
if (perf_mode >= DPU_PERF_MODE_MAX)
|
2018-12-03 22:47:21 +00:00
|
|
|
return -EINVAL;
|
2018-06-27 19:26:09 +00:00
|
|
|
|
|
|
|
if (perf_mode == DPU_PERF_MODE_FIXED) {
|
|
|
|
DRM_INFO("fix performance mode\n");
|
|
|
|
} else if (perf_mode == DPU_PERF_MODE_MINIMUM) {
|
|
|
|
/* run the driver with max clk and BW vote */
|
|
|
|
DRM_INFO("minimum performance mode\n");
|
|
|
|
} else if (perf_mode == DPU_PERF_MODE_NORMAL) {
|
|
|
|
/* reset the perf tune params to 0 */
|
|
|
|
DRM_INFO("normal performance mode\n");
|
|
|
|
}
|
|
|
|
perf->perf_tune.mode = perf_mode;
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t _dpu_core_perf_mode_read(struct file *file,
|
|
|
|
char __user *buff, size_t count, loff_t *ppos)
|
|
|
|
{
|
|
|
|
struct dpu_core_perf *perf = file->private_data;
|
2018-12-03 22:47:21 +00:00
|
|
|
int len;
|
|
|
|
char buf[128];
|
2018-06-27 19:26:09 +00:00
|
|
|
|
2018-12-03 22:47:21 +00:00
|
|
|
len = scnprintf(buf, sizeof(buf),
|
2023-07-30 01:00:55 +00:00
|
|
|
"mode %d\n",
|
|
|
|
perf->perf_tune.mode);
|
2018-06-27 19:26:09 +00:00
|
|
|
|
2018-12-03 22:47:21 +00:00
|
|
|
return simple_read_from_buffer(buff, count, ppos, buf, len);
|
2018-06-27 19:26:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations dpu_core_perf_mode_fops = {
|
|
|
|
.open = simple_open,
|
|
|
|
.read = _dpu_core_perf_mode_read,
|
|
|
|
.write = _dpu_core_perf_mode_write,
|
|
|
|
};
|
|
|
|
|
2018-12-03 22:47:21 +00:00
|
|
|
int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
|
2018-06-27 19:26:09 +00:00
|
|
|
{
|
2018-12-03 22:47:21 +00:00
|
|
|
struct dpu_core_perf *perf = &dpu_kms->perf;
|
2022-06-02 20:24:46 +00:00
|
|
|
const struct dpu_mdss_cfg *catalog = perf->catalog;
|
2018-12-03 22:47:21 +00:00
|
|
|
struct dentry *entry;
|
2018-06-27 19:26:09 +00:00
|
|
|
|
2018-12-03 22:47:21 +00:00
|
|
|
entry = debugfs_create_dir("core_perf", parent);
|
2018-06-27 19:26:09 +00:00
|
|
|
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u64("max_core_clk_rate", 0600, entry,
|
2018-06-27 19:26:09 +00:00
|
|
|
&perf->max_core_clk_rate);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u64("core_clk_rate", 0600, entry,
|
2018-06-27 19:26:09 +00:00
|
|
|
&perf->core_clk_rate);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u32("enable_bw_release", 0600, entry,
|
2018-06-27 19:26:09 +00:00
|
|
|
(u32 *)&perf->enable_bw_release);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u32("threshold_low", 0600, entry,
|
2022-06-02 20:24:44 +00:00
|
|
|
(u32 *)&catalog->perf->max_bw_low);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u32("threshold_high", 0600, entry,
|
2022-06-02 20:24:44 +00:00
|
|
|
(u32 *)&catalog->perf->max_bw_high);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u32("min_core_ib", 0600, entry,
|
2022-06-02 20:24:44 +00:00
|
|
|
(u32 *)&catalog->perf->min_core_ib);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u32("min_llcc_ib", 0600, entry,
|
2022-06-02 20:24:44 +00:00
|
|
|
(u32 *)&catalog->perf->min_llcc_ib);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u32("min_dram_ib", 0600, entry,
|
2022-06-02 20:24:44 +00:00
|
|
|
(u32 *)&catalog->perf->min_dram_ib);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_file("perf_mode", 0600, entry,
|
2018-06-27 19:26:09 +00:00
|
|
|
(u32 *)perf, &dpu_core_perf_mode_fops);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u64("fix_core_clk_rate", 0600, entry,
|
2018-06-27 19:26:09 +00:00
|
|
|
&perf->fix_core_clk_rate);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u64("fix_core_ib_vote", 0600, entry,
|
2018-06-27 19:26:09 +00:00
|
|
|
&perf->fix_core_ib_vote);
|
2018-12-03 22:47:21 +00:00
|
|
|
debugfs_create_u64("fix_core_ab_vote", 0600, entry,
|
2018-06-27 19:26:09 +00:00
|
|
|
&perf->fix_core_ab_vote);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void dpu_core_perf_destroy(struct dpu_core_perf *perf)
|
|
|
|
{
|
|
|
|
if (!perf) {
|
|
|
|
DPU_ERROR("invalid parameters\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
perf->max_core_clk_rate = 0;
|
|
|
|
perf->core_clk = NULL;
|
|
|
|
perf->catalog = NULL;
|
|
|
|
perf->dev = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dpu_core_perf_init(struct dpu_core_perf *perf,
|
|
|
|
struct drm_device *dev,
|
2022-06-02 20:24:46 +00:00
|
|
|
const struct dpu_mdss_cfg *catalog,
|
2022-02-17 05:55:25 +00:00
|
|
|
struct clk *core_clk)
|
2018-06-27 19:26:09 +00:00
|
|
|
{
|
|
|
|
perf->dev = dev;
|
|
|
|
perf->catalog = catalog;
|
|
|
|
perf->core_clk = core_clk;
|
|
|
|
|
2022-02-17 05:55:25 +00:00
|
|
|
perf->max_core_clk_rate = clk_get_rate(core_clk);
|
2018-06-27 19:26:09 +00:00
|
|
|
if (!perf->max_core_clk_rate) {
|
|
|
|
DPU_DEBUG("optional max core clk rate, use default\n");
|
|
|
|
perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|