100 lines
1.9 KiB
Plaintext
100 lines
1.9 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* NXP S32G2 SoC family
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*
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* Copyright (c) 2021 SUSE LLC
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "nxp,s32g2";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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firmware {
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x80000000>;
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gic: interrupt-controller@50800000 {
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compatible = "arm,gic-v3";
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reg = <0x50800000 0x10000>,
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<0x50880000 0x80000>,
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<0x50400000 0x2000>,
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<0x50410000 0x2000>,
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<0x50420000 0x2000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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