2020-04-22 19:57:36 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This file contains definitions from Hyper-V Hypervisor Top-Level Functional
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* Specification (TLFS):
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* https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
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*/
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#ifndef _ASM_GENERIC_HYPERV_TLFS_H
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#define _ASM_GENERIC_HYPERV_TLFS_H
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#include <linux/types.h>
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#include <linux/bits.h>
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#include <linux/time64.h>
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/*
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* While not explicitly listed in the TLFS, Hyper-V always runs with a page size
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* of 4096. These definitions are used when communicating with Hyper-V using
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* guest physical pages and guest physical page addresses, since the guest page
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* size may not be 4096 on all architectures.
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*/
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#define HV_HYP_PAGE_SHIFT 12
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#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)
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#define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))
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/*
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* Hyper-V provides two categories of flags relevant to guest VMs. The
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* "Features" category indicates specific functionality that is available
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* to guests on this particular instance of Hyper-V. The "Features"
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* are presented in four groups, each of which is 32 bits. The group A
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* and B definitions are common across architectures and are listed here.
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* However, not all flags are relevant on all architectures.
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*
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* Groups C and D vary across architectures and are listed in the
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* architecture specific portion of hyperv-tlfs.h. Some of these flags exist
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* on multiple architectures, but the bit positions are different so they
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* cannot appear in the generic portion of hyperv-tlfs.h.
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*
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* The "Enlightenments" category provides recommendations on whether to use
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* specific enlightenments that are available. The Enlighenments are a single
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* group of 32 bits, but they vary across architectures and are listed in
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* the architecture specific portion of hyperv-tlfs.h.
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*/
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/*
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* Group A Features.
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*/
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/* VP Runtime register available */
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#define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0)
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/* Partition Reference Counter available*/
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#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1)
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/* Basic SynIC register available */
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#define HV_MSR_SYNIC_AVAILABLE BIT(2)
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/* Synthetic Timer registers available */
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#define HV_MSR_SYNTIMER_AVAILABLE BIT(3)
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/* Virtual APIC assist and VP assist page registers available */
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#define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4)
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/* Hypercall and Guest OS ID registers available*/
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#define HV_MSR_HYPERCALL_AVAILABLE BIT(5)
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/* Access virtual processor index register available*/
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#define HV_MSR_VP_INDEX_AVAILABLE BIT(6)
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/* Virtual system reset register available*/
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#define HV_MSR_RESET_AVAILABLE BIT(7)
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/* Access statistics page registers available */
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#define HV_MSR_STAT_PAGES_AVAILABLE BIT(8)
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/* Partition reference TSC register is available */
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#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9)
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/* Partition Guest IDLE register is available */
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#define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10)
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/* Partition local APIC and TSC frequency registers available */
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#define HV_ACCESS_FREQUENCY_MSRS BIT(11)
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/* AccessReenlightenmentControls privilege */
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#define HV_ACCESS_REENLIGHTENMENT BIT(13)
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/* AccessTscInvariantControls privilege */
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#define HV_ACCESS_TSC_INVARIANT BIT(15)
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/*
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* Group B features.
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*/
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#define HV_CREATE_PARTITIONS BIT(0)
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#define HV_ACCESS_PARTITION_ID BIT(1)
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#define HV_ACCESS_MEMORY_POOL BIT(2)
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#define HV_ADJUST_MESSAGE_BUFFERS BIT(3)
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#define HV_POST_MESSAGES BIT(4)
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#define HV_SIGNAL_EVENTS BIT(5)
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#define HV_CREATE_PORT BIT(6)
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#define HV_CONNECT_PORT BIT(7)
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#define HV_ACCESS_STATS BIT(8)
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#define HV_DEBUGGING BIT(11)
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2021-02-03 15:04:20 +00:00
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#define HV_CPU_MANAGEMENT BIT(12)
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2021-03-23 18:47:16 +00:00
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#define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20)
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2021-02-01 14:48:11 +00:00
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#define HV_ISOLATION BIT(22)
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2020-04-22 19:57:36 +00:00
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/*
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* TSC page layout.
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*/
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struct ms_hyperv_tsc_page {
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volatile u32 tsc_sequence;
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u32 reserved1;
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volatile u64 tsc_scale;
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volatile s64 tsc_offset;
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} __packed;
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/*
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* The guest OS needs to register the guest ID with the hypervisor.
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* The guest ID is a 64 bit entity and the structure of this ID is
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* specified in the Hyper-V specification:
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*
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* msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx
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*
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* While the current guideline does not specify how Linux guest ID(s)
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* need to be generated, our plan is to publish the guidelines for
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* Linux and other guest operating systems that currently are hosted
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* on Hyper-V. The implementation here conforms to this yet
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* unpublished guidelines.
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*
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*
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* Bit(s)
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* 63 - Indicates if the OS is Open Source or not; 1 is Open Source
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* 62:56 - Os Type; Linux is 0x100
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* 55:48 - Distro specific identification
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* 47:16 - Linux kernel version number
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* 15:0 - Distro specific identification
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*
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*
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*/
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#define HV_LINUX_VENDOR_ID 0x8100
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/*
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* Crash notification flags.
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*/
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#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)
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#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63)
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/* Declare the various hypercall operations. */
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
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#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
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#define HVCALL_SEND_IPI 0x000b
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
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#define HVCALL_SEND_IPI_EX 0x0015
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2021-02-03 15:04:25 +00:00
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#define HVCALL_GET_PARTITION_ID 0x0046
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2021-02-03 15:04:28 +00:00
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#define HVCALL_DEPOSIT_MEMORY 0x0048
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#define HVCALL_CREATE_VP 0x004e
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2020-04-22 19:57:37 +00:00
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#define HVCALL_GET_VP_REGISTERS 0x0050
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#define HVCALL_SET_VP_REGISTERS 0x0051
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2020-04-22 19:57:36 +00:00
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#define HVCALL_POST_MESSAGE 0x005c
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#define HVCALL_SIGNAL_EVENT 0x005d
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ARM:
- Move the arch-specific code into arch/arm64/kvm
- Start the post-32bit cleanup
- Cherry-pick a few non-invasive pre-NV patches
x86:
- Rework of TLB flushing
- Rework of event injection, especially with respect to nested virtualization
- Nested AMD event injection facelift, building on the rework of generic code
and fixing a lot of corner cases
- Nested AMD live migration support
- Optimization for TSC deadline MSR writes and IPIs
- Various cleanups
- Asynchronous page fault cleanups (from tglx, common topic branch with tip tree)
- Interrupt-based delivery of asynchronous "page ready" events (host side)
- Hyper-V MSRs and hypercalls for guest debugging
- VMX preemption timer fixes
s390:
- Cleanups
Generic:
- switch vCPU thread wakeup from swait to rcuwait
The other architectures, and the guest side of the asynchronous page fault
work, will come next week.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Paolo Bonzini:
"ARM:
- Move the arch-specific code into arch/arm64/kvm
- Start the post-32bit cleanup
- Cherry-pick a few non-invasive pre-NV patches
x86:
- Rework of TLB flushing
- Rework of event injection, especially with respect to nested
virtualization
- Nested AMD event injection facelift, building on the rework of
generic code and fixing a lot of corner cases
- Nested AMD live migration support
- Optimization for TSC deadline MSR writes and IPIs
- Various cleanups
- Asynchronous page fault cleanups (from tglx, common topic branch
with tip tree)
- Interrupt-based delivery of asynchronous "page ready" events (host
side)
- Hyper-V MSRs and hypercalls for guest debugging
- VMX preemption timer fixes
s390:
- Cleanups
Generic:
- switch vCPU thread wakeup from swait to rcuwait
The other architectures, and the guest side of the asynchronous page
fault work, will come next week"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (256 commits)
KVM: selftests: fix rdtsc() for vmx_tsc_adjust_test
KVM: check userspace_addr for all memslots
KVM: selftests: update hyperv_cpuid with SynDBG tests
x86/kvm/hyper-v: Add support for synthetic debugger via hypercalls
x86/kvm/hyper-v: enable hypercalls regardless of hypercall page
x86/kvm/hyper-v: Add support for synthetic debugger interface
x86/hyper-v: Add synthetic debugger definitions
KVM: selftests: VMX preemption timer migration test
KVM: nVMX: Fix VMX preemption timer migration
x86/kvm/hyper-v: Explicitly align hcall param for kvm_hyperv_exit
KVM: x86/pmu: Support full width counting
KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in
KVM: x86: announce KVM_FEATURE_ASYNC_PF_INT
KVM: x86: acknowledgment mechanism for async pf page ready notifications
KVM: x86: interrupt based APF 'page ready' event delivery
KVM: introduce kvm_read_guest_offset_cached()
KVM: rename kvm_arch_can_inject_async_page_present() to kvm_arch_can_dequeue_async_page_present()
KVM: x86: extend struct kvm_vcpu_pv_apf_data with token info
Revert "KVM: async_pf: Fix #DF due to inject "Page not Present" and "Page Ready" exceptions simultaneously"
KVM: VMX: Replace zero-length array with flexible-array
...
2020-06-03 22:13:47 +00:00
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#define HVCALL_POST_DEBUG_DATA 0x0069
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#define HVCALL_RETRIEVE_DEBUG_DATA 0x006a
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#define HVCALL_RESET_DEBUG_SESSION 0x006b
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2021-02-03 15:04:28 +00:00
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#define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076
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2021-02-03 15:04:33 +00:00
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#define HVCALL_MAP_DEVICE_INTERRUPT 0x007c
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#define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d
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2020-04-22 19:57:36 +00:00
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#define HVCALL_RETARGET_INTERRUPT 0x007e
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#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
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#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
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2021-10-25 12:21:08 +00:00
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#define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db
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2020-04-22 19:57:36 +00:00
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2021-03-23 18:47:16 +00:00
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/* Extended hypercalls */
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#define HV_EXT_CALL_QUERY_CAPABILITIES 0x8001
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#define HV_EXT_CALL_MEMORY_HEAT_HINT 0x8003
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2020-04-22 19:57:36 +00:00
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#define HV_FLUSH_ALL_PROCESSORS BIT(0)
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#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
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#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
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#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
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2021-03-23 18:47:16 +00:00
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/* Extended capability bits */
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#define HV_EXT_CAPABILITY_MEMORY_COLD_DISCARD_HINT BIT(8)
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2020-04-22 19:57:36 +00:00
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enum HV_GENERIC_SET_FORMAT {
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HV_GENERIC_SET_SPARSE_4K,
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HV_GENERIC_SET_ALL,
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};
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#define HV_PARTITION_ID_SELF ((u64)-1)
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#define HV_VP_INDEX_SELF ((u32)-2)
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#define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0)
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#define HV_HYPERCALL_FAST_BIT BIT(16)
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#define HV_HYPERCALL_VARHEAD_OFFSET 17
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2021-12-07 22:09:20 +00:00
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#define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17)
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2021-12-07 22:09:26 +00:00
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#define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27)
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2020-04-22 19:57:36 +00:00
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#define HV_HYPERCALL_REP_COMP_OFFSET 32
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#define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32)
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#define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32)
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2021-12-07 22:09:26 +00:00
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#define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44)
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2020-04-22 19:57:36 +00:00
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#define HV_HYPERCALL_REP_START_OFFSET 48
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#define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48)
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2021-12-07 22:09:26 +00:00
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#define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60)
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#define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \
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HV_HYPERCALL_RSVD1_MASK | \
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HV_HYPERCALL_RSVD2_MASK)
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2020-04-22 19:57:36 +00:00
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/* hypercall status code */
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#define HV_STATUS_SUCCESS 0
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#define HV_STATUS_INVALID_HYPERCALL_CODE 2
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#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
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#define HV_STATUS_INVALID_ALIGNMENT 4
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#define HV_STATUS_INVALID_PARAMETER 5
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2021-05-21 09:51:35 +00:00
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#define HV_STATUS_ACCESS_DENIED 6
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ARM:
- Move the arch-specific code into arch/arm64/kvm
- Start the post-32bit cleanup
- Cherry-pick a few non-invasive pre-NV patches
x86:
- Rework of TLB flushing
- Rework of event injection, especially with respect to nested virtualization
- Nested AMD event injection facelift, building on the rework of generic code
and fixing a lot of corner cases
- Nested AMD live migration support
- Optimization for TSC deadline MSR writes and IPIs
- Various cleanups
- Asynchronous page fault cleanups (from tglx, common topic branch with tip tree)
- Interrupt-based delivery of asynchronous "page ready" events (host side)
- Hyper-V MSRs and hypercalls for guest debugging
- VMX preemption timer fixes
s390:
- Cleanups
Generic:
- switch vCPU thread wakeup from swait to rcuwait
The other architectures, and the guest side of the asynchronous page fault
work, will come next week.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Paolo Bonzini:
"ARM:
- Move the arch-specific code into arch/arm64/kvm
- Start the post-32bit cleanup
- Cherry-pick a few non-invasive pre-NV patches
x86:
- Rework of TLB flushing
- Rework of event injection, especially with respect to nested
virtualization
- Nested AMD event injection facelift, building on the rework of
generic code and fixing a lot of corner cases
- Nested AMD live migration support
- Optimization for TSC deadline MSR writes and IPIs
- Various cleanups
- Asynchronous page fault cleanups (from tglx, common topic branch
with tip tree)
- Interrupt-based delivery of asynchronous "page ready" events (host
side)
- Hyper-V MSRs and hypercalls for guest debugging
- VMX preemption timer fixes
s390:
- Cleanups
Generic:
- switch vCPU thread wakeup from swait to rcuwait
The other architectures, and the guest side of the asynchronous page
fault work, will come next week"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (256 commits)
KVM: selftests: fix rdtsc() for vmx_tsc_adjust_test
KVM: check userspace_addr for all memslots
KVM: selftests: update hyperv_cpuid with SynDBG tests
x86/kvm/hyper-v: Add support for synthetic debugger via hypercalls
x86/kvm/hyper-v: enable hypercalls regardless of hypercall page
x86/kvm/hyper-v: Add support for synthetic debugger interface
x86/hyper-v: Add synthetic debugger definitions
KVM: selftests: VMX preemption timer migration test
KVM: nVMX: Fix VMX preemption timer migration
x86/kvm/hyper-v: Explicitly align hcall param for kvm_hyperv_exit
KVM: x86/pmu: Support full width counting
KVM: x86/pmu: Tweak kvm_pmu_get_msr to pass 'struct msr_data' in
KVM: x86: announce KVM_FEATURE_ASYNC_PF_INT
KVM: x86: acknowledgment mechanism for async pf page ready notifications
KVM: x86: interrupt based APF 'page ready' event delivery
KVM: introduce kvm_read_guest_offset_cached()
KVM: rename kvm_arch_can_inject_async_page_present() to kvm_arch_can_dequeue_async_page_present()
KVM: x86: extend struct kvm_vcpu_pv_apf_data with token info
Revert "KVM: async_pf: Fix #DF due to inject "Page not Present" and "Page Ready" exceptions simultaneously"
KVM: VMX: Replace zero-length array with flexible-array
...
2020-06-03 22:13:47 +00:00
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#define HV_STATUS_OPERATION_DENIED 8
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2020-04-22 19:57:36 +00:00
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#define HV_STATUS_INSUFFICIENT_MEMORY 11
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#define HV_STATUS_INVALID_PORT_ID 17
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#define HV_STATUS_INVALID_CONNECTION_ID 18
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#define HV_STATUS_INSUFFICIENT_BUFFERS 19
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/*
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* The Hyper-V TimeRefCount register and the TSC
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* page provide a guest VM clock with 100ns tick rate
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*/
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#define HV_CLOCK_HZ (NSEC_PER_SEC/100)
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/* Define the number of synthetic interrupt sources. */
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#define HV_SYNIC_SINT_COUNT (16)
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/* Define the expected SynIC version. */
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#define HV_SYNIC_VERSION_1 (0x1)
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/* Valid SynIC vectors are 16-255. */
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#define HV_SYNIC_FIRST_VALID_VECTOR (16)
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#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
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#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
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#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
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#define HV_SYNIC_SINT_MASKED (1ULL << 16)
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#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
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#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
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#define HV_SYNIC_STIMER_COUNT (4)
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/* Define synthetic interrupt controller message constants. */
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#define HV_MESSAGE_SIZE (256)
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#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
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#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
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2021-03-02 21:38:14 +00:00
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/*
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* Define hypervisor message types. Some of the message types
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* are x86/x64 specific, but there's no good way to separate
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* them out into the arch-specific version of hyperv-tlfs.h
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* because C doesn't provide a way to extend enum types.
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* Keeping them all in the arch neutral hyperv-tlfs.h seems
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* the least messy compromise.
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*/
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enum hv_message_type {
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HVMSG_NONE = 0x00000000,
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/* Memory access messages. */
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HVMSG_UNMAPPED_GPA = 0x80000000,
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HVMSG_GPA_INTERCEPT = 0x80000001,
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/* Timer notification messages. */
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HVMSG_TIMER_EXPIRED = 0x80000010,
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/* Error messages. */
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HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
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HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
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HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
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/* Trace buffer complete messages. */
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HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
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/* Platform-specific processor intercept messages. */
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HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
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HVMSG_X64_MSR_INTERCEPT = 0x80010001,
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HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
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HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
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HVMSG_X64_APIC_EOI = 0x80010004,
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HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
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};
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2020-04-22 19:57:36 +00:00
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/* Define synthetic interrupt controller message flags. */
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union hv_message_flags {
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__u8 asu8;
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struct {
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__u8 msg_pending:1;
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__u8 reserved:7;
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} __packed;
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};
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/* Define port identifier type. */
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union hv_port_id {
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__u32 asu32;
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struct {
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__u32 id:24;
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__u32 reserved:8;
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} __packed u;
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};
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/* Define synthetic interrupt controller message header. */
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struct hv_message_header {
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__u32 message_type;
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__u8 payload_size;
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union hv_message_flags message_flags;
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__u8 reserved[2];
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union {
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__u64 sender;
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union hv_port_id port;
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};
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} __packed;
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/* Define synthetic interrupt controller message format. */
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struct hv_message {
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struct hv_message_header header;
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union {
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__u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
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} u;
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} __packed;
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/* Define the synthetic interrupt message page layout. */
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struct hv_message_page {
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struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
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} __packed;
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/* Define timer message payload structure. */
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struct hv_timer_message_payload {
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__u32 timer_index;
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__u32 reserved;
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__u64 expiration_time; /* When the timer expired */
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__u64 delivery_time; /* When the message was delivered */
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} __packed;
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/* Define synthetic interrupt controller flag constants. */
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#define HV_EVENT_FLAGS_COUNT (256 * 8)
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#define HV_EVENT_FLAGS_LONG_COUNT (256 / sizeof(unsigned long))
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/*
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* Synthetic timer configuration.
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*/
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union hv_stimer_config {
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u64 as_uint64;
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struct {
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u64 enable:1;
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u64 periodic:1;
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u64 lazy:1;
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u64 auto_enable:1;
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u64 apic_vector:8;
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u64 direct_mode:1;
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u64 reserved_z0:3;
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u64 sintx:4;
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u64 reserved_z1:44;
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} __packed;
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};
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/* Define the synthetic interrupt controller event flags format. */
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union hv_synic_event_flags {
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unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT];
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};
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/* Define SynIC control register. */
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union hv_synic_scontrol {
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u64 as_uint64;
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struct {
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u64 enable:1;
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u64 reserved:63;
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} __packed;
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};
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/* Define synthetic interrupt source. */
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union hv_synic_sint {
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u64 as_uint64;
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struct {
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u64 vector:8;
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u64 reserved1:8;
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u64 masked:1;
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u64 auto_eoi:1;
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u64 polling:1;
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u64 reserved2:45;
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} __packed;
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};
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/* Define the format of the SIMP register */
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union hv_synic_simp {
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u64 as_uint64;
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struct {
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u64 simp_enabled:1;
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u64 preserved:11;
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u64 base_simp_gpa:52;
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} __packed;
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};
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/* Define the format of the SIEFP register */
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union hv_synic_siefp {
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u64 as_uint64;
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struct {
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u64 siefp_enabled:1;
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u64 preserved:11;
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u64 base_siefp_gpa:52;
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} __packed;
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};
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struct hv_vpset {
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u64 format;
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u64 valid_bank_mask;
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u64 bank_contents[];
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} __packed;
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/* HvCallSendSyntheticClusterIpi hypercall */
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struct hv_send_ipi {
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u32 vector;
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u32 reserved;
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u64 cpu_mask;
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} __packed;
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/* HvCallSendSyntheticClusterIpiEx hypercall */
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struct hv_send_ipi_ex {
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u32 vector;
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u32 reserved;
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struct hv_vpset vp_set;
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} __packed;
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/* HvFlushGuestPhysicalAddressSpace hypercalls */
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struct hv_guest_mapping_flush {
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u64 address_space;
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u64 flags;
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} __packed;
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/*
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* HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited
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* by the bitwidth of "additional_pages" in union hv_gpa_page_range.
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*/
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#define HV_MAX_FLUSH_PAGES (2048)
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2021-03-23 18:47:16 +00:00
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#define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0
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#define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1
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2020-04-22 19:57:36 +00:00
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2021-03-23 18:47:16 +00:00
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/* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */
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2020-04-22 19:57:36 +00:00
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union hv_gpa_page_range {
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u64 address_space;
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struct {
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u64 additional_pages:11;
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u64 largepage:1;
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u64 basepfn:52;
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} page;
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2021-03-23 18:47:16 +00:00
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struct {
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u64 reserved:12;
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u64 page_size:1;
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u64 reserved1:8;
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u64 base_large_pfn:43;
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};
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2020-04-22 19:57:36 +00:00
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};
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/*
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* All input flush parameters should be in single page. The max flush
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* count is equal with how many entries of union hv_gpa_page_range can
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* be populated into the input parameter page.
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*/
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#define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \
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sizeof(union hv_gpa_page_range))
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struct hv_guest_mapping_flush_list {
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u64 address_space;
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u64 flags;
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union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT];
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};
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/* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */
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struct hv_tlb_flush {
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u64 address_space;
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u64 flags;
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u64 processor_mask;
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u64 gva_list[];
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} __packed;
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/* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
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struct hv_tlb_flush_ex {
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u64 address_space;
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u64 flags;
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struct hv_vpset hv_vp_set;
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u64 gva_list[];
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} __packed;
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2021-02-03 15:04:25 +00:00
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/* HvGetPartitionId hypercall (output only) */
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struct hv_get_partition_id {
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u64 partition_id;
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} __packed;
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2021-02-03 15:04:28 +00:00
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/* HvDepositMemory hypercall */
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struct hv_deposit_memory {
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u64 partition_id;
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u64 gpa_page_list[];
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} __packed;
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struct hv_proximity_domain_flags {
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u32 proximity_preferred : 1;
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u32 reserved : 30;
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u32 proximity_info_valid : 1;
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} __packed;
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/* Not a union in windows but useful for zeroing */
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union hv_proximity_domain_info {
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struct {
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u32 domain_id;
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struct hv_proximity_domain_flags flags;
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};
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u64 as_uint64;
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} __packed;
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struct hv_lp_startup_status {
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u64 hv_status;
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u64 substatus1;
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u64 substatus2;
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u64 substatus3;
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u64 substatus4;
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u64 substatus5;
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u64 substatus6;
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} __packed;
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/* HvAddLogicalProcessor hypercall */
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struct hv_add_logical_processor_in {
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u32 lp_index;
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u32 apic_id;
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union hv_proximity_domain_info proximity_domain_info;
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u64 flags;
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} __packed;
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struct hv_add_logical_processor_out {
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struct hv_lp_startup_status startup_status;
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} __packed;
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enum HV_SUBNODE_TYPE
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{
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HvSubnodeAny = 0,
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HvSubnodeSocket = 1,
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HvSubnodeAmdNode = 2,
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HvSubnodeL3 = 3,
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HvSubnodeCount = 4,
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HvSubnodeInvalid = -1
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};
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/* HvCreateVp hypercall */
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struct hv_create_vp {
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u64 partition_id;
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u32 vp_index;
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u8 padding[3];
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u8 subnode_type;
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u64 subnode_id;
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union hv_proximity_domain_info proximity_domain_info;
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u64 flags;
|
|
|
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} __packed;
|
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|
2021-02-03 15:04:31 +00:00
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enum hv_interrupt_source {
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HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */
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HV_INTERRUPT_SOURCE_IOAPIC,
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};
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union hv_ioapic_rte {
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u64 as_uint64;
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struct {
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u32 vector:8;
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u32 delivery_mode:3;
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u32 destination_mode:1;
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u32 delivery_status:1;
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u32 interrupt_polarity:1;
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u32 remote_irr:1;
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u32 trigger_mode:1;
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u32 interrupt_mask:1;
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u32 reserved1:15;
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u32 reserved2:24;
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u32 destination_id:8;
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};
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struct {
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u32 low_uint32;
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|
|
u32 high_uint32;
|
|
|
|
};
|
|
|
|
} __packed;
|
|
|
|
|
2020-04-22 19:57:36 +00:00
|
|
|
struct hv_interrupt_entry {
|
2021-02-03 15:04:31 +00:00
|
|
|
u32 source;
|
2020-04-22 19:57:36 +00:00
|
|
|
u32 reserved1;
|
2021-02-03 15:04:31 +00:00
|
|
|
union {
|
|
|
|
union hv_msi_entry msi_entry;
|
|
|
|
union hv_ioapic_rte ioapic_rte;
|
|
|
|
};
|
2020-04-22 19:57:36 +00:00
|
|
|
} __packed;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* flags for hv_device_interrupt_target.flags
|
|
|
|
*/
|
|
|
|
#define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1
|
|
|
|
#define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2
|
|
|
|
|
|
|
|
struct hv_device_interrupt_target {
|
|
|
|
u32 vector;
|
|
|
|
u32 flags;
|
|
|
|
union {
|
|
|
|
u64 vp_mask;
|
|
|
|
struct hv_vpset vp_set;
|
|
|
|
};
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
struct hv_retarget_device_interrupt {
|
|
|
|
u64 partition_id; /* use "self" */
|
|
|
|
u64 device_id;
|
|
|
|
struct hv_interrupt_entry int_entry;
|
|
|
|
u64 reserved2;
|
|
|
|
struct hv_device_interrupt_target int_target;
|
|
|
|
} __packed __aligned(8);
|
|
|
|
|
2020-04-22 19:57:37 +00:00
|
|
|
|
|
|
|
/* HvGetVpRegisters hypercall input with variable size reg name list*/
|
|
|
|
struct hv_get_vp_registers_input {
|
|
|
|
struct {
|
|
|
|
u64 partitionid;
|
|
|
|
u32 vpindex;
|
|
|
|
u8 inputvtl;
|
|
|
|
u8 padding[3];
|
|
|
|
} header;
|
|
|
|
struct input {
|
|
|
|
u32 name0;
|
|
|
|
u32 name1;
|
|
|
|
} element[];
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
|
|
|
|
/* HvGetVpRegisters returns an array of these output elements */
|
|
|
|
struct hv_get_vp_registers_output {
|
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
u32 a;
|
|
|
|
u32 b;
|
|
|
|
u32 c;
|
|
|
|
u32 d;
|
|
|
|
} as32 __packed;
|
|
|
|
struct {
|
|
|
|
u64 low;
|
|
|
|
u64 high;
|
|
|
|
} as64 __packed;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
/* HvSetVpRegisters hypercall with variable size reg name/value list*/
|
|
|
|
struct hv_set_vp_registers_input {
|
|
|
|
struct {
|
|
|
|
u64 partitionid;
|
|
|
|
u32 vpindex;
|
|
|
|
u8 inputvtl;
|
|
|
|
u8 padding[3];
|
|
|
|
} header;
|
|
|
|
struct {
|
|
|
|
u32 name;
|
|
|
|
u32 padding1;
|
|
|
|
u64 padding2;
|
|
|
|
u64 valuelow;
|
|
|
|
u64 valuehigh;
|
|
|
|
} element[];
|
|
|
|
} __packed;
|
|
|
|
|
2021-02-03 15:04:32 +00:00
|
|
|
enum hv_device_type {
|
|
|
|
HV_DEVICE_TYPE_LOGICAL = 0,
|
|
|
|
HV_DEVICE_TYPE_PCI = 1,
|
|
|
|
HV_DEVICE_TYPE_IOAPIC = 2,
|
|
|
|
HV_DEVICE_TYPE_ACPI = 3,
|
|
|
|
};
|
|
|
|
|
|
|
|
typedef u16 hv_pci_rid;
|
|
|
|
typedef u16 hv_pci_segment;
|
|
|
|
typedef u64 hv_logical_device_id;
|
|
|
|
union hv_pci_bdf {
|
|
|
|
u16 as_uint16;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
u8 function:3;
|
|
|
|
u8 device:5;
|
|
|
|
u8 bus;
|
|
|
|
};
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
union hv_pci_bus_range {
|
|
|
|
u16 as_uint16;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
u8 subordinate_bus;
|
|
|
|
u8 secondary_bus;
|
|
|
|
};
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
union hv_device_id {
|
|
|
|
u64 as_uint64;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
u64 reserved0:62;
|
|
|
|
u64 device_type:2;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* HV_DEVICE_TYPE_LOGICAL */
|
|
|
|
struct {
|
|
|
|
u64 id:62;
|
|
|
|
u64 device_type:2;
|
|
|
|
} logical;
|
|
|
|
|
|
|
|
/* HV_DEVICE_TYPE_PCI */
|
|
|
|
struct {
|
|
|
|
union {
|
|
|
|
hv_pci_rid rid;
|
|
|
|
union hv_pci_bdf bdf;
|
|
|
|
};
|
|
|
|
|
|
|
|
hv_pci_segment segment;
|
|
|
|
union hv_pci_bus_range shadow_bus_range;
|
|
|
|
|
|
|
|
u16 phantom_function_bits:2;
|
|
|
|
u16 source_shadow:1;
|
|
|
|
|
|
|
|
u16 rsvdz0:11;
|
|
|
|
u16 device_type:2;
|
|
|
|
} pci;
|
|
|
|
|
|
|
|
/* HV_DEVICE_TYPE_IOAPIC */
|
|
|
|
struct {
|
|
|
|
u8 ioapic_id;
|
|
|
|
u8 rsvdz0;
|
|
|
|
u16 rsvdz1;
|
|
|
|
u16 rsvdz2;
|
|
|
|
|
|
|
|
u16 rsvdz3:14;
|
|
|
|
u16 device_type:2;
|
|
|
|
} ioapic;
|
|
|
|
|
|
|
|
/* HV_DEVICE_TYPE_ACPI */
|
|
|
|
struct {
|
|
|
|
u32 input_mapping_base;
|
|
|
|
u32 input_mapping_count:30;
|
|
|
|
u32 device_type:2;
|
|
|
|
} acpi;
|
|
|
|
} __packed;
|
|
|
|
|
2021-02-03 15:04:33 +00:00
|
|
|
enum hv_interrupt_trigger_mode {
|
|
|
|
HV_INTERRUPT_TRIGGER_MODE_EDGE = 0,
|
|
|
|
HV_INTERRUPT_TRIGGER_MODE_LEVEL = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct hv_device_interrupt_descriptor {
|
|
|
|
u32 interrupt_type;
|
|
|
|
u32 trigger_mode;
|
|
|
|
u32 vector_count;
|
|
|
|
u32 reserved;
|
|
|
|
struct hv_device_interrupt_target target;
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
struct hv_input_map_device_interrupt {
|
|
|
|
u64 partition_id;
|
|
|
|
u64 device_id;
|
|
|
|
u64 flags;
|
|
|
|
struct hv_interrupt_entry logical_interrupt_entry;
|
|
|
|
struct hv_device_interrupt_descriptor interrupt_descriptor;
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
struct hv_output_map_device_interrupt {
|
|
|
|
struct hv_interrupt_entry interrupt_entry;
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
struct hv_input_unmap_device_interrupt {
|
|
|
|
u64 partition_id;
|
|
|
|
u64 device_id;
|
|
|
|
struct hv_interrupt_entry interrupt_entry;
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
#define HV_SOURCE_SHADOW_NONE 0x0
|
|
|
|
#define HV_SOURCE_SHADOW_BRIDGE_BUS_RANGE 0x1
|
|
|
|
|
2021-03-23 18:47:16 +00:00
|
|
|
/*
|
|
|
|
* The whole argument should fit in a page to be able to pass to the hypervisor
|
|
|
|
* in one hypercall.
|
|
|
|
*/
|
|
|
|
#define HV_MEMORY_HINT_MAX_GPA_PAGE_RANGES \
|
|
|
|
((HV_HYP_PAGE_SIZE - sizeof(struct hv_memory_hint)) / \
|
|
|
|
sizeof(union hv_gpa_page_range))
|
|
|
|
|
|
|
|
/* HvExtCallMemoryHeatHint hypercall */
|
|
|
|
#define HV_EXT_MEMORY_HEAT_HINT_TYPE_COLD_DISCARD 2
|
|
|
|
struct hv_memory_hint {
|
|
|
|
u64 type:2;
|
|
|
|
u64 reserved:62;
|
|
|
|
union hv_gpa_page_range ranges[];
|
|
|
|
} __packed;
|
|
|
|
|
2020-04-22 19:57:36 +00:00
|
|
|
#endif
|