2021-07-09 15:40:36 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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enum {
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RTQ6752_IDX_PAVDD = 0,
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RTQ6752_IDX_NAVDD = 1,
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RTQ6752_IDX_MAX
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};
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#define RTQ6752_REG_PAVDD 0x00
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#define RTQ6752_REG_NAVDD 0x01
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#define RTQ6752_REG_PAVDDONDLY 0x07
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#define RTQ6752_REG_PAVDDSSTIME 0x08
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#define RTQ6752_REG_NAVDDONDLY 0x0D
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#define RTQ6752_REG_NAVDDSSTIME 0x0E
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#define RTQ6752_REG_OPTION1 0x12
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#define RTQ6752_REG_CHSWITCH 0x16
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#define RTQ6752_REG_FAULT 0x1D
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#define RTQ6752_VOUT_MASK GENMASK(5, 0)
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#define RTQ6752_NAVDDEN_MASK BIT(3)
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#define RTQ6752_PAVDDEN_MASK BIT(0)
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#define RTQ6752_PAVDDAD_MASK BIT(4)
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#define RTQ6752_NAVDDAD_MASK BIT(3)
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#define RTQ6752_PAVDDF_MASK BIT(3)
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#define RTQ6752_NAVDDF_MASK BIT(0)
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#define RTQ6752_ENABLE_MASK (BIT(RTQ6752_IDX_MAX) - 1)
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#define RTQ6752_VOUT_MINUV 5000000
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#define RTQ6752_VOUT_STEPUV 50000
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#define RTQ6752_VOUT_NUM 47
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#define RTQ6752_I2CRDY_TIMEUS 1000
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#define RTQ6752_MINSS_TIMEUS 5000
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struct rtq6752_priv {
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struct regmap *regmap;
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struct gpio_desc *enable_gpio;
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struct mutex lock;
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unsigned char enable_flag;
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};
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static int rtq6752_set_vdd_enable(struct regulator_dev *rdev)
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{
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struct rtq6752_priv *priv = rdev_get_drvdata(rdev);
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int rid = rdev_get_id(rdev), ret;
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mutex_lock(&priv->lock);
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if (priv->enable_gpio) {
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gpiod_set_value(priv->enable_gpio, 1);
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usleep_range(RTQ6752_I2CRDY_TIMEUS,
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RTQ6752_I2CRDY_TIMEUS + 100);
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}
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2021-07-16 03:55:46 +00:00
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if (!priv->enable_flag) {
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regcache_cache_only(priv->regmap, false);
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ret = regcache_sync(priv->regmap);
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if (ret) {
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mutex_unlock(&priv->lock);
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return ret;
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}
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}
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priv->enable_flag |= BIT(rid);
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mutex_unlock(&priv->lock);
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return regulator_enable_regmap(rdev);
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}
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static int rtq6752_set_vdd_disable(struct regulator_dev *rdev)
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{
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struct rtq6752_priv *priv = rdev_get_drvdata(rdev);
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int rid = rdev_get_id(rdev), ret;
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ret = regulator_disable_regmap(rdev);
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if (ret)
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return ret;
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mutex_lock(&priv->lock);
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priv->enable_flag &= ~BIT(rid);
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if (!priv->enable_flag) {
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regcache_cache_only(priv->regmap, true);
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regcache_mark_dirty(priv->regmap);
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}
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2021-07-16 03:55:46 +00:00
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if (priv->enable_gpio)
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gpiod_set_value(priv->enable_gpio, 0);
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2021-07-09 15:40:36 +00:00
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mutex_unlock(&priv->lock);
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return 0;
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}
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static int rtq6752_get_error_flags(struct regulator_dev *rdev,
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unsigned int *flags)
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{
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unsigned int val, events = 0;
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const unsigned int fault_mask[] = {
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RTQ6752_PAVDDF_MASK, RTQ6752_NAVDDF_MASK };
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int rid = rdev_get_id(rdev), ret;
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ret = regmap_read(rdev->regmap, RTQ6752_REG_FAULT, &val);
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if (ret)
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return ret;
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if (val & fault_mask[rid])
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events = REGULATOR_ERROR_REGULATION_OUT;
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*flags = events;
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return 0;
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}
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static const struct regulator_ops rtq6752_regulator_ops = {
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.list_voltage = regulator_list_voltage_linear,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.enable = rtq6752_set_vdd_enable,
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.disable = rtq6752_set_vdd_disable,
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.is_enabled = regulator_is_enabled_regmap,
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.set_active_discharge = regulator_set_active_discharge_regmap,
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.get_error_flags = rtq6752_get_error_flags,
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};
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static const struct regulator_desc rtq6752_regulator_descs[] = {
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{
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.name = "rtq6752-pavdd",
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.of_match = of_match_ptr("pavdd"),
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.regulators_node = of_match_ptr("regulators"),
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.id = RTQ6752_IDX_PAVDD,
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.n_voltages = RTQ6752_VOUT_NUM,
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.ops = &rtq6752_regulator_ops,
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.owner = THIS_MODULE,
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.min_uV = RTQ6752_VOUT_MINUV,
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.uV_step = RTQ6752_VOUT_STEPUV,
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.enable_time = RTQ6752_MINSS_TIMEUS,
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.vsel_reg = RTQ6752_REG_PAVDD,
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.vsel_mask = RTQ6752_VOUT_MASK,
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.enable_reg = RTQ6752_REG_CHSWITCH,
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.enable_mask = RTQ6752_PAVDDEN_MASK,
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.active_discharge_reg = RTQ6752_REG_OPTION1,
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.active_discharge_mask = RTQ6752_PAVDDAD_MASK,
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.active_discharge_off = RTQ6752_PAVDDAD_MASK,
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},
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{
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.name = "rtq6752-navdd",
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.of_match = of_match_ptr("navdd"),
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.regulators_node = of_match_ptr("regulators"),
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.id = RTQ6752_IDX_NAVDD,
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.n_voltages = RTQ6752_VOUT_NUM,
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.ops = &rtq6752_regulator_ops,
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.owner = THIS_MODULE,
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.min_uV = RTQ6752_VOUT_MINUV,
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.uV_step = RTQ6752_VOUT_STEPUV,
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.enable_time = RTQ6752_MINSS_TIMEUS,
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.vsel_reg = RTQ6752_REG_NAVDD,
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.vsel_mask = RTQ6752_VOUT_MASK,
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.enable_reg = RTQ6752_REG_CHSWITCH,
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.enable_mask = RTQ6752_NAVDDEN_MASK,
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.active_discharge_reg = RTQ6752_REG_OPTION1,
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.active_discharge_mask = RTQ6752_NAVDDAD_MASK,
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.active_discharge_off = RTQ6752_NAVDDAD_MASK,
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}
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};
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static int rtq6752_init_device_properties(struct rtq6752_priv *priv)
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{
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u8 raw_vals[] = { 0, 0 };
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int ret;
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/* Configure PAVDD on and softstart delay time to the minimum */
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ret = regmap_raw_write(priv->regmap, RTQ6752_REG_PAVDDONDLY, raw_vals,
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ARRAY_SIZE(raw_vals));
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if (ret)
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return ret;
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/* Configure NAVDD on and softstart delay time to the minimum */
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return regmap_raw_write(priv->regmap, RTQ6752_REG_NAVDDONDLY, raw_vals,
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ARRAY_SIZE(raw_vals));
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}
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static bool rtq6752_is_volatile_reg(struct device *dev, unsigned int reg)
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{
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if (reg == RTQ6752_REG_FAULT)
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return true;
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return false;
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}
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static const struct reg_default rtq6752_reg_defaults[] = {
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{ RTQ6752_REG_PAVDD, 0x14 },
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{ RTQ6752_REG_NAVDD, 0x14 },
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{ RTQ6752_REG_PAVDDONDLY, 0x01 },
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{ RTQ6752_REG_PAVDDSSTIME, 0x01 },
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{ RTQ6752_REG_NAVDDONDLY, 0x01 },
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{ RTQ6752_REG_NAVDDSSTIME, 0x01 },
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{ RTQ6752_REG_OPTION1, 0x07 },
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{ RTQ6752_REG_CHSWITCH, 0x29 },
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};
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static const struct regmap_config rtq6752_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_RBTREE,
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.max_register = RTQ6752_REG_FAULT,
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.reg_defaults = rtq6752_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(rtq6752_reg_defaults),
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.volatile_reg = rtq6752_is_volatile_reg,
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};
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static int rtq6752_probe(struct i2c_client *i2c)
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{
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struct rtq6752_priv *priv;
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struct regulator_config reg_cfg = {};
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struct regulator_dev *rdev;
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int i, ret;
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priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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mutex_init(&priv->lock);
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priv->enable_gpio = devm_gpiod_get_optional(&i2c->dev, "enable",
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GPIOD_OUT_HIGH);
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if (IS_ERR(priv->enable_gpio)) {
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dev_err(&i2c->dev, "Failed to get 'enable' gpio\n");
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return PTR_ERR(priv->enable_gpio);
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}
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usleep_range(RTQ6752_I2CRDY_TIMEUS, RTQ6752_I2CRDY_TIMEUS + 100);
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/* Default EN pin to high, PAVDD and NAVDD will be on */
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priv->enable_flag = RTQ6752_ENABLE_MASK;
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priv->regmap = devm_regmap_init_i2c(i2c, &rtq6752_regmap_config);
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if (IS_ERR(priv->regmap)) {
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dev_err(&i2c->dev, "Failed to init regmap\n");
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return PTR_ERR(priv->regmap);
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}
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ret = rtq6752_init_device_properties(priv);
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if (ret) {
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dev_err(&i2c->dev, "Failed to init device properties\n");
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return ret;
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}
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reg_cfg.dev = &i2c->dev;
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reg_cfg.regmap = priv->regmap;
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reg_cfg.driver_data = priv;
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for (i = 0; i < ARRAY_SIZE(rtq6752_regulator_descs); i++) {
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rdev = devm_regulator_register(&i2c->dev,
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rtq6752_regulator_descs + i,
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®_cfg);
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if (IS_ERR(rdev)) {
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dev_err(&i2c->dev, "Failed to init %d regulator\n", i);
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return PTR_ERR(rdev);
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}
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}
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return 0;
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}
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static const struct of_device_id __maybe_unused rtq6752_device_table[] = {
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{ .compatible = "richtek,rtq6752", },
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{}
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};
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MODULE_DEVICE_TABLE(of, rtq6752_device_table);
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static struct i2c_driver rtq6752_driver = {
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.driver = {
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.name = "rtq6752",
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.of_match_table = rtq6752_device_table,
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},
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.probe_new = rtq6752_probe,
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};
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module_i2c_driver(rtq6752_driver);
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2021-07-14 02:36:10 +00:00
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MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
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MODULE_DESCRIPTION("Richtek RTQ6752 Regulator Driver");
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MODULE_LICENSE("GPL v2");
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