2007-12-11 21:50:17 +00:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2006 Micron Technology Inc.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*/
|
|
|
|
|
2012-09-29 06:56:13 +00:00
|
|
|
#ifndef _MTD_NAND_OMAP2_H
|
|
|
|
#define _MTD_NAND_OMAP2_H
|
|
|
|
|
2007-12-11 21:50:17 +00:00
|
|
|
#include <linux/mtd/partitions.h>
|
|
|
|
|
2012-10-04 10:19:04 +00:00
|
|
|
#define GPMC_BCH_NUM_REMAINDER 8
|
|
|
|
|
2011-01-28 10:12:04 +00:00
|
|
|
enum nand_io {
|
|
|
|
NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
|
|
|
|
NAND_OMAP_POLLED, /* polled mode, without prefetch */
|
2011-01-28 10:12:06 +00:00
|
|
|
NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
|
|
|
|
NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
|
2011-01-28 10:12:04 +00:00
|
|
|
};
|
|
|
|
|
2012-09-29 06:56:13 +00:00
|
|
|
enum omap_ecc {
|
2014-08-25 23:15:32 +00:00
|
|
|
/*
|
|
|
|
* 1-bit ECC: calculation and correction by SW
|
|
|
|
* ECC stored at end of spare area
|
|
|
|
*/
|
|
|
|
OMAP_ECC_HAM1_CODE_SW = 0,
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 1-bit ECC: calculation by GPMC, Error detection by Software
|
|
|
|
* ECC layout compatible with ROM code layout
|
|
|
|
*/
|
|
|
|
OMAP_ECC_HAM1_CODE_HW,
|
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
OMAP NAND driver support multiple ECC scheme, which can used in different
flavours, depending on in-build Hardware engines present on SoC.
This patch updates following in DT bindings related to sectionion of ecc-schemes
- ti,elm-id: replaces elm_id (maintains backward compatibility)
- ti,nand-ecc-opts: selection of h/w or s/w implementation of an ecc-scheme
depends on ti,elm-id. (supported values ham1, bch4, and bch8)
- maintain backward compatibility to deprecated DT bindings (sw, hw, hw-romcode)
Below table shows different flavours of ecc-schemes supported by OMAP devices
+---------------------------------------+---------------+---------------+
| ECC scheme |ECC calculation|Error detection|
+---------------------------------------+---------------+---------------+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W |
|(requires CONFIG_MTD_NAND_ECC_BCH) | | |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
|(requires CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id in DT) | | |
+---------------------------------------+---------------+---------------+
To optimize footprint of omap2-nand driver, selection of some ECC schemes
also require enabling following Kconfigs, in addition to setting appropriate
DT bindings
- Kconfig:CONFIG_MTD_NAND_ECC_BCH error detection done in software
- Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-10-24 12:50:17 +00:00
|
|
|
/* 4-bit ECC calculation by GPMC, Error detection by Software */
|
|
|
|
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
|
|
|
|
/* 4-bit ECC calculation by GPMC, Error detection by ELM */
|
|
|
|
OMAP_ECC_BCH4_CODE_HW,
|
|
|
|
/* 8-bit ECC calculation by GPMC, Error detection by Software */
|
|
|
|
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
|
|
|
|
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
|
|
|
|
OMAP_ECC_BCH8_CODE_HW,
|
2014-05-19 07:54:39 +00:00
|
|
|
/* 16-bit ECC calculation by GPMC, Error detection by ELM */
|
|
|
|
OMAP_ECC_BCH16_CODE_HW,
|
2012-09-29 06:56:13 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct gpmc_nand_regs {
|
|
|
|
void __iomem *gpmc_nand_command;
|
|
|
|
void __iomem *gpmc_nand_address;
|
|
|
|
void __iomem *gpmc_nand_data;
|
|
|
|
void __iomem *gpmc_prefetch_config1;
|
|
|
|
void __iomem *gpmc_prefetch_config2;
|
|
|
|
void __iomem *gpmc_prefetch_control;
|
|
|
|
void __iomem *gpmc_prefetch_status;
|
|
|
|
void __iomem *gpmc_ecc_config;
|
|
|
|
void __iomem *gpmc_ecc_control;
|
|
|
|
void __iomem *gpmc_ecc_size_config;
|
|
|
|
void __iomem *gpmc_ecc1_result;
|
2012-10-04 10:19:04 +00:00
|
|
|
void __iomem *gpmc_bch_result0[GPMC_BCH_NUM_REMAINDER];
|
|
|
|
void __iomem *gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
|
|
|
|
void __iomem *gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
|
|
|
|
void __iomem *gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
|
2014-05-19 07:54:39 +00:00
|
|
|
void __iomem *gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
|
|
|
|
void __iomem *gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
|
|
|
|
void __iomem *gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
|
2015-08-07 07:38:13 +00:00
|
|
|
/* Deprecated. Do not use */
|
|
|
|
void __iomem *gpmc_status;
|
2012-09-29 06:56:13 +00:00
|
|
|
};
|
|
|
|
|
2007-12-11 21:50:17 +00:00
|
|
|
struct omap_nand_platform_data {
|
|
|
|
int cs;
|
|
|
|
struct mtd_partition *parts;
|
|
|
|
int nr_parts;
|
2014-09-11 15:02:08 +00:00
|
|
|
bool flash_bbt;
|
2011-01-28 10:12:04 +00:00
|
|
|
enum nand_io xfer_type;
|
2010-02-15 18:03:33 +00:00
|
|
|
int devsize;
|
2011-01-28 10:12:08 +00:00
|
|
|
enum omap_ecc ecc_opt;
|
2010-02-15 18:03:33 +00:00
|
|
|
|
ARM: OMAP2+: cleaned-up DT support of various ECC schemes
OMAP NAND driver support multiple ECC scheme, which can used in different
flavours, depending on in-build Hardware engines present on SoC.
This patch updates following in DT bindings related to sectionion of ecc-schemes
- ti,elm-id: replaces elm_id (maintains backward compatibility)
- ti,nand-ecc-opts: selection of h/w or s/w implementation of an ecc-scheme
depends on ti,elm-id. (supported values ham1, bch4, and bch8)
- maintain backward compatibility to deprecated DT bindings (sw, hw, hw-romcode)
Below table shows different flavours of ecc-schemes supported by OMAP devices
+---------------------------------------+---------------+---------------+
| ECC scheme |ECC calculation|Error detection|
+---------------------------------------+---------------+---------------+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W |
|(requires CONFIG_MTD_NAND_ECC_BCH) | | |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
|(requires CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id in DT) | | |
+---------------------------------------+---------------+---------------+
To optimize footprint of omap2-nand driver, selection of some ECC schemes
also require enabling following Kconfigs, in addition to setting appropriate
DT bindings
- Kconfig:CONFIG_MTD_NAND_ECC_BCH error detection done in software
- Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-10-24 12:50:17 +00:00
|
|
|
struct device_node *elm_of_node;
|
2015-08-05 11:01:50 +00:00
|
|
|
|
|
|
|
/* deprecated */
|
|
|
|
struct gpmc_nand_regs reg;
|
2014-05-21 04:29:03 +00:00
|
|
|
struct device_node *of_node;
|
2015-08-06 14:39:35 +00:00
|
|
|
bool dev_ready;
|
2012-12-14 10:36:41 +00:00
|
|
|
};
|
2010-04-20 06:33:26 +00:00
|
|
|
#endif
|