2018-05-09 18:06:04 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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2016-05-03 17:33:40 +00:00
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*
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* Description: CoreSight System Trace Macrocell driver
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*
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* Initial implementation by Pratik Patel
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* (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
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*
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* Serious refactoring, code cleanup and upgrading to the Coresight upstream
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* framework by Mathieu Poirier
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* (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
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*
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* Guaranteed timing and support for various packet type coming from the
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* generic STM API by Chunyan Zhang
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* (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
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*/
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#include <asm/local.h>
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2019-06-19 19:53:05 +00:00
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#include <linux/acpi.h>
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2016-05-03 17:33:40 +00:00
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#include <linux/amba/bus.h>
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#include <linux/bitmap.h>
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#include <linux/clk.h>
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#include <linux/coresight.h>
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#include <linux/coresight-stm.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/of_address.h>
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#include <linux/perf_event.h>
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#include <linux/pm_runtime.h>
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#include <linux/stm.h>
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#include "coresight-priv.h"
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#define STMDMASTARTR 0xc04
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#define STMDMASTOPR 0xc08
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#define STMDMASTATR 0xc0c
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#define STMDMACTLR 0xc10
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#define STMDMAIDR 0xcfc
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#define STMHEER 0xd00
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#define STMHETER 0xd20
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#define STMHEBSR 0xd60
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#define STMHEMCR 0xd64
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#define STMHEMASTR 0xdf4
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#define STMHEFEAT1R 0xdf8
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#define STMHEIDR 0xdfc
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#define STMSPER 0xe00
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#define STMSPTER 0xe20
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#define STMPRIVMASKR 0xe40
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#define STMSPSCR 0xe60
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#define STMSPMSCR 0xe64
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#define STMSPOVERRIDER 0xe68
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#define STMSPMOVERRIDER 0xe6c
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#define STMSPTRIGCSR 0xe70
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#define STMTCSR 0xe80
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#define STMTSSTIMR 0xe84
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#define STMTSFREQR 0xe8c
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#define STMSYNCR 0xe90
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#define STMAUXCR 0xe94
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#define STMSPFEAT1R 0xea0
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#define STMSPFEAT2R 0xea4
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#define STMSPFEAT3R 0xea8
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#define STMITTRIGGER 0xee8
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#define STMITATBDATA0 0xeec
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#define STMITATBCTR2 0xef0
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#define STMITATBID 0xef4
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#define STMITATBCTR0 0xef8
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#define STM_32_CHANNEL 32
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#define BYTES_PER_CHANNEL 256
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#define STM_TRACE_BUF_SIZE 4096
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#define STM_SW_MASTER_END 127
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/* Register bit definition */
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#define STMTCSR_BUSY_BIT 23
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/* Reserve the first 10 channels for kernel usage */
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#define STM_CHANNEL_OFFSET 0
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enum stm_pkt_type {
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STM_PKT_TYPE_DATA = 0x98,
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STM_PKT_TYPE_FLAG = 0xE8,
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STM_PKT_TYPE_TRIG = 0xF8,
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};
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#define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
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(ch * BYTES_PER_CHANNEL))
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#define stm_channel_off(type, opts) (type & ~opts)
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static int boot_nr_channel;
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/*
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* Not really modular but using module_param is the easiest way to
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* remain consistent with existing use cases for now.
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*/
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module_param_named(
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boot_nr_channel, boot_nr_channel, int, S_IRUGO
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);
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2020-11-27 17:52:56 +00:00
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/*
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2016-05-03 17:33:40 +00:00
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* struct channel_space - central management entity for extended ports
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* @base: memory mapped base address where channels start.
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2016-08-25 21:18:52 +00:00
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* @phys: physical base address of channel region.
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2016-05-03 17:33:40 +00:00
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* @guaraneed: is the channel delivery guaranteed.
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*/
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struct channel_space {
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void __iomem *base;
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2016-08-25 21:18:52 +00:00
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phys_addr_t phys;
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2016-05-03 17:33:40 +00:00
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unsigned long *guaranteed;
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};
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2019-06-19 19:53:04 +00:00
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DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
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2016-05-03 17:33:40 +00:00
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/**
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* struct stm_drvdata - specifics associated to an STM component
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* @base: memory mapped base address for this component.
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* @atclk: optional clock for the core parts of the STM.
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* @csdev: component vitals needed by the framework.
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* @spinlock: only one at a time pls.
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* @chs: the channels accociated to this STM.
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* @stm: structure associated to the generic STM interface.
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* @mode: this tracer's mode, i.e sysFS, or disabled.
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* @traceid: value of the current ID for this component.
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* @write_bytes: Maximus bytes this STM can write at a time.
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* @stmsper: settings for register STMSPER.
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* @stmspscr: settings for register STMSPSCR.
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* @numsp: the total number of stimulus port support by this STM.
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* @stmheer: settings for register STMHEER.
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* @stmheter: settings for register STMHETER.
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* @stmhebsr: settings for register STMHEBSR.
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*/
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struct stm_drvdata {
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void __iomem *base;
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struct clk *atclk;
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struct coresight_device *csdev;
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spinlock_t spinlock;
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struct channel_space chs;
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struct stm_data stm;
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local_t mode;
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u8 traceid;
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u32 write_bytes;
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u32 stmsper;
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u32 stmspscr;
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u32 numsp;
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u32 stmheer;
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u32 stmheter;
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u32 stmhebsr;
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};
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static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
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writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
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writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
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writel_relaxed(0x01 | /* Enable HW event tracing */
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0x04, /* Error detection on event tracing */
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drvdata->base + STMHEMCR);
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CS_LOCK(drvdata->base);
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}
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static void stm_port_enable_hw(struct stm_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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/* ATB trigger enable on direct writes to TRIG locations */
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writel_relaxed(0x10,
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drvdata->base + STMSPTRIGCSR);
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writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
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writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
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CS_LOCK(drvdata->base);
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}
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static void stm_enable_hw(struct stm_drvdata *drvdata)
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{
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if (drvdata->stmheer)
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stm_hwevent_enable_hw(drvdata);
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stm_port_enable_hw(drvdata);
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CS_UNLOCK(drvdata->base);
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/* 4096 byte between synchronisation packets */
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writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
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writel_relaxed((drvdata->traceid << 16 | /* trace id */
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0x02 | /* timestamp enable */
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0x01), /* global STM enable */
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drvdata->base + STMTCSR);
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CS_LOCK(drvdata->base);
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}
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static int stm_enable(struct coresight_device *csdev,
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2016-08-25 21:19:10 +00:00
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struct perf_event *event, u32 mode)
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2016-05-03 17:33:40 +00:00
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{
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u32 val;
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struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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if (mode != CS_MODE_SYSFS)
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return -EINVAL;
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val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
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/* Someone is already using the tracer */
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if (val)
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return -EBUSY;
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2019-06-19 17:29:15 +00:00
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pm_runtime_get_sync(csdev->dev.parent);
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2016-05-03 17:33:40 +00:00
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spin_lock(&drvdata->spinlock);
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stm_enable_hw(drvdata);
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spin_unlock(&drvdata->spinlock);
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2019-06-19 17:29:15 +00:00
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dev_dbg(&csdev->dev, "STM tracing enabled\n");
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2016-05-03 17:33:40 +00:00
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return 0;
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}
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static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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writel_relaxed(0x0, drvdata->base + STMHEMCR);
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writel_relaxed(0x0, drvdata->base + STMHEER);
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writel_relaxed(0x0, drvdata->base + STMHETER);
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CS_LOCK(drvdata->base);
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}
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static void stm_port_disable_hw(struct stm_drvdata *drvdata)
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{
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CS_UNLOCK(drvdata->base);
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writel_relaxed(0x0, drvdata->base + STMSPER);
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writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
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CS_LOCK(drvdata->base);
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}
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static void stm_disable_hw(struct stm_drvdata *drvdata)
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{
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u32 val;
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CS_UNLOCK(drvdata->base);
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val = readl_relaxed(drvdata->base + STMTCSR);
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val &= ~0x1; /* clear global STM enable [0] */
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writel_relaxed(val, drvdata->base + STMTCSR);
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CS_LOCK(drvdata->base);
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stm_port_disable_hw(drvdata);
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if (drvdata->stmheer)
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stm_hwevent_disable_hw(drvdata);
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}
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2016-08-25 21:19:10 +00:00
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static void stm_disable(struct coresight_device *csdev,
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struct perf_event *event)
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2016-05-03 17:33:40 +00:00
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{
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struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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2021-02-01 18:13:27 +00:00
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struct csdev_access *csa = &csdev->access;
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2016-05-03 17:33:40 +00:00
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/*
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* For as long as the tracer isn't disabled another entity can't
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* change its status. As such we can read the status here without
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* fearing it will change under us.
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*/
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if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
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spin_lock(&drvdata->spinlock);
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stm_disable_hw(drvdata);
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spin_unlock(&drvdata->spinlock);
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/* Wait until the engine has completely stopped */
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2021-02-01 18:13:27 +00:00
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coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
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2016-05-03 17:33:40 +00:00
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2019-06-19 17:29:15 +00:00
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pm_runtime_put(csdev->dev.parent);
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2016-05-03 17:33:40 +00:00
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local_set(&drvdata->mode, CS_MODE_DISABLED);
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2019-06-19 17:29:15 +00:00
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dev_dbg(&csdev->dev, "STM tracing disabled\n");
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2016-05-03 17:33:40 +00:00
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}
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}
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static int stm_trace_id(struct coresight_device *csdev)
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{
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struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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return drvdata->traceid;
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}
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static const struct coresight_ops_source stm_source_ops = {
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.trace_id = stm_trace_id,
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.enable = stm_enable,
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.disable = stm_disable,
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};
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static const struct coresight_ops stm_cs_ops = {
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.source_ops = &stm_source_ops,
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};
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static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
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{
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return ((unsigned long)addr & (write_bytes - 1));
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}
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2017-08-02 16:22:20 +00:00
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static void stm_send(void __iomem *addr, const void *data,
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u32 size, u8 write_bytes)
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2016-05-03 17:33:40 +00:00
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{
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u8 paload[8];
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if (stm_addr_unaligned(data, write_bytes)) {
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memcpy(paload, data, size);
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data = paload;
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}
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/* now we are 64bit/32bit aligned */
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switch (size) {
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#ifdef CONFIG_64BIT
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case 8:
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writeq_relaxed(*(u64 *)data, addr);
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break;
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#endif
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case 4:
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writel_relaxed(*(u32 *)data, addr);
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break;
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case 2:
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writew_relaxed(*(u16 *)data, addr);
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break;
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case 1:
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writeb_relaxed(*(u8 *)data, addr);
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break;
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default:
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break;
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}
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}
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static int stm_generic_link(struct stm_data *stm_data,
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unsigned int master, unsigned int channel)
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{
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struct stm_drvdata *drvdata = container_of(stm_data,
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struct stm_drvdata, stm);
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if (!drvdata || !drvdata->csdev)
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return -EINVAL;
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return coresight_enable(drvdata->csdev);
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}
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static void stm_generic_unlink(struct stm_data *stm_data,
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|
|
|
unsigned int master, unsigned int channel)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = container_of(stm_data,
|
|
|
|
struct stm_drvdata, stm);
|
|
|
|
if (!drvdata || !drvdata->csdev)
|
|
|
|
return;
|
|
|
|
|
coresight: STM: Balance enable/disable
The stm is automatically enabled when an application sets the policy
via ->link() call back by using coresight_enable(), which keeps the
refcount of the current users of the STM. However, the unlink() callback
issues stm_disable() directly, which leaves the STM turned off, without
the coresight layer knowing about it. This prevents any further uses
of the STM hardware as the coresight layer still thinks the STM is
turned on and doesn't enable the hardware when required. Even manually
enabling the STM via sysfs can't really enable the hw.
e.g,
$ echo 1 > $CS_DEVS/$ETR/enable_sink
$ mkdir -p $CONFIG_FS/stp-policy/$source.0/stm_test/
$ echo 32768 65535 > $CONFIG_FS/stp-policy/$source.0/stm_test/channels
$ echo 64 > $CS_DEVS/$source/traceid
$ ./stm_app
Sending 64000 byte blocks of pattern 0 at 0us intervals
Success to map channel(32768~32783) to 0xffffa95fa000
Sending on channel 32768
$ dd if=/dev/$ETR of=~/trace.bin.1
597+1 records in
597+1 records out
305920 bytes (306 kB) copied, 0.399952 s, 765 kB/s
$ ./stm_app
Sending 64000 byte blocks of pattern 0 at 0us intervals
Success to map channel(32768~32783) to 0xffff7e9e2000
Sending on channel 32768
$ dd if=/dev/$ETR of=~/trace.bin.2
0+0 records in
0+0 records out
0 bytes (0 B) copied, 0.0232083 s, 0.0 kB/s
Note that we don't get any data from the ETR for the second session.
Also dmesg shows :
[ 77.520458] coresight-tmc 20800000.etr: TMC-ETR enabled
[ 77.537097] coresight-replicator etr_replicator@20890000: REPLICATOR enabled
[ 77.558828] coresight-replicator main_replicator@208a0000: REPLICATOR enabled
[ 77.581068] coresight-funnel 208c0000.main_funnel: FUNNEL inport 0 enabled
[ 77.602217] coresight-tmc 20840000.etf: TMC-ETF enabled
[ 77.618422] coresight-stm 20860000.stm: STM tracing enabled
[ 139.554252] coresight-stm 20860000.stm: STM tracing disabled
# End of first tracing session
[ 146.351135] coresight-tmc 20800000.etr: TMC read start
[ 146.514486] coresight-tmc 20800000.etr: TMC read end
# Note that the STM is not turned on via stm_generic_link()->coresight_enable()
# and hence none of the components are turned on.
[ 152.479080] coresight-tmc 20800000.etr: TMC read start
[ 152.542632] coresight-tmc 20800000.etr: TMC read end
This patch fixes the problem by balancing the unlink operation by using
the coresight_disable(), keeping the coresight layer in sync with the
hardware state and thus allowing normal usage of the STM component.
Fixes: commit 237483aa5cf43 ("coresight: stm: adding driver for CoreSight STM component")
Cc: Pratik Patel <pratikp@codeaurora.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: stable@vger.kernel.org # 4.7+
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reported-by: Robert Walker <robert.walker@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-01-16 18:00:00 +00:00
|
|
|
coresight_disable(drvdata->csdev);
|
2016-05-03 17:33:40 +00:00
|
|
|
}
|
|
|
|
|
2016-08-25 21:18:52 +00:00
|
|
|
static phys_addr_t
|
|
|
|
stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
|
|
|
|
unsigned int channel, unsigned int nr_chans)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = container_of(stm_data,
|
|
|
|
struct stm_drvdata, stm);
|
|
|
|
phys_addr_t addr;
|
|
|
|
|
|
|
|
addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
|
|
|
|
|
|
|
|
if (offset_in_page(addr) ||
|
|
|
|
offset_in_page(nr_chans * BYTES_PER_CHANNEL))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
2016-05-03 17:33:40 +00:00
|
|
|
static long stm_generic_set_options(struct stm_data *stm_data,
|
|
|
|
unsigned int master,
|
|
|
|
unsigned int channel,
|
|
|
|
unsigned int nr_chans,
|
|
|
|
unsigned long options)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = container_of(stm_data,
|
|
|
|
struct stm_drvdata, stm);
|
|
|
|
if (!(drvdata && local_read(&drvdata->mode)))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (channel >= drvdata->numsp)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
switch (options) {
|
|
|
|
case STM_OPTION_GUARANTEED:
|
|
|
|
set_bit(channel, drvdata->chs.guaranteed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM_OPTION_INVARIANT:
|
|
|
|
clear_bit(channel, drvdata->chs.guaranteed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-21 07:57:20 +00:00
|
|
|
static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
|
2016-05-03 17:33:40 +00:00
|
|
|
unsigned int master,
|
|
|
|
unsigned int channel,
|
|
|
|
unsigned int packet,
|
|
|
|
unsigned int flags,
|
|
|
|
unsigned int size,
|
|
|
|
const unsigned char *payload)
|
|
|
|
{
|
2017-08-02 16:22:20 +00:00
|
|
|
void __iomem *ch_addr;
|
2016-05-03 17:33:40 +00:00
|
|
|
struct stm_drvdata *drvdata = container_of(stm_data,
|
|
|
|
struct stm_drvdata, stm);
|
2020-09-16 19:17:23 +00:00
|
|
|
unsigned int stm_flags;
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
if (!(drvdata && local_read(&drvdata->mode)))
|
2016-11-29 16:47:11 +00:00
|
|
|
return -EACCES;
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
if (channel >= drvdata->numsp)
|
2016-11-29 16:47:11 +00:00
|
|
|
return -EINVAL;
|
2016-05-03 17:33:40 +00:00
|
|
|
|
2017-08-02 16:22:20 +00:00
|
|
|
ch_addr = stm_channel_addr(drvdata, channel);
|
2016-05-03 17:33:40 +00:00
|
|
|
|
2020-09-16 19:17:23 +00:00
|
|
|
stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
|
|
|
|
STM_FLAG_TIMESTAMPED : 0;
|
|
|
|
stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
|
2016-05-03 17:33:40 +00:00
|
|
|
STM_FLAG_GUARANTEED : 0;
|
|
|
|
|
|
|
|
if (size > drvdata->write_bytes)
|
|
|
|
size = drvdata->write_bytes;
|
|
|
|
else
|
|
|
|
size = rounddown_pow_of_two(size);
|
|
|
|
|
|
|
|
switch (packet) {
|
|
|
|
case STP_PACKET_FLAG:
|
2020-09-16 19:17:23 +00:00
|
|
|
ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The generic STM core sets a size of '0' on flag packets.
|
|
|
|
* As such send a flag packet of size '1' and tell the
|
|
|
|
* core we did so.
|
|
|
|
*/
|
2017-08-02 16:22:20 +00:00
|
|
|
stm_send(ch_addr, payload, 1, drvdata->write_bytes);
|
2016-05-03 17:33:40 +00:00
|
|
|
size = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STP_PACKET_DATA:
|
2020-09-16 19:17:23 +00:00
|
|
|
stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
|
|
|
|
ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
|
2017-08-02 16:22:20 +00:00
|
|
|
stm_send(ch_addr, payload, size,
|
2016-05-03 17:33:40 +00:00
|
|
|
drvdata->write_bytes);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t hwevent_enable_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val = drvdata->stmheer;
|
|
|
|
|
|
|
|
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t hwevent_enable_store(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = kstrtoul(buf, 16, &val);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
drvdata->stmheer = val;
|
|
|
|
/* HW event enable and trigger go hand in hand */
|
|
|
|
drvdata->stmheter = val;
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(hwevent_enable);
|
|
|
|
|
|
|
|
static ssize_t hwevent_select_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val = drvdata->stmhebsr;
|
|
|
|
|
|
|
|
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t hwevent_select_store(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = kstrtoul(buf, 16, &val);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
drvdata->stmhebsr = val;
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(hwevent_select);
|
|
|
|
|
|
|
|
static ssize_t port_select_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val;
|
|
|
|
|
|
|
|
if (!local_read(&drvdata->mode)) {
|
|
|
|
val = drvdata->stmspscr;
|
|
|
|
} else {
|
|
|
|
spin_lock(&drvdata->spinlock);
|
|
|
|
val = readl_relaxed(drvdata->base + STMSPSCR);
|
|
|
|
spin_unlock(&drvdata->spinlock);
|
|
|
|
}
|
|
|
|
|
|
|
|
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t port_select_store(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val, stmsper;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = kstrtoul(buf, 16, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
spin_lock(&drvdata->spinlock);
|
|
|
|
drvdata->stmspscr = val;
|
|
|
|
|
|
|
|
if (local_read(&drvdata->mode)) {
|
|
|
|
CS_UNLOCK(drvdata->base);
|
|
|
|
/* Process as per ARM's TRM recommendation */
|
|
|
|
stmsper = readl_relaxed(drvdata->base + STMSPER);
|
|
|
|
writel_relaxed(0x0, drvdata->base + STMSPER);
|
|
|
|
writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
|
|
|
|
writel_relaxed(stmsper, drvdata->base + STMSPER);
|
|
|
|
CS_LOCK(drvdata->base);
|
|
|
|
}
|
|
|
|
spin_unlock(&drvdata->spinlock);
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(port_select);
|
|
|
|
|
|
|
|
static ssize_t port_enable_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val;
|
|
|
|
|
|
|
|
if (!local_read(&drvdata->mode)) {
|
|
|
|
val = drvdata->stmsper;
|
|
|
|
} else {
|
|
|
|
spin_lock(&drvdata->spinlock);
|
|
|
|
val = readl_relaxed(drvdata->base + STMSPER);
|
|
|
|
spin_unlock(&drvdata->spinlock);
|
|
|
|
}
|
|
|
|
|
|
|
|
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t port_enable_store(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
unsigned long val;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = kstrtoul(buf, 16, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
spin_lock(&drvdata->spinlock);
|
|
|
|
drvdata->stmsper = val;
|
|
|
|
|
|
|
|
if (local_read(&drvdata->mode)) {
|
|
|
|
CS_UNLOCK(drvdata->base);
|
|
|
|
writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
|
|
|
|
CS_LOCK(drvdata->base);
|
|
|
|
}
|
|
|
|
spin_unlock(&drvdata->spinlock);
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(port_enable);
|
|
|
|
|
|
|
|
static ssize_t traceid_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *buf)
|
|
|
|
{
|
|
|
|
unsigned long val;
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
|
|
|
|
val = drvdata->traceid;
|
|
|
|
return sprintf(buf, "%#lx\n", val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t traceid_store(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
const char *buf, size_t size)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
unsigned long val;
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
|
|
|
|
|
|
|
|
ret = kstrtoul(buf, 16, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* traceid field is 7bit wide on STM32 */
|
|
|
|
drvdata->traceid = val & 0x7f;
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(traceid);
|
|
|
|
|
2017-08-02 16:22:06 +00:00
|
|
|
#define coresight_stm_reg(name, offset) \
|
|
|
|
coresight_simple_reg32(struct stm_drvdata, name, offset)
|
|
|
|
|
|
|
|
coresight_stm_reg(tcsr, STMTCSR);
|
|
|
|
coresight_stm_reg(tsfreqr, STMTSFREQR);
|
|
|
|
coresight_stm_reg(syncr, STMSYNCR);
|
|
|
|
coresight_stm_reg(sper, STMSPER);
|
|
|
|
coresight_stm_reg(spter, STMSPTER);
|
|
|
|
coresight_stm_reg(privmaskr, STMPRIVMASKR);
|
|
|
|
coresight_stm_reg(spscr, STMSPSCR);
|
|
|
|
coresight_stm_reg(spmscr, STMSPMSCR);
|
|
|
|
coresight_stm_reg(spfeat1r, STMSPFEAT1R);
|
|
|
|
coresight_stm_reg(spfeat2r, STMSPFEAT2R);
|
|
|
|
coresight_stm_reg(spfeat3r, STMSPFEAT3R);
|
|
|
|
coresight_stm_reg(devid, CORESIGHT_DEVID);
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
static struct attribute *coresight_stm_attrs[] = {
|
|
|
|
&dev_attr_hwevent_enable.attr,
|
|
|
|
&dev_attr_hwevent_select.attr,
|
|
|
|
&dev_attr_port_enable.attr,
|
|
|
|
&dev_attr_port_select.attr,
|
|
|
|
&dev_attr_traceid.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute *coresight_stm_mgmt_attrs[] = {
|
|
|
|
&dev_attr_tcsr.attr,
|
|
|
|
&dev_attr_tsfreqr.attr,
|
|
|
|
&dev_attr_syncr.attr,
|
|
|
|
&dev_attr_sper.attr,
|
|
|
|
&dev_attr_spter.attr,
|
|
|
|
&dev_attr_privmaskr.attr,
|
|
|
|
&dev_attr_spscr.attr,
|
|
|
|
&dev_attr_spmscr.attr,
|
|
|
|
&dev_attr_spfeat1r.attr,
|
|
|
|
&dev_attr_spfeat2r.attr,
|
|
|
|
&dev_attr_spfeat3r.attr,
|
|
|
|
&dev_attr_devid.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group coresight_stm_group = {
|
|
|
|
.attrs = coresight_stm_attrs,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group coresight_stm_mgmt_group = {
|
|
|
|
.attrs = coresight_stm_mgmt_attrs,
|
|
|
|
.name = "mgmt",
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group *coresight_stm_groups[] = {
|
|
|
|
&coresight_stm_group,
|
|
|
|
&coresight_stm_mgmt_group,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2019-06-19 17:29:21 +00:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
|
2016-05-03 17:33:40 +00:00
|
|
|
{
|
|
|
|
const char *name = NULL;
|
|
|
|
int index = 0, found = 0;
|
2019-06-19 17:29:21 +00:00
|
|
|
struct device_node *np = dev->of_node;
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
while (!of_property_read_string_index(np, "reg-names", index, &name)) {
|
2019-06-19 17:29:21 +00:00
|
|
|
if (strcmp("stm-stimulus-base", name)) {
|
2016-05-03 17:33:40 +00:00
|
|
|
index++;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We have a match and @index is where it's at */
|
|
|
|
found = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!found)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return of_address_to_resource(np, index, res);
|
|
|
|
}
|
2019-06-19 17:29:21 +00:00
|
|
|
#else
|
|
|
|
static inline int of_stm_get_stimulus_area(struct device *dev,
|
|
|
|
struct resource *res)
|
|
|
|
{
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2019-06-19 19:53:05 +00:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
bool found_base = false;
|
|
|
|
struct resource_entry *rent;
|
|
|
|
LIST_HEAD(res_list);
|
|
|
|
|
|
|
|
struct acpi_device *adev = ACPI_COMPANION(dev);
|
|
|
|
|
|
|
|
rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
|
|
|
|
if (rc < 0)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The stimulus base for STM device must be listed as the second memory
|
|
|
|
* resource, followed by the programming base address as described in
|
|
|
|
* "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
|
|
|
|
* document (DEN0067).
|
|
|
|
*/
|
|
|
|
rc = -ENOENT;
|
|
|
|
list_for_each_entry(rent, &res_list, node) {
|
|
|
|
if (resource_type(rent->res) != IORESOURCE_MEM)
|
|
|
|
continue;
|
|
|
|
if (found_base) {
|
|
|
|
*res = *rent->res;
|
|
|
|
rc = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
found_base = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
acpi_dev_free_resource_list(&res_list);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline int acpi_stm_get_stimulus_area(struct device *dev,
|
|
|
|
struct resource *res)
|
|
|
|
{
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2019-06-19 17:29:21 +00:00
|
|
|
static int stm_get_stimulus_area(struct device *dev, struct resource *res)
|
|
|
|
{
|
2019-06-19 19:53:05 +00:00
|
|
|
struct fwnode_handle *fwnode = dev_fwnode(dev);
|
|
|
|
|
|
|
|
if (is_of_node(fwnode))
|
2019-06-19 17:29:21 +00:00
|
|
|
return of_stm_get_stimulus_area(dev, res);
|
2019-06-19 19:53:05 +00:00
|
|
|
else if (is_acpi_node(fwnode))
|
|
|
|
return acpi_stm_get_stimulus_area(dev, res);
|
2019-06-19 17:29:21 +00:00
|
|
|
return -ENOENT;
|
|
|
|
}
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
u32 stmspfeat2r;
|
|
|
|
|
|
|
|
if (!IS_ENABLED(CONFIG_64BIT))
|
|
|
|
return 4;
|
|
|
|
|
|
|
|
stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* bit[15:12] represents the fundamental data size
|
|
|
|
* 0 - 32-bit data
|
|
|
|
* 1 - 64-bit data
|
|
|
|
*/
|
|
|
|
return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
u32 numsp;
|
|
|
|
|
|
|
|
numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
|
|
|
|
/*
|
|
|
|
* NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
|
|
|
|
* 32 stimulus ports are supported.
|
|
|
|
*/
|
|
|
|
numsp &= 0x1ffff;
|
|
|
|
if (!numsp)
|
|
|
|
numsp = STM_32_CHANNEL;
|
|
|
|
return numsp;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stm_init_default_data(struct stm_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
/* Don't use port selection */
|
|
|
|
drvdata->stmspscr = 0x0;
|
|
|
|
/*
|
|
|
|
* Enable all channel regardless of their number. When port
|
|
|
|
* selection isn't used (see above) STMSPER applies to all
|
|
|
|
* 32 channel group available, hence setting all 32 bits to 1
|
|
|
|
*/
|
|
|
|
drvdata->stmsper = ~0x0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
|
|
|
|
* anything equal to or higher than 0x70 is reserved. Since 0x00 is
|
|
|
|
* also reserved the STM trace ID needs to be higher than 0x00 and
|
|
|
|
* lowner than 0x10.
|
|
|
|
*/
|
|
|
|
drvdata->traceid = 0x1;
|
|
|
|
|
|
|
|
/* Set invariant transaction timing on all channels */
|
|
|
|
bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
|
|
|
|
}
|
|
|
|
|
2019-06-19 17:29:15 +00:00
|
|
|
static void stm_init_generic_data(struct stm_drvdata *drvdata,
|
|
|
|
const char *name)
|
2016-05-03 17:33:40 +00:00
|
|
|
{
|
2019-06-19 17:29:15 +00:00
|
|
|
drvdata->stm.name = name;
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* MasterIDs are assigned at HW design phase. As such the core is
|
|
|
|
* using a single master for interaction with this device.
|
|
|
|
*/
|
|
|
|
drvdata->stm.sw_start = 1;
|
|
|
|
drvdata->stm.sw_end = 1;
|
|
|
|
drvdata->stm.hw_override = true;
|
|
|
|
drvdata->stm.sw_nchannels = drvdata->numsp;
|
2016-08-25 21:18:52 +00:00
|
|
|
drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
|
2016-05-03 17:33:40 +00:00
|
|
|
drvdata->stm.packet = stm_generic_packet;
|
2016-08-25 21:18:52 +00:00
|
|
|
drvdata->stm.mmio_addr = stm_mmio_addr;
|
2016-05-03 17:33:40 +00:00
|
|
|
drvdata->stm.link = stm_generic_link;
|
|
|
|
drvdata->stm.unlink = stm_generic_unlink;
|
|
|
|
drvdata->stm.set_options = stm_generic_set_options;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm_probe(struct amba_device *adev, const struct amba_id *id)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
void __iomem *base;
|
|
|
|
struct device *dev = &adev->dev;
|
|
|
|
struct coresight_platform_data *pdata = NULL;
|
|
|
|
struct stm_drvdata *drvdata;
|
|
|
|
struct resource *res = &adev->res;
|
|
|
|
struct resource ch_res;
|
2016-08-25 21:19:05 +00:00
|
|
|
struct coresight_desc desc = { 0 };
|
2016-05-03 17:33:40 +00:00
|
|
|
|
2019-06-19 19:53:04 +00:00
|
|
|
desc.name = coresight_alloc_device_name(&stm_devs, dev);
|
|
|
|
if (!desc.name)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2016-05-03 17:33:40 +00:00
|
|
|
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
|
|
|
if (!drvdata)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
|
|
|
|
if (!IS_ERR(drvdata->atclk)) {
|
|
|
|
ret = clk_prepare_enable(drvdata->atclk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
dev_set_drvdata(dev, drvdata);
|
|
|
|
|
|
|
|
base = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
|
|
|
drvdata->base = base;
|
2021-02-01 18:13:25 +00:00
|
|
|
desc.access = CSDEV_ACCESS_IOMEM(base);
|
2016-05-03 17:33:40 +00:00
|
|
|
|
2019-06-19 17:29:21 +00:00
|
|
|
ret = stm_get_stimulus_area(dev, &ch_res);
|
2016-05-03 17:33:40 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-08-25 21:18:52 +00:00
|
|
|
drvdata->chs.phys = ch_res.start;
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
base = devm_ioremap_resource(dev, &ch_res);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
|
|
|
drvdata->chs.base = base;
|
|
|
|
|
|
|
|
drvdata->write_bytes = stm_fundamental_data_size(drvdata);
|
|
|
|
|
2019-02-05 23:24:54 +00:00
|
|
|
if (boot_nr_channel)
|
2016-05-03 17:33:40 +00:00
|
|
|
drvdata->numsp = boot_nr_channel;
|
2019-02-05 23:24:54 +00:00
|
|
|
else
|
2016-05-03 17:33:40 +00:00
|
|
|
drvdata->numsp = stm_num_stimulus_port(drvdata);
|
2019-02-05 23:24:54 +00:00
|
|
|
|
2021-11-03 18:39:18 +00:00
|
|
|
drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!drvdata->chs.guaranteed)
|
2016-05-03 17:33:40 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
spin_lock_init(&drvdata->spinlock);
|
|
|
|
|
|
|
|
stm_init_default_data(drvdata);
|
2019-06-19 19:53:04 +00:00
|
|
|
stm_init_generic_data(drvdata, desc.name);
|
2016-05-03 17:33:40 +00:00
|
|
|
|
|
|
|
if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
|
|
|
|
dev_info(dev,
|
2019-06-19 19:53:04 +00:00
|
|
|
"%s : stm_register_device failed, probing deferred\n",
|
|
|
|
desc.name);
|
2016-05-03 17:33:40 +00:00
|
|
|
return -EPROBE_DEFER;
|
|
|
|
}
|
|
|
|
|
2019-06-19 19:53:00 +00:00
|
|
|
pdata = coresight_get_platform_data(dev);
|
|
|
|
if (IS_ERR(pdata)) {
|
|
|
|
ret = PTR_ERR(pdata);
|
|
|
|
goto stm_unregister;
|
|
|
|
}
|
|
|
|
adev->dev.platform_data = pdata;
|
|
|
|
|
2016-08-25 21:19:05 +00:00
|
|
|
desc.type = CORESIGHT_DEV_TYPE_SOURCE;
|
|
|
|
desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
|
|
|
|
desc.ops = &stm_cs_ops;
|
|
|
|
desc.pdata = pdata;
|
|
|
|
desc.dev = dev;
|
|
|
|
desc.groups = coresight_stm_groups;
|
|
|
|
drvdata->csdev = coresight_register(&desc);
|
2016-05-03 17:33:40 +00:00
|
|
|
if (IS_ERR(drvdata->csdev)) {
|
|
|
|
ret = PTR_ERR(drvdata->csdev);
|
|
|
|
goto stm_unregister;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_put(&adev->dev);
|
|
|
|
|
2019-06-19 17:29:15 +00:00
|
|
|
dev_info(&drvdata->csdev->dev, "%s initialized\n",
|
|
|
|
(char *)coresight_get_uci_data(id));
|
2016-05-03 17:33:40 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
stm_unregister:
|
|
|
|
stm_unregister_device(&drvdata->stm);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-01-26 16:58:34 +00:00
|
|
|
static void stm_remove(struct amba_device *adev)
|
2020-09-28 16:34:55 +00:00
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
|
|
|
|
|
|
|
|
coresight_unregister(drvdata->csdev);
|
|
|
|
|
|
|
|
stm_unregister_device(&drvdata->stm);
|
|
|
|
}
|
|
|
|
|
2016-05-03 17:33:40 +00:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int stm_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (drvdata && !IS_ERR(drvdata->atclk))
|
|
|
|
clk_disable_unprepare(drvdata->atclk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (drvdata && !IS_ERR(drvdata->atclk))
|
|
|
|
clk_prepare_enable(drvdata->atclk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct dev_pm_ops stm_dev_pm_ops = {
|
|
|
|
SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
|
|
|
|
};
|
|
|
|
|
2017-08-24 16:36:03 +00:00
|
|
|
static const struct amba_id stm_ids[] = {
|
ARM: 8838/1: drivers: amba: Updates to component identification for driver matching.
The CoreSight specification (ARM IHI 0029E), updates the ID register
requirements for components on an AMBA bus, to cover both traditional
ARM Primecell type devices, and newer CoreSight and other components.
The Peripheral ID (PID) / Component ID (CID) pair is extended in certain
cases to uniquely identify components. CoreSight components related to
a single function can share Peripheral ID values, and must be further
identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI,
PMU and Debug hardware of the A35 all share the same PID.
Bits 15:12 of the CID are defined to be the device class.
Class 0xF remains for PrimeCell and legacy components.
Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
at present.
Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
The specification futher defines which classes of device use the standard
CID/PID pair, and when additional ID registers are required.
This patch introduces the amba_cs_uci_id structure which will be used in
all coresight drivers for indentification via the private data pointer in
the amba_id structure.
Existing drivers that currently use the amba_id->data pointer for private
data are updated to use the amba_cs_uci_id->data pointer. Macros and
inline functions are added to simplify this code.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-02-13 13:41:49 +00:00
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|
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CS_AMBA_ID_DATA(0x000bb962, "STM32"),
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|
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CS_AMBA_ID_DATA(0x000bb963, "STM500"),
|
2016-05-03 17:33:40 +00:00
|
|
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{ 0, 0},
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};
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2020-09-28 16:34:55 +00:00
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|
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MODULE_DEVICE_TABLE(amba, stm_ids);
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2016-05-03 17:33:40 +00:00
|
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static struct amba_driver stm_driver = {
|
|
|
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.drv = {
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|
|
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.name = "coresight-stm",
|
|
|
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.owner = THIS_MODULE,
|
|
|
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.pm = &stm_dev_pm_ops,
|
|
|
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.suppress_bind_attrs = true,
|
|
|
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},
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|
|
.probe = stm_probe,
|
2020-09-28 16:34:55 +00:00
|
|
|
.remove = stm_remove,
|
2016-05-03 17:33:40 +00:00
|
|
|
.id_table = stm_ids,
|
|
|
|
};
|
|
|
|
|
2020-09-28 16:34:55 +00:00
|
|
|
module_amba_driver(stm_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
|
|
|
|
MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|