mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 08:19:28 +00:00
554 lines
14 KiB
C
554 lines
14 KiB
C
![]() |
/*
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* Driver for the Diolan DLN-2 USB-GPIO adapter
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*
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* Copyright (c) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/gpio.h>
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#include <linux/gpio/driver.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/dln2.h>
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#define DLN2_GPIO_ID 0x01
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#define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
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#define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
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#define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
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#define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
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#define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
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#define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
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#define DLN2_GPIO_EVENT_NONE 0
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#define DLN2_GPIO_EVENT_CHANGE 1
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#define DLN2_GPIO_EVENT_LVL_HIGH 2
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#define DLN2_GPIO_EVENT_LVL_LOW 3
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#define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
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#define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
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#define DLN2_GPIO_EVENT_MASK 0x0F
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#define DLN2_GPIO_MAX_PINS 32
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struct dln2_irq_work {
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struct work_struct work;
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struct dln2_gpio *dln2;
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int pin;
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int type;
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};
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struct dln2_gpio {
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struct platform_device *pdev;
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struct gpio_chip gpio;
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/*
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* Cache pin direction to save us one transfer, since the hardware has
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* separate commands to read the in and out values.
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*/
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DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
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DECLARE_BITMAP(irqs_masked, DLN2_GPIO_MAX_PINS);
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DECLARE_BITMAP(irqs_enabled, DLN2_GPIO_MAX_PINS);
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DECLARE_BITMAP(irqs_pending, DLN2_GPIO_MAX_PINS);
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struct dln2_irq_work *irq_work;
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};
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struct dln2_gpio_pin {
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__le16 pin;
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};
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struct dln2_gpio_pin_val {
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__le16 pin __packed;
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u8 value;
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};
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static int dln2_gpio_get_pin_count(struct platform_device *pdev)
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{
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int ret;
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__le16 count;
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int len = sizeof(count);
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ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
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if (ret < 0)
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return ret;
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if (len < sizeof(count))
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return -EPROTO;
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return le16_to_cpu(count);
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}
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static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
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{
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struct dln2_gpio_pin req = {
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.pin = cpu_to_le16(pin),
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};
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return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
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}
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static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
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{
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int ret;
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struct dln2_gpio_pin req = {
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.pin = cpu_to_le16(pin),
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};
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struct dln2_gpio_pin_val rsp;
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int len = sizeof(rsp);
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ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
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if (ret < 0)
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return ret;
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if (len < sizeof(rsp) || req.pin != rsp.pin)
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return -EPROTO;
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return rsp.value;
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}
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static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
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{
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int ret;
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ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
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if (ret < 0)
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return ret;
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return !!ret;
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}
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static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
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{
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int ret;
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ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
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if (ret < 0)
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return ret;
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return !!ret;
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}
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static void dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
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unsigned int pin, int value)
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{
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struct dln2_gpio_pin_val req = {
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.pin = cpu_to_le16(pin),
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.value = value,
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};
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dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
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sizeof(req));
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}
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#define DLN2_GPIO_DIRECTION_IN 0
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#define DLN2_GPIO_DIRECTION_OUT 1
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static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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struct dln2_gpio_pin req = {
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.pin = cpu_to_le16(offset),
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};
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struct dln2_gpio_pin_val rsp;
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int len = sizeof(rsp);
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int ret;
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ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
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if (ret < 0)
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return ret;
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/* cache the pin direction */
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ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
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&req, sizeof(req), &rsp, &len);
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if (ret < 0)
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return ret;
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if (len < sizeof(rsp) || req.pin != rsp.pin) {
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ret = -EPROTO;
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goto out_disable;
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}
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switch (rsp.value) {
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case DLN2_GPIO_DIRECTION_IN:
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clear_bit(offset, dln2->output_enabled);
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return 0;
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case DLN2_GPIO_DIRECTION_OUT:
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set_bit(offset, dln2->output_enabled);
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return 0;
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default:
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ret = -EPROTO;
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goto out_disable;
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}
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out_disable:
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dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
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return ret;
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}
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static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
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}
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static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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if (test_bit(offset, dln2->output_enabled))
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return GPIOF_DIR_OUT;
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return GPIOF_DIR_IN;
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}
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static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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int dir;
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dir = dln2_gpio_get_direction(chip, offset);
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if (dir < 0)
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return dir;
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if (dir == GPIOF_DIR_IN)
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return dln2_gpio_pin_get_in_val(dln2, offset);
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return dln2_gpio_pin_get_out_val(dln2, offset);
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}
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static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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dln2_gpio_pin_set_out_val(dln2, offset, value);
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}
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static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
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unsigned dir)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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struct dln2_gpio_pin_val req = {
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.pin = cpu_to_le16(offset),
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.value = dir,
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};
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int ret;
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ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
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&req, sizeof(req));
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if (ret < 0)
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return ret;
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if (dir == DLN2_GPIO_DIRECTION_OUT)
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set_bit(offset, dln2->output_enabled);
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else
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clear_bit(offset, dln2->output_enabled);
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return ret;
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}
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static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
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}
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static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
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}
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static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
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unsigned debounce)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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__le32 duration = cpu_to_le32(debounce);
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return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
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&duration, sizeof(duration));
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}
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static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
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unsigned type, unsigned period)
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{
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struct {
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__le16 pin;
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u8 type;
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__le16 period;
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} __packed req = {
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.pin = cpu_to_le16(pin),
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.type = type,
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.period = cpu_to_le16(period),
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};
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return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
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&req, sizeof(req));
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}
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static void dln2_irq_work(struct work_struct *w)
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{
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struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work);
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struct dln2_gpio *dln2 = iw->dln2;
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u8 type = iw->type & DLN2_GPIO_EVENT_MASK;
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if (test_bit(iw->pin, dln2->irqs_enabled))
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dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0);
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else
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dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0);
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}
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static void dln2_irq_enable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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set_bit(pin, dln2->irqs_enabled);
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schedule_work(&dln2->irq_work[pin].work);
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}
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static void dln2_irq_disable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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clear_bit(pin, dln2->irqs_enabled);
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schedule_work(&dln2->irq_work[pin].work);
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}
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static void dln2_irq_mask(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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set_bit(pin, dln2->irqs_masked);
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}
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static void dln2_irq_unmask(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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struct device *dev = dln2->gpio.dev;
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int pin = irqd_to_hwirq(irqd);
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if (test_and_clear_bit(pin, dln2->irqs_pending)) {
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int irq;
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irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
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if (!irq) {
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dev_err(dev, "pin %d not mapped to IRQ\n", pin);
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return;
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}
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generic_handle_irq(irq);
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}
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}
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static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_chip dln2_gpio_irqchip = {
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.name = "dln2-irq",
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.irq_enable = dln2_irq_enable,
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.irq_disable = dln2_irq_disable,
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.irq_mask = dln2_irq_mask,
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.irq_unmask = dln2_irq_unmask,
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.irq_set_type = dln2_irq_set_type,
|
||
|
};
|
||
|
|
||
|
static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
|
||
|
const void *data, int len)
|
||
|
{
|
||
|
int pin, irq;
|
||
|
const struct {
|
||
|
__le16 count;
|
||
|
__u8 type;
|
||
|
__le16 pin;
|
||
|
__u8 value;
|
||
|
} __packed *event = data;
|
||
|
struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
|
||
|
|
||
|
if (len < sizeof(*event)) {
|
||
|
dev_err(dln2->gpio.dev, "short event message\n");
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
pin = le16_to_cpu(event->pin);
|
||
|
if (pin >= dln2->gpio.ngpio) {
|
||
|
dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
|
||
|
if (!irq) {
|
||
|
dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
if (!test_bit(pin, dln2->irqs_enabled))
|
||
|
return;
|
||
|
if (test_bit(pin, dln2->irqs_masked)) {
|
||
|
set_bit(pin, dln2->irqs_pending);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
switch (dln2->irq_work[pin].type) {
|
||
|
case DLN2_GPIO_EVENT_CHANGE_RISING:
|
||
|
if (event->value)
|
||
|
generic_handle_irq(irq);
|
||
|
break;
|
||
|
case DLN2_GPIO_EVENT_CHANGE_FALLING:
|
||
|
if (!event->value)
|
||
|
generic_handle_irq(irq);
|
||
|
break;
|
||
|
default:
|
||
|
generic_handle_irq(irq);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static int dln2_gpio_probe(struct platform_device *pdev)
|
||
|
{
|
||
|
struct dln2_gpio *dln2;
|
||
|
struct device *dev = &pdev->dev;
|
||
|
int pins;
|
||
|
int i, ret;
|
||
|
|
||
|
pins = dln2_gpio_get_pin_count(pdev);
|
||
|
if (pins < 0) {
|
||
|
dev_err(dev, "failed to get pin count: %d\n", pins);
|
||
|
return pins;
|
||
|
}
|
||
|
if (pins > DLN2_GPIO_MAX_PINS) {
|
||
|
pins = DLN2_GPIO_MAX_PINS;
|
||
|
dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
|
||
|
}
|
||
|
|
||
|
dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
|
||
|
if (!dln2)
|
||
|
return -ENOMEM;
|
||
|
|
||
|
dln2->irq_work = devm_kcalloc(&pdev->dev, pins,
|
||
|
sizeof(struct dln2_irq_work), GFP_KERNEL);
|
||
|
if (!dln2->irq_work)
|
||
|
return -ENOMEM;
|
||
|
for (i = 0; i < pins; i++) {
|
||
|
INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work);
|
||
|
dln2->irq_work[i].pin = i;
|
||
|
dln2->irq_work[i].dln2 = dln2;
|
||
|
}
|
||
|
|
||
|
dln2->pdev = pdev;
|
||
|
|
||
|
dln2->gpio.label = "dln2";
|
||
|
dln2->gpio.dev = dev;
|
||
|
dln2->gpio.owner = THIS_MODULE;
|
||
|
dln2->gpio.base = -1;
|
||
|
dln2->gpio.ngpio = pins;
|
||
|
dln2->gpio.exported = true;
|
||
|
dln2->gpio.can_sleep = true;
|
||
|
dln2->gpio.irq_not_threaded = true;
|
||
|
dln2->gpio.set = dln2_gpio_set;
|
||
|
dln2->gpio.get = dln2_gpio_get;
|
||
|
dln2->gpio.request = dln2_gpio_request;
|
||
|
dln2->gpio.free = dln2_gpio_free;
|
||
|
dln2->gpio.get_direction = dln2_gpio_get_direction;
|
||
|
dln2->gpio.direction_input = dln2_gpio_direction_input;
|
||
|
dln2->gpio.direction_output = dln2_gpio_direction_output;
|
||
|
dln2->gpio.set_debounce = dln2_gpio_set_debounce;
|
||
|
|
||
|
platform_set_drvdata(pdev, dln2);
|
||
|
|
||
|
ret = gpiochip_add(&dln2->gpio);
|
||
|
if (ret < 0) {
|
||
|
dev_err(dev, "failed to add gpio chip: %d\n", ret);
|
||
|
goto out;
|
||
|
}
|
||
|
|
||
|
ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
|
||
|
handle_simple_irq, IRQ_TYPE_NONE);
|
||
|
if (ret < 0) {
|
||
|
dev_err(dev, "failed to add irq chip: %d\n", ret);
|
||
|
goto out_gpiochip_remove;
|
||
|
}
|
||
|
|
||
|
ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
|
||
|
dln2_gpio_event);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "failed to register event cb: %d\n", ret);
|
||
|
goto out_gpiochip_remove;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
|
||
|
out_gpiochip_remove:
|
||
|
gpiochip_remove(&dln2->gpio);
|
||
|
out:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static int dln2_gpio_remove(struct platform_device *pdev)
|
||
|
{
|
||
|
struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
|
||
|
int i;
|
||
|
|
||
|
dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
|
||
|
for (i = 0; i < dln2->gpio.ngpio; i++)
|
||
|
flush_work(&dln2->irq_work[i].work);
|
||
|
gpiochip_remove(&dln2->gpio);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static struct platform_driver dln2_gpio_driver = {
|
||
|
.driver.name = "dln2-gpio",
|
||
|
.probe = dln2_gpio_probe,
|
||
|
.remove = dln2_gpio_remove,
|
||
|
};
|
||
|
|
||
|
module_platform_driver(dln2_gpio_driver);
|
||
|
|
||
|
MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
|
||
|
MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
|
||
|
MODULE_LICENSE("GPL v2");
|
||
|
MODULE_ALIAS("platform:dln2-gpio");
|