2006-08-29 22:12:40 +00:00
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/*
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* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
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*
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* This driver is heavily based upon:
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*
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* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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* Portions Copyright (C) 2003 Red Hat Inc
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*
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*
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* TODO
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* Maybe PLL mode
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* Look into engine reset on timeout errors. Should not be
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* required.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_hpt366"
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2008-02-26 21:35:54 +00:00
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#define DRV_VERSION "0.6.2"
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2006-08-29 22:12:40 +00:00
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struct hpt_clock {
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u8 xfer_speed;
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u32 timing;
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};
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/* key for bus clock timings
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* bit
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* 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
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* register access.
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* 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
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* register access.
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* 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
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* during task file register access.
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* 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
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* xfer.
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* 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
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* register access.
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* 28 UDMA enable
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* 29 DMA enable
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* 30 PIO_MST enable. if set, the chip is in bus master mode during
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* PIO.
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* 31 FIFO enable.
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*/
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static const struct hpt_clock hpt366_40[] = {
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{ XFER_UDMA_4, 0x900fd943 },
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{ XFER_UDMA_3, 0x900ad943 },
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{ XFER_UDMA_2, 0x900bd943 },
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{ XFER_UDMA_1, 0x9008d943 },
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{ XFER_UDMA_0, 0x9008d943 },
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{ XFER_MW_DMA_2, 0xa008d943 },
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{ XFER_MW_DMA_1, 0xa010d955 },
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{ XFER_MW_DMA_0, 0xa010d9fc },
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{ XFER_PIO_4, 0xc008d963 },
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{ XFER_PIO_3, 0xc010d974 },
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{ XFER_PIO_2, 0xc010d997 },
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{ XFER_PIO_1, 0xc010d9c7 },
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{ XFER_PIO_0, 0xc018d9d9 },
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{ 0, 0x0120d9d9 }
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};
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static const struct hpt_clock hpt366_33[] = {
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{ XFER_UDMA_4, 0x90c9a731 },
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{ XFER_UDMA_3, 0x90cfa731 },
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{ XFER_UDMA_2, 0x90caa731 },
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{ XFER_UDMA_1, 0x90cba731 },
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{ XFER_UDMA_0, 0x90c8a731 },
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{ XFER_MW_DMA_2, 0xa0c8a731 },
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{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
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{ XFER_MW_DMA_0, 0xa0c8a797 },
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{ XFER_PIO_4, 0xc0c8a731 },
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{ XFER_PIO_3, 0xc0c8a742 },
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{ XFER_PIO_2, 0xc0d0a753 },
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{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
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{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
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{ 0, 0x0120a7a7 }
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};
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static const struct hpt_clock hpt366_25[] = {
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{ XFER_UDMA_4, 0x90c98521 },
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{ XFER_UDMA_3, 0x90cf8521 },
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{ XFER_UDMA_2, 0x90cf8521 },
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{ XFER_UDMA_1, 0x90cb8521 },
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{ XFER_UDMA_0, 0x90cb8521 },
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{ XFER_MW_DMA_2, 0xa0ca8521 },
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{ XFER_MW_DMA_1, 0xa0ca8532 },
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{ XFER_MW_DMA_0, 0xa0ca8575 },
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{ XFER_PIO_4, 0xc0ca8521 },
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{ XFER_PIO_3, 0xc0ca8532 },
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{ XFER_PIO_2, 0xc0ca8542 },
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{ XFER_PIO_1, 0xc0d08572 },
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{ XFER_PIO_0, 0xc0d08585 },
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{ 0, 0x01208585 }
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};
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static const char *bad_ata33[] = {
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"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
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"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
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"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
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"Maxtor 90510D4",
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"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
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"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
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"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
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NULL
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};
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static const char *bad_ata66_4[] = {
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"IBM-DTLA-307075",
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"IBM-DTLA-307060",
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"IBM-DTLA-307045",
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"IBM-DTLA-307030",
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"IBM-DTLA-307020",
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"IBM-DTLA-307015",
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"IBM-DTLA-305040",
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"IBM-DTLA-305030",
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"IBM-DTLA-305020",
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"IC35L010AVER07-0",
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"IC35L020AVER07-0",
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"IC35L030AVER07-0",
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"IC35L040AVER07-0",
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"IC35L060AVER07-0",
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"WDC AC310200R",
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NULL
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};
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static const char *bad_ata66_3[] = {
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"WDC AC310200R",
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NULL
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};
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static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
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{
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2007-01-02 11:19:40 +00:00
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unsigned char model_num[ATA_ID_PROD_LEN + 1];
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2006-08-29 22:12:40 +00:00
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int i = 0;
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2007-01-02 11:19:40 +00:00
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ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
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2006-08-29 22:12:40 +00:00
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2007-01-02 11:19:40 +00:00
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while (list[i] != NULL) {
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if (!strcmp(list[i], model_num)) {
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2006-08-31 04:03:49 +00:00
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printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
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2006-08-29 22:12:40 +00:00
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modestr, list[i]);
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return 1;
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}
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i++;
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}
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return 0;
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}
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/**
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* hpt366_filter - mode selection filter
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* @adev: ATA device
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*
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* Block UDMA on devices that cause trouble with this controller.
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*/
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2006-08-31 04:03:49 +00:00
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2007-03-09 14:34:07 +00:00
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static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
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2006-08-29 22:12:40 +00:00
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{
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if (adev->class == ATA_DEV_ATA) {
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if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
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mask &= ~ATA_MASK_UDMA;
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if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
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2008-02-26 21:35:54 +00:00
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mask &= ~(0xF8 << ATA_SHIFT_UDMA);
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2006-08-29 22:12:40 +00:00
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if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
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2008-02-26 21:35:54 +00:00
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mask &= ~(0xF0 << ATA_SHIFT_UDMA);
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2006-08-29 22:12:40 +00:00
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}
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2008-04-07 13:47:16 +00:00
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return ata_bmdma_mode_filter(adev, mask);
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2006-08-29 22:12:40 +00:00
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}
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/**
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* hpt36x_find_mode - reset the hpt36x bus
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* @ap: ATA port
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* @speed: transfer mode
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*
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* Return the 32bit register programming information for this channel
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* that matches the speed provided.
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*/
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
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{
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struct hpt_clock *clocks = ap->host->private_data;
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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while(clocks->xfer_speed) {
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if (clocks->xfer_speed == speed)
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return clocks->timing;
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clocks++;
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}
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BUG();
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return 0xffffffffU; /* silence compiler warning */
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}
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2006-08-31 04:03:49 +00:00
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2007-03-08 19:34:28 +00:00
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static int hpt36x_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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2008-12-09 08:13:19 +00:00
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u8 ata66;
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2007-03-08 19:34:28 +00:00
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2008-12-09 08:13:19 +00:00
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/*
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* Each channel of pata_hpt366 occupies separate PCI function
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* as the primary channel and bit1 indicates the cable type.
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*/
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2007-03-08 19:34:28 +00:00
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pci_read_config_byte(pdev, 0x5A, &ata66);
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2008-12-09 08:13:19 +00:00
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if (ata66 & 2)
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2007-03-08 19:34:28 +00:00
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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2006-08-29 22:12:40 +00:00
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/**
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* hpt366_set_piomode - PIO setup
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* @ap: ATA interface
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* @adev: device on the interface
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*
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2006-08-31 04:03:49 +00:00
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* Perform PIO mode setup.
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2006-08-29 22:12:40 +00:00
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*/
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1, addr2;
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u32 reg;
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u32 mode;
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u8 fast;
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addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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addr2 = 0x51 + 4 * ap->port_no;
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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if (fast & 0x80) {
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fast &= ~0x80;
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pci_write_config_byte(pdev, addr2, fast);
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}
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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pci_read_config_dword(pdev, addr1, ®);
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mode = hpt36x_find_mode(ap, adev->pio_mode);
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mode &= ~0x8000000; /* No FIFO in PIO */
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mode &= ~0x30070000; /* Leave config bits alone */
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reg &= 0x30070000; /* Strip timing bits */
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pci_write_config_dword(pdev, addr1, reg | mode);
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}
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/**
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* hpt366_set_dmamode - DMA timing setup
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* @ap: ATA interface
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* @adev: Device being configured
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*
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* Set up the channel for MWDMA or UDMA modes. Much the same as with
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* PIO, load the mode number and then set MWDMA or UDMA flag.
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*/
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1, addr2;
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u32 reg;
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u32 mode;
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u8 fast;
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addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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addr2 = 0x51 + 4 * ap->port_no;
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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if (fast & 0x80) {
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fast &= ~0x80;
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pci_write_config_byte(pdev, addr2, fast);
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}
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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pci_read_config_dword(pdev, addr1, ®);
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mode = hpt36x_find_mode(ap, adev->dma_mode);
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mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
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mode &= ~0xC0000000; /* Leave config bits alone */
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reg &= 0xC0000000; /* Strip timing bits */
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pci_write_config_dword(pdev, addr1, reg | mode);
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}
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static struct scsi_host_template hpt36x_sht = {
|
2008-03-25 03:22:49 +00:00
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ATA_BMDMA_SHT(DRV_NAME),
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2006-08-29 22:12:40 +00:00
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};
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/*
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* Configuration for HPT366/68
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*/
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2006-08-31 04:03:49 +00:00
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2006-08-29 22:12:40 +00:00
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static struct ata_port_operations hpt366_port_ops = {
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libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 03:22:49 +00:00
|
|
|
.inherits = &ata_bmdma_port_ops,
|
|
|
|
.cable_detect = hpt36x_cable_detect,
|
|
|
|
.mode_filter = hpt366_filter,
|
2006-08-29 22:12:40 +00:00
|
|
|
.set_piomode = hpt366_set_piomode,
|
|
|
|
.set_dmamode = hpt366_set_dmamode,
|
2006-08-31 04:03:49 +00:00
|
|
|
};
|
2006-08-29 22:12:40 +00:00
|
|
|
|
2006-11-27 16:24:15 +00:00
|
|
|
/**
|
|
|
|
* hpt36x_init_chipset - common chip setup
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* Perform the chip setup work that must be done at both init and
|
|
|
|
* resume time
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void hpt36x_init_chipset(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u8 drive_fast;
|
|
|
|
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
|
|
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
|
|
|
|
pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
|
|
|
|
pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
|
|
|
|
|
|
|
|
pci_read_config_byte(dev, 0x51, &drive_fast);
|
|
|
|
if (drive_fast & 0x80)
|
|
|
|
pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
|
|
|
|
}
|
|
|
|
|
2006-08-29 22:12:40 +00:00
|
|
|
/**
|
|
|
|
* hpt36x_init_one - Initialise an HPT366/368
|
|
|
|
* @dev: PCI device
|
|
|
|
* @id: Entry in match table
|
|
|
|
*
|
|
|
|
* Initialise an HPT36x device. There are some interesting complications
|
|
|
|
* here. Firstly the chip may report 366 and be one of several variants.
|
|
|
|
* Secondly all the timings depend on the clock for the chip which we must
|
|
|
|
* detect and look up
|
|
|
|
*
|
|
|
|
* This is the known chip mappings. It may be missing a couple of later
|
|
|
|
* releases.
|
|
|
|
*
|
|
|
|
* Chip version PCI Rev Notes
|
|
|
|
* HPT366 4 (HPT366) 0 UDMA66
|
|
|
|
* HPT366 4 (HPT366) 1 UDMA66
|
|
|
|
* HPT368 4 (HPT366) 2 UDMA66
|
|
|
|
* HPT37x/30x 4 (HPT366) 3+ Other driver
|
|
|
|
*
|
|
|
|
*/
|
2006-08-31 04:03:49 +00:00
|
|
|
|
2006-08-29 22:12:40 +00:00
|
|
|
static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
{
|
2007-05-04 10:43:58 +00:00
|
|
|
static const struct ata_port_info info_hpt366 = {
|
2007-05-28 10:59:48 +00:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2006-08-29 22:12:40 +00:00
|
|
|
.pio_mask = 0x1f,
|
|
|
|
.mwdma_mask = 0x07,
|
2007-07-09 16:16:50 +00:00
|
|
|
.udma_mask = ATA_UDMA4,
|
2006-08-29 22:12:40 +00:00
|
|
|
.port_ops = &hpt366_port_ops
|
|
|
|
};
|
2008-03-25 03:22:49 +00:00
|
|
|
const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
|
2006-08-29 22:12:40 +00:00
|
|
|
|
2008-03-25 03:22:49 +00:00
|
|
|
void *hpriv = NULL;
|
2006-08-29 22:12:40 +00:00
|
|
|
u32 class_rev;
|
|
|
|
u32 reg1;
|
2008-03-25 03:22:47 +00:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = pcim_enable_device(dev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2006-08-29 22:12:40 +00:00
|
|
|
|
|
|
|
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
|
|
|
|
class_rev &= 0xFF;
|
2006-08-31 04:03:49 +00:00
|
|
|
|
2006-08-29 22:12:40 +00:00
|
|
|
/* May be a later chip in disguise. Check */
|
|
|
|
/* Newer chips are not in the HPT36x driver. Ignore them */
|
|
|
|
if (class_rev > 2)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2006-11-27 16:24:15 +00:00
|
|
|
hpt36x_init_chipset(dev);
|
2006-08-29 22:12:40 +00:00
|
|
|
|
|
|
|
pci_read_config_dword(dev, 0x40, ®1);
|
2006-08-31 04:03:49 +00:00
|
|
|
|
2006-08-29 22:12:40 +00:00
|
|
|
/* PCI clocking determines the ATA timing values to use */
|
|
|
|
/* info_hpt366 is safe against re-entry so we can scribble on it */
|
2006-10-03 08:14:03 +00:00
|
|
|
switch((reg1 & 0x700) >> 8) {
|
2008-12-08 09:48:42 +00:00
|
|
|
case 9:
|
2008-03-25 03:22:49 +00:00
|
|
|
hpriv = &hpt366_40;
|
2006-08-29 22:12:40 +00:00
|
|
|
break;
|
2008-12-08 09:48:42 +00:00
|
|
|
case 5:
|
2008-03-25 03:22:49 +00:00
|
|
|
hpriv = &hpt366_25;
|
2006-08-29 22:12:40 +00:00
|
|
|
break;
|
|
|
|
default:
|
2008-03-25 03:22:49 +00:00
|
|
|
hpriv = &hpt366_33;
|
2006-08-29 22:12:40 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* Now kick off ATA set up */
|
2008-04-07 13:47:16 +00:00
|
|
|
return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
|
2006-08-29 22:12:40 +00:00
|
|
|
}
|
|
|
|
|
2007-03-02 08:31:26 +00:00
|
|
|
#ifdef CONFIG_PM
|
2006-11-27 16:24:15 +00:00
|
|
|
static int hpt36x_reinit_one(struct pci_dev *dev)
|
|
|
|
{
|
2008-03-25 03:22:47 +00:00
|
|
|
struct ata_host *host = dev_get_drvdata(&dev->dev);
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = ata_pci_device_do_resume(dev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2006-11-27 16:24:15 +00:00
|
|
|
hpt36x_init_chipset(dev);
|
2008-03-25 03:22:47 +00:00
|
|
|
ata_host_resume(host);
|
|
|
|
return 0;
|
2006-11-27 16:24:15 +00:00
|
|
|
}
|
2007-03-02 08:31:26 +00:00
|
|
|
#endif
|
2006-11-27 16:24:15 +00:00
|
|
|
|
2006-09-29 00:21:59 +00:00
|
|
|
static const struct pci_device_id hpt36x[] = {
|
|
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
|
|
|
|
{ },
|
2006-08-29 22:12:40 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver hpt36x_pci_driver = {
|
2006-09-29 00:21:59 +00:00
|
|
|
.name = DRV_NAME,
|
2006-08-29 22:12:40 +00:00
|
|
|
.id_table = hpt36x,
|
|
|
|
.probe = hpt36x_init_one,
|
2006-11-27 16:24:15 +00:00
|
|
|
.remove = ata_pci_remove_one,
|
2007-03-02 08:31:26 +00:00
|
|
|
#ifdef CONFIG_PM
|
2006-11-27 16:24:15 +00:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = hpt36x_reinit_one,
|
2007-03-02 08:31:26 +00:00
|
|
|
#endif
|
2006-08-29 22:12:40 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init hpt36x_init(void)
|
|
|
|
{
|
|
|
|
return pci_register_driver(&hpt36x_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit hpt36x_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&hpt36x_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, hpt36x);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
|
|
module_init(hpt36x_init);
|
|
|
|
module_exit(hpt36x_exit);
|