2011-01-20 17:50:14 +00:00
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/*
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* Definitions for the NVM Express interface
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2014-04-11 14:37:39 +00:00
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* Copyright (c) 2011-2014, Intel Corporation.
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2011-01-20 17:50:14 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _LINUX_NVME_H
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#define _LINUX_NVME_H
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2013-06-25 19:14:56 +00:00
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#include <uapi/linux/nvme.h>
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#include <linux/pci.h>
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#include <linux/kref.h>
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2014-11-04 15:20:14 +00:00
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#include <linux/blk-mq.h>
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2011-01-20 17:50:14 +00:00
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struct nvme_bar {
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__u64 cap; /* Controller Capabilities */
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__u32 vs; /* Version */
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2011-02-14 17:20:15 +00:00
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__u32 intms; /* Interrupt Mask Set */
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__u32 intmc; /* Interrupt Mask Clear */
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2011-01-20 17:50:14 +00:00
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__u32 cc; /* Controller Configuration */
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2011-02-14 17:20:15 +00:00
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__u32 rsvd1; /* Reserved */
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2011-01-20 17:50:14 +00:00
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__u32 csts; /* Controller Status */
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2015-08-10 21:20:41 +00:00
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__u32 nssr; /* Subsystem Reset */
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2011-01-20 17:50:14 +00:00
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__u32 aqa; /* Admin Queue Attributes */
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__u64 asq; /* Admin SQ Base Address */
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__u64 acq; /* Admin CQ Base Address */
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2015-07-20 16:14:09 +00:00
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__u32 cmbloc; /* Controller Memory Buffer Location */
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__u32 cmbsz; /* Controller Memory Buffer Size */
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2011-01-20 17:50:14 +00:00
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};
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2012-07-27 17:57:23 +00:00
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#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
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2011-04-19 19:04:20 +00:00
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#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
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2011-10-20 21:00:41 +00:00
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#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
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2015-08-10 21:20:40 +00:00
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#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
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2012-07-26 17:29:57 +00:00
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#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
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2014-06-23 17:34:01 +00:00
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#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
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2011-04-19 19:04:20 +00:00
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2015-07-20 16:14:09 +00:00
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#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
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#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
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#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
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#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
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#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
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#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
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#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
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#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
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#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
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2011-01-20 17:50:14 +00:00
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enum {
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NVME_CC_ENABLE = 1 << 0,
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NVME_CC_CSS_NVM = 0 << 4,
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NVME_CC_MPS_SHIFT = 7,
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NVME_CC_ARB_RR = 0 << 11,
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NVME_CC_ARB_WRRU = 1 << 11,
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2011-03-22 19:55:45 +00:00
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NVME_CC_ARB_VS = 7 << 11,
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NVME_CC_SHN_NONE = 0 << 14,
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NVME_CC_SHN_NORMAL = 1 << 14,
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NVME_CC_SHN_ABRUPT = 2 << 14,
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2013-07-15 21:02:22 +00:00
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NVME_CC_SHN_MASK = 3 << 14,
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2011-03-22 19:55:45 +00:00
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NVME_CC_IOSQES = 6 << 16,
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NVME_CC_IOCQES = 4 << 20,
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2011-01-20 17:50:14 +00:00
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NVME_CSTS_RDY = 1 << 0,
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NVME_CSTS_CFS = 1 << 1,
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2015-08-10 21:20:40 +00:00
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NVME_CSTS_NSSRO = 1 << 4,
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2011-01-20 17:50:14 +00:00
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NVME_CSTS_SHST_NORMAL = 0 << 2,
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NVME_CSTS_SHST_OCCUR = 1 << 2,
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NVME_CSTS_SHST_CMPLT = 2 << 2,
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2013-07-15 21:02:22 +00:00
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NVME_CSTS_SHST_MASK = 3 << 2,
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2011-01-20 17:50:14 +00:00
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};
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2014-06-04 03:04:30 +00:00
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extern unsigned char nvme_io_timeout;
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#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
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2013-03-05 01:40:57 +00:00
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/*
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* Represents an NVM Express device. Each nvme_dev is a PCI function.
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*/
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struct nvme_dev {
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struct list_head node;
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2014-11-04 15:20:14 +00:00
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struct nvme_queue **queues;
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struct request_queue *admin_q;
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struct blk_mq_tag_set tagset;
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struct blk_mq_tag_set admin_tagset;
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2013-03-05 01:40:57 +00:00
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u32 __iomem *dbs;
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2015-05-22 09:12:39 +00:00
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struct device *dev;
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2013-03-05 01:40:57 +00:00
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struct dma_pool *prp_page_pool;
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struct dma_pool *prp_small_pool;
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int instance;
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2014-03-24 16:46:25 +00:00
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unsigned queue_count;
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unsigned online_queues;
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unsigned max_qid;
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int q_depth;
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2013-09-10 03:25:37 +00:00
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u32 db_stride;
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2013-03-05 01:40:57 +00:00
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u32 ctrl_config;
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struct msix_entry *entry;
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struct nvme_bar __iomem *bar;
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struct list_head namespaces;
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2013-02-19 17:17:58 +00:00
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struct kref kref;
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2015-02-03 18:21:42 +00:00
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struct device *device;
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2014-03-07 15:24:49 +00:00
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work_func_t reset_workfn;
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2013-12-10 20:10:36 +00:00
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struct work_struct reset_work;
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2015-02-12 22:33:00 +00:00
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struct work_struct probe_work;
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2015-06-01 20:28:14 +00:00
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struct work_struct scan_work;
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2013-02-19 17:17:58 +00:00
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char name[12];
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2013-03-05 01:40:57 +00:00
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char serial[20];
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char model[40];
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char firmware_rev[8];
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2015-08-10 21:20:40 +00:00
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bool subsystem;
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2013-03-05 01:40:57 +00:00
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u32 max_hw_sectors;
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2013-04-09 23:13:20 +00:00
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u32 stripe_size;
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2014-06-23 17:34:01 +00:00
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u32 page_size;
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2015-07-20 16:14:09 +00:00
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void __iomem *cmb;
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dma_addr_t cmb_dma_addr;
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u64 cmb_size;
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u32 cmbsz;
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2013-03-05 01:40:57 +00:00
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u16 oncs;
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2013-12-10 20:10:38 +00:00
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u16 abort_limit;
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2014-06-18 19:58:57 +00:00
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u8 event_limit;
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2014-04-29 17:41:28 +00:00
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u8 vwc;
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2013-03-05 01:40:57 +00:00
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};
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/*
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* An NVM Express namespace is equivalent to a SCSI LUN
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*/
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struct nvme_ns {
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struct list_head list;
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struct nvme_dev *dev;
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struct request_queue *queue;
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struct gendisk *disk;
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2013-07-08 21:26:25 +00:00
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unsigned ns_id;
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2013-03-05 01:40:57 +00:00
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int lba_shift;
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2015-04-07 22:57:19 +00:00
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u16 ms;
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bool ext;
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u8 pi_type;
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2013-03-05 01:40:58 +00:00
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u64 mode_select_num_blocks;
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u32 mode_select_block_len;
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2013-03-05 01:40:57 +00:00
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};
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/*
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* The nvme_iod describes the data in an I/O, including the list of PRP
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* entries. You can't see it in this data structure because C doesn't let
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* me express that. Use nvme_alloc_iod to ensure there's enough space
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* allocated to store the PRP list.
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*/
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struct nvme_iod {
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2015-01-22 19:07:58 +00:00
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unsigned long private; /* For the use of the submitter of the I/O */
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2013-03-05 01:40:57 +00:00
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int npages; /* In the PRP list. 0 means small pool in use */
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int offset; /* Of PRP list */
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int nents; /* Used in scatterlist */
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int length; /* Of data, in bytes */
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dma_addr_t first_dma;
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NVMe: Metadata format support
Adds support for NVMe metadata formats and exposes block devices for
all namespaces regardless of their format. Namespace formats that are
unusable will have disk capacity set to 0, but a handle to the block
device is created to simplify device management. A namespace is not
usable when the format requires host interleave block and metadata in
single buffer, has no provisioned storage, or has better data but failed
to register with blk integrity.
The namespace has to be scanned in two phases to support separate
metadata formats. The first establishes the sector size and capacity
prior to invoking add_disk. If metadata is required, the capacity will
be temporarilly set to 0 until it can be revalidated and registered with
the integrity extenstions after add_disk completes.
The driver relies on the integrity extensions to provide the metadata
buffer. NVMe requires this be a single physically contiguous region,
so only one integrity segment is allowed per command. If the metadata
is used for T10 PI, the driver provides mappings to save and restore
the reftag physical block translation. The driver provides no-op
functions for generate and verify if metadata is not used for protection
information. This way the setup is always provided by the block layer.
If a request does not supply a required metadata buffer, the command
is failed with bad address. This could only happen if a user manually
disables verify/generate on such a disk. The only exception to where
this is okay is if the controller is capable of stripping/generating
the metadata, which is possible on some types of formats.
The metadata scatter gather list now occupies the spot in the nvme_iod
that used to be used to link retryable IOD's, but we don't do that
anymore, so the field was unused.
Signed-off-by: Keith Busch <keith.busch@intel.com>
2015-02-19 20:39:03 +00:00
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struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
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2013-03-05 01:40:57 +00:00
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struct scatterlist sg[0];
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};
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2013-03-05 01:40:58 +00:00
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2013-03-28 01:28:22 +00:00
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static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
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{
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return (sector >> (ns->lba_shift - 9));
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}
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2015-05-22 09:12:46 +00:00
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int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
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void *buf, unsigned bufflen);
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int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
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void *buffer, void __user *ubuffer, unsigned bufflen,
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u32 *result, unsigned timeout);
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int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id);
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int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
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struct nvme_id_ns **id);
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int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log);
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2013-03-05 01:40:58 +00:00
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int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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dma_addr_t dma_addr, u32 *result);
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int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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dma_addr_t dma_addr, u32 *result);
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struct sg_io_hdr;
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int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
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2013-10-23 19:07:34 +00:00
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int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
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2013-03-05 01:40:58 +00:00
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int nvme_sg_get_version_num(int __user *ip);
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2011-01-20 17:50:14 +00:00
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#endif /* _LINUX_NVME_H */
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