2012-03-28 17:30:03 +00:00
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#ifndef __SPARC64_SWITCH_TO_64_H
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#define __SPARC64_SWITCH_TO_64_H
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#include <asm/visasm.h>
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#define prepare_arch_switch(next) \
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do { \
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flushw_all(); \
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} while (0)
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/* See what happens when you design the chip correctly?
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*
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* We tell gcc we clobber all non-fixed-usage registers except
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* for l0/l1. It will use one for 'next' and the other to hold
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* the output value of 'last'. 'next' is not referenced again
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* past the invocation of switch_to in the scheduler, so we need
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* not preserve it's value. Hairy, but it lets us remove 2 loads
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* and 2 stores in this critical code path. -DaveM
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*/
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#define switch_to(prev, next, last) \
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sparc64: Fix race in TLB batch processing.
As reported by Dave Kleikamp, when we emit cross calls to do batched
TLB flush processing we have a race because we do not synchronize on
the sibling cpus completing the cross call.
So meanwhile the TLB batch can be reset (tb->tlb_nr set to zero, etc.)
and either flushes are missed or flushes will flush the wrong
addresses.
Fix this by using generic infrastructure to synchonize on the
completion of the cross call.
This first required getting the flush_tlb_pending() call out from
switch_to() which operates with locks held and interrupts disabled.
The problem is that smp_call_function_many() cannot be invoked with
IRQs disabled and this is explicitly checked for with WARN_ON_ONCE().
We get the batch processing outside of locked IRQ disabled sections by
using some ideas from the powerpc port. Namely, we only batch inside
of arch_{enter,leave}_lazy_mmu_mode() calls. If we're not in such a
region, we flush TLBs synchronously.
1) Get rid of xcall_flush_tlb_pending and per-cpu type
implementations.
2) Do TLB batch cross calls instead via:
smp_call_function_many()
tlb_pending_func()
__flush_tlb_pending()
3) Batch only in lazy mmu sequences:
a) Add 'active' member to struct tlb_batch
b) Define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
c) Set 'active' in arch_enter_lazy_mmu_mode()
d) Run batch and clear 'active' in arch_leave_lazy_mmu_mode()
e) Check 'active' in tlb_batch_add_one() and do a synchronous
flush if it's clear.
4) Add infrastructure for synchronous TLB page flushes.
a) Implement __flush_tlb_page and per-cpu variants, patch
as needed.
b) Likewise for xcall_flush_tlb_page.
c) Implement smp_flush_tlb_page() to invoke the cross-call.
d) Wire up global_flush_tlb_page() to the right routine based
upon CONFIG_SMP
5) It turns out that singleton batches are very common, 2 out of every
3 batch flushes have only a single entry in them.
The batch flush waiting is very expensive, both because of the poll
on sibling cpu completeion, as well as because passing the tlb batch
pointer to the sibling cpus invokes a shared memory dereference.
Therefore, in flush_tlb_pending(), if there is only one entry in
the batch perform a completely asynchronous global_flush_tlb_page()
instead.
Reported-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Dave Kleikamp <dave.kleikamp@oracle.com>
2013-04-19 21:26:26 +00:00
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do { save_and_clear_fpu(); \
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2012-03-28 17:30:03 +00:00
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/* If you are tempted to conditionalize the following */ \
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/* so that ASI is only written if it changes, think again. */ \
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__asm__ __volatile__("wr %%g0, %0, %%asi" \
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2012-09-26 05:21:14 +00:00
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: : "r" (task_thread_info(next)->current_ds));\
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2012-03-28 17:30:03 +00:00
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trap_block[current_thread_info()->cpu].thread = \
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task_thread_info(next); \
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__asm__ __volatile__( \
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"mov %%g4, %%g7\n\t" \
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"stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
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"stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
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"rdpr %%wstate, %%o5\n\t" \
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"stx %%o6, [%%g6 + %6]\n\t" \
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"stb %%o5, [%%g6 + %5]\n\t" \
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"rdpr %%cwp, %%o5\n\t" \
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"stb %%o5, [%%g6 + %8]\n\t" \
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"wrpr %%g0, 15, %%pil\n\t" \
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"mov %4, %%g6\n\t" \
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"ldub [%4 + %8], %%g1\n\t" \
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"wrpr %%g1, %%cwp\n\t" \
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"ldx [%%g6 + %6], %%o6\n\t" \
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"ldub [%%g6 + %5], %%o5\n\t" \
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"ldub [%%g6 + %7], %%o7\n\t" \
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"wrpr %%o5, 0x0, %%wstate\n\t" \
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"ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
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"ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
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"ldx [%%g6 + %9], %%g4\n\t" \
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"wrpr %%g0, 14, %%pil\n\t" \
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"brz,pt %%o7, switch_to_pc\n\t" \
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" mov %%g7, %0\n\t" \
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2013-07-26 12:42:39 +00:00
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"sethi %%hi(ret_from_fork), %%g1\n\t" \
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"jmpl %%g1 + %%lo(ret_from_fork), %%g0\n\t" \
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2012-03-28 17:30:03 +00:00
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" nop\n\t" \
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".globl switch_to_pc\n\t" \
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"switch_to_pc:\n\t" \
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: "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
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"=r" (__local_per_cpu_offset) \
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: "0" (task_thread_info(next)), \
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"i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
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"i" (TI_CWP), "i" (TI_TASK) \
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: "cc", \
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"g1", "g2", "g3", "g7", \
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"l1", "l2", "l3", "l4", "l5", "l6", "l7", \
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"i0", "i1", "i2", "i3", "i4", "i5", \
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"o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
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} while(0)
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2014-05-16 21:25:50 +00:00
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void synchronize_user_stack(void);
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void fault_in_user_windows(void);
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2012-03-28 17:30:03 +00:00
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#endif /* __SPARC64_SWITCH_TO_64_H */
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