2012-09-21 08:07:50 +00:00
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/*
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* i.MX IPUv3 Graphics driver
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*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/export.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <drm/drmP.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <linux/fb.h>
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#include <linux/clk.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include "ipu-v3/imx-ipu-v3.h"
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#include "imx-drm.h"
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#define DRIVER_DESC "i.MX IPUv3 Graphics"
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struct ipu_framebuffer {
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struct drm_framebuffer base;
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void *virt;
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dma_addr_t phys;
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size_t len;
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};
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struct ipu_crtc {
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struct drm_fb_helper fb_helper;
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struct ipu_framebuffer ifb;
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int num_crtcs;
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struct device *dev;
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struct drm_crtc base;
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struct imx_drm_crtc *imx_crtc;
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struct ipuv3_channel *ipu_ch;
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struct ipu_dc *dc;
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struct ipu_dp *dp;
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struct dmfc_channel *dmfc;
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struct ipu_di *di;
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int enabled;
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struct ipu_priv *ipu_priv;
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struct drm_pending_vblank_event *page_flip_event;
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struct drm_framebuffer *newfb;
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int irq;
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u32 interface_pix_fmt;
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unsigned long di_clkflags;
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2013-04-08 16:04:35 +00:00
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int di_hsync_pin;
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int di_vsync_pin;
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2012-09-21 08:07:50 +00:00
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};
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#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
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static int calc_vref(struct drm_display_mode *mode)
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{
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unsigned long htotal, vtotal;
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htotal = mode->htotal;
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vtotal = mode->vtotal;
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if (!htotal || !vtotal)
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return 60;
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return mode->clock * 1000 / vtotal / htotal;
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}
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static int calc_bandwidth(struct drm_display_mode *mode, unsigned int vref)
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{
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return mode->hdisplay * mode->vdisplay * vref;
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}
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static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
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{
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if (ipu_crtc->enabled)
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return;
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ipu_di_enable(ipu_crtc->di);
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ipu_dmfc_enable_channel(ipu_crtc->dmfc);
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ipu_idmac_enable_channel(ipu_crtc->ipu_ch);
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ipu_dc_enable_channel(ipu_crtc->dc);
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if (ipu_crtc->dp)
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ipu_dp_enable_channel(ipu_crtc->dp);
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ipu_crtc->enabled = 1;
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}
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static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
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{
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if (!ipu_crtc->enabled)
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return;
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if (ipu_crtc->dp)
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ipu_dp_disable_channel(ipu_crtc->dp);
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ipu_dc_disable_channel(ipu_crtc->dc);
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ipu_idmac_disable_channel(ipu_crtc->ipu_ch);
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ipu_dmfc_disable_channel(ipu_crtc->dmfc);
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ipu_di_disable(ipu_crtc->di);
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ipu_crtc->enabled = 0;
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}
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static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
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2012-11-12 15:29:01 +00:00
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dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
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2012-09-21 08:07:50 +00:00
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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ipu_fb_enable(ipu_crtc);
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break;
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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case DRM_MODE_DPMS_OFF:
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ipu_fb_disable(ipu_crtc);
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break;
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}
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}
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static int ipu_page_flip(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event)
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{
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struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
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int ret;
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if (ipu_crtc->newfb)
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return -EBUSY;
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ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
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if (ret) {
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dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
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list_del(&event->base.link);
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return ret;
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}
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ipu_crtc->newfb = fb;
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ipu_crtc->page_flip_event = event;
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return 0;
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}
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static const struct drm_crtc_funcs ipu_crtc_funcs = {
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.set_config = drm_crtc_helper_set_config,
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.destroy = drm_crtc_cleanup,
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.page_flip = ipu_page_flip,
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};
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static int ipu_drm_set_base(struct drm_crtc *crtc, int x, int y)
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{
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struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
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struct drm_gem_cma_object *cma_obj;
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struct drm_framebuffer *fb = crtc->fb;
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unsigned long phys;
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cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
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if (!cma_obj) {
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DRM_LOG_KMS("entry is null.\n");
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return -EFAULT;
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}
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phys = cma_obj->paddr;
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phys += x * (fb->bits_per_pixel >> 3);
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phys += y * fb->pitches[0];
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dev_dbg(ipu_crtc->dev, "%s: phys: 0x%lx\n", __func__, phys);
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dev_dbg(ipu_crtc->dev, "%s: xy: %dx%d\n", __func__, x, y);
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ipu_cpmem_set_stride(ipu_get_cpmem(ipu_crtc->ipu_ch), fb->pitches[0]);
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ipu_cpmem_set_buffer(ipu_get_cpmem(ipu_crtc->ipu_ch),
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0, phys);
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return 0;
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}
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static int ipu_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *orig_mode,
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struct drm_display_mode *mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
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struct drm_framebuffer *fb = ipu_crtc->base.fb;
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int ret;
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struct ipu_di_signal_cfg sig_cfg = {};
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u32 out_pixel_fmt;
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struct ipu_ch_param __iomem *cpmem = ipu_get_cpmem(ipu_crtc->ipu_ch);
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int bpp;
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u32 v4l2_fmt;
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dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
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mode->hdisplay);
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dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
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mode->vdisplay);
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ipu_ch_param_zero(cpmem);
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switch (fb->pixel_format) {
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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v4l2_fmt = V4L2_PIX_FMT_RGB32;
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bpp = 32;
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break;
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case DRM_FORMAT_RGB565:
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v4l2_fmt = V4L2_PIX_FMT_RGB565;
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bpp = 16;
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break;
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case DRM_FORMAT_RGB888:
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v4l2_fmt = V4L2_PIX_FMT_RGB24;
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bpp = 24;
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break;
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default:
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dev_err(ipu_crtc->dev, "unsupported pixel format 0x%08x\n",
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fb->pixel_format);
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return -EINVAL;
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}
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out_pixel_fmt = ipu_crtc->interface_pix_fmt;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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sig_cfg.interlaced = 1;
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if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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sig_cfg.Hsync_pol = 1;
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if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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sig_cfg.Vsync_pol = 1;
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sig_cfg.enable_pol = 1;
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sig_cfg.clk_pol = 0;
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sig_cfg.width = mode->hdisplay;
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sig_cfg.height = mode->vdisplay;
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sig_cfg.pixel_fmt = out_pixel_fmt;
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sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
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sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
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sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;
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sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
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sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
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sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
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sig_cfg.pixelclock = mode->clock * 1000;
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sig_cfg.clkflags = ipu_crtc->di_clkflags;
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sig_cfg.v_to_h_sync = 0;
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2013-04-08 16:04:35 +00:00
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sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
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sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
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2012-09-21 08:07:50 +00:00
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if (ipu_crtc->dp) {
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ret = ipu_dp_setup_channel(ipu_crtc->dp, IPUV3_COLORSPACE_RGB,
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IPUV3_COLORSPACE_RGB);
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if (ret) {
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dev_err(ipu_crtc->dev,
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"initializing display processor failed with %d\n",
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ret);
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return ret;
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}
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ipu_dp_set_global_alpha(ipu_crtc->dp, 1, 0, 1);
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}
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ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
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out_pixel_fmt, mode->hdisplay);
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if (ret) {
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dev_err(ipu_crtc->dev,
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"initializing display controller failed with %d\n",
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ret);
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return ret;
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}
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ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
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if (ret) {
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dev_err(ipu_crtc->dev,
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"initializing panel failed with %d\n", ret);
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return ret;
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}
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ipu_cpmem_set_resolution(cpmem, mode->hdisplay, mode->vdisplay);
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ipu_cpmem_set_fmt(cpmem, v4l2_fmt);
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ipu_cpmem_set_high_priority(ipu_crtc->ipu_ch);
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ret = ipu_dmfc_init_channel(ipu_crtc->dmfc, mode->hdisplay);
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if (ret) {
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dev_err(ipu_crtc->dev,
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"initializing dmfc channel failed with %d\n",
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ret);
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return ret;
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}
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ret = ipu_dmfc_alloc_bandwidth(ipu_crtc->dmfc,
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calc_bandwidth(mode, calc_vref(mode)), 64);
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if (ret) {
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dev_err(ipu_crtc->dev,
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"allocating dmfc bandwidth failed with %d\n",
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ret);
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return ret;
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}
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ipu_drm_set_base(crtc, x, y);
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return 0;
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}
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static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
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{
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struct drm_pending_vblank_event *e;
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struct timeval now;
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unsigned long flags;
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struct drm_device *drm = ipu_crtc->base.dev;
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spin_lock_irqsave(&drm->event_lock, flags);
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e = ipu_crtc->page_flip_event;
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if (!e) {
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spin_unlock_irqrestore(&drm->event_lock, flags);
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return;
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}
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do_gettimeofday(&now);
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e->event.sequence = 0;
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e->event.tv_sec = now.tv_sec;
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e->event.tv_usec = now.tv_usec;
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ipu_crtc->page_flip_event = NULL;
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imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
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list_add_tail(&e->base.link, &e->base.file_priv->event_list);
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wake_up_interruptible(&e->base.file_priv->event_wait);
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spin_unlock_irqrestore(&drm->event_lock, flags);
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}
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static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
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{
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struct ipu_crtc *ipu_crtc = dev_id;
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|
imx_drm_handle_vblank(ipu_crtc->imx_crtc);
|
|
|
|
|
|
|
|
if (ipu_crtc->newfb) {
|
|
|
|
ipu_crtc->base.fb = ipu_crtc->newfb;
|
|
|
|
ipu_crtc->newfb = NULL;
|
|
|
|
ipu_drm_set_base(&ipu_crtc->base, 0, 0);
|
|
|
|
ipu_crtc_handle_pageflip(ipu_crtc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
|
|
const struct drm_display_mode *mode,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipu_crtc_prepare(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
|
|
|
|
|
|
|
|
ipu_fb_disable(ipu_crtc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipu_crtc_commit(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
|
|
|
|
|
|
|
|
ipu_fb_enable(ipu_crtc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipu_crtc_load_lut(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct drm_crtc_helper_funcs ipu_helper_funcs = {
|
|
|
|
.dpms = ipu_crtc_dpms,
|
|
|
|
.mode_fixup = ipu_crtc_mode_fixup,
|
|
|
|
.mode_set = ipu_crtc_mode_set,
|
|
|
|
.prepare = ipu_crtc_prepare,
|
|
|
|
.commit = ipu_crtc_commit,
|
|
|
|
.load_lut = ipu_crtc_load_lut,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int ipu_enable_vblank(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
|
|
|
|
|
|
|
|
enable_irq(ipu_crtc->irq);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipu_disable_vblank(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
|
|
|
|
|
|
|
|
disable_irq(ipu_crtc->irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
|
2013-04-08 16:04:35 +00:00
|
|
|
u32 pixfmt, int hsync_pin, int vsync_pin)
|
2012-09-21 08:07:50 +00:00
|
|
|
{
|
|
|
|
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
|
|
|
|
|
|
|
|
ipu_crtc->interface_pix_fmt = pixfmt;
|
2013-04-08 16:04:35 +00:00
|
|
|
ipu_crtc->di_hsync_pin = hsync_pin;
|
|
|
|
ipu_crtc->di_vsync_pin = vsync_pin;
|
2012-09-21 08:07:50 +00:00
|
|
|
|
|
|
|
switch (encoder_type) {
|
2013-04-08 16:04:33 +00:00
|
|
|
case DRM_MODE_ENCODER_DAC:
|
|
|
|
case DRM_MODE_ENCODER_TVDAC:
|
2012-09-21 08:07:50 +00:00
|
|
|
case DRM_MODE_ENCODER_LVDS:
|
|
|
|
ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC |
|
|
|
|
IPU_DI_CLKMODE_EXT;
|
|
|
|
break;
|
|
|
|
case DRM_MODE_ENCODER_NONE:
|
|
|
|
ipu_crtc->di_clkflags = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
|
|
|
|
.enable_vblank = ipu_enable_vblank,
|
|
|
|
.disable_vblank = ipu_disable_vblank,
|
|
|
|
.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
|
|
|
|
.crtc_funcs = &ipu_crtc_funcs,
|
|
|
|
.crtc_helper_funcs = &ipu_helper_funcs,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
|
|
|
|
{
|
|
|
|
if (!IS_ERR_OR_NULL(ipu_crtc->ipu_ch))
|
|
|
|
ipu_idmac_put(ipu_crtc->ipu_ch);
|
|
|
|
if (!IS_ERR_OR_NULL(ipu_crtc->dmfc))
|
|
|
|
ipu_dmfc_put(ipu_crtc->dmfc);
|
|
|
|
if (!IS_ERR_OR_NULL(ipu_crtc->dp))
|
|
|
|
ipu_dp_put(ipu_crtc->dp);
|
|
|
|
if (!IS_ERR_OR_NULL(ipu_crtc->di))
|
|
|
|
ipu_di_put(ipu_crtc->di);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
|
|
|
|
struct ipu_client_platformdata *pdata)
|
|
|
|
{
|
|
|
|
struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ipu_crtc->ipu_ch = ipu_idmac_get(ipu, pdata->dma[0]);
|
2012-12-25 14:58:38 +00:00
|
|
|
if (IS_ERR(ipu_crtc->ipu_ch)) {
|
2012-09-21 08:07:50 +00:00
|
|
|
ret = PTR_ERR(ipu_crtc->ipu_ch);
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
|
|
|
|
if (IS_ERR(ipu_crtc->dc)) {
|
|
|
|
ret = PTR_ERR(ipu_crtc->dc);
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ipu_crtc->dmfc = ipu_dmfc_get(ipu, pdata->dma[0]);
|
|
|
|
if (IS_ERR(ipu_crtc->dmfc)) {
|
|
|
|
ret = PTR_ERR(ipu_crtc->dmfc);
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pdata->dp >= 0) {
|
|
|
|
ipu_crtc->dp = ipu_dp_get(ipu, pdata->dp);
|
|
|
|
if (IS_ERR(ipu_crtc->dp)) {
|
2012-12-25 14:58:38 +00:00
|
|
|
ret = PTR_ERR(ipu_crtc->dp);
|
2012-09-21 08:07:50 +00:00
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ipu_crtc->di = ipu_di_get(ipu, pdata->di);
|
|
|
|
if (IS_ERR(ipu_crtc->di)) {
|
|
|
|
ret = PTR_ERR(ipu_crtc->di);
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
|
|
ipu_put_resources(ipu_crtc);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
|
|
|
|
struct ipu_client_platformdata *pdata)
|
|
|
|
{
|
2013-02-20 02:57:01 +00:00
|
|
|
struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
|
2012-09-21 08:07:50 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = ipu_get_resources(ipu_crtc, pdata);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = imx_drm_add_crtc(&ipu_crtc->base,
|
|
|
|
&ipu_crtc->imx_crtc,
|
|
|
|
&ipu_crtc_helper_funcs, THIS_MODULE,
|
|
|
|
ipu_crtc->dev->parent->of_node, pdata->di);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
|
|
|
|
goto err_put_resources;
|
|
|
|
}
|
|
|
|
|
2013-02-20 02:57:01 +00:00
|
|
|
ipu_crtc->irq = ipu_idmac_channel_irq(ipu, ipu_crtc->ipu_ch,
|
|
|
|
IPU_IRQ_EOF);
|
|
|
|
ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
|
|
|
|
"imx_drm", ipu_crtc);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
|
|
|
|
goto err_put_resources;
|
|
|
|
}
|
|
|
|
|
|
|
|
disable_irq(ipu_crtc->irq);
|
|
|
|
|
2012-09-21 08:07:50 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_put_resources:
|
|
|
|
ipu_put_resources(ipu_crtc);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-19 18:22:11 +00:00
|
|
|
static int ipu_drm_probe(struct platform_device *pdev)
|
2012-09-21 08:07:50 +00:00
|
|
|
{
|
|
|
|
struct ipu_client_platformdata *pdata = pdev->dev.platform_data;
|
|
|
|
struct ipu_crtc *ipu_crtc;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!pdata)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
|
|
|
|
|
|
|
ipu_crtc = devm_kzalloc(&pdev->dev, sizeof(*ipu_crtc), GFP_KERNEL);
|
|
|
|
if (!ipu_crtc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ipu_crtc->dev = &pdev->dev;
|
|
|
|
|
|
|
|
ret = ipu_crtc_init(ipu_crtc, pdata);
|
2012-12-25 14:58:38 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2012-09-21 08:07:50 +00:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, ipu_crtc);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-19 18:26:38 +00:00
|
|
|
static int ipu_drm_remove(struct platform_device *pdev)
|
2012-09-21 08:07:50 +00:00
|
|
|
{
|
|
|
|
struct ipu_crtc *ipu_crtc = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
imx_drm_remove_crtc(ipu_crtc->imx_crtc);
|
|
|
|
|
|
|
|
ipu_put_resources(ipu_crtc);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver ipu_drm_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "imx-ipuv3-crtc",
|
|
|
|
},
|
|
|
|
.probe = ipu_drm_probe,
|
2012-11-19 18:20:51 +00:00
|
|
|
.remove = ipu_drm_remove,
|
2012-09-21 08:07:50 +00:00
|
|
|
};
|
|
|
|
module_platform_driver(ipu_drm_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
|
|
MODULE_LICENSE("GPL");
|