142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
![]() |
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2018 Intel Corporation
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*/
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#include "intel_drv.h"
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enum {
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PROCMON_0_85V_DOT_0,
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PROCMON_0_95V_DOT_0,
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PROCMON_0_95V_DOT_1,
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PROCMON_1_05V_DOT_0,
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PROCMON_1_05V_DOT_1,
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};
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static const struct cnl_procmon {
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u32 dw1, dw9, dw10;
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} cnl_procmon_values[] = {
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[PROCMON_0_85V_DOT_0] =
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{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
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[PROCMON_0_95V_DOT_0] =
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{ .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
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[PROCMON_0_95V_DOT_1] =
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{ .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
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[PROCMON_1_05V_DOT_0] =
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{ .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
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[PROCMON_1_05V_DOT_1] =
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{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
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};
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/*
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* CNL has just one set of registers, while ICL has two sets: one for port A and
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* the other for port B. The CNL registers are equivalent to the ICL port A
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* registers, that's why we call the ICL macros even though the function has CNL
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* on its name.
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*/
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static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
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enum port port)
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{
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const struct cnl_procmon *procmon;
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u32 val;
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val = I915_READ(ICL_PORT_COMP_DW3(port));
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switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
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default:
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MISSING_CASE(val);
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/* fall through */
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case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
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procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
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break;
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case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
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procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
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break;
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case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
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procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
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break;
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case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
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procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
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break;
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case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
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procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
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break;
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}
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val = I915_READ(ICL_PORT_COMP_DW1(port));
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val &= ~((0xff << 16) | 0xff);
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val |= procmon->dw1;
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I915_WRITE(ICL_PORT_COMP_DW1(port), val);
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I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
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I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
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}
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void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
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{
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u32 val;
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val = I915_READ(CHICKEN_MISC_2);
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val &= ~CNL_COMP_PWR_DOWN;
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I915_WRITE(CHICKEN_MISC_2, val);
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/* Dummy PORT_A to get the correct CNL register from the ICL macro */
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cnl_set_procmon_ref_values(dev_priv, PORT_A);
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val = I915_READ(CNL_PORT_COMP_DW0);
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val |= COMP_INIT;
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I915_WRITE(CNL_PORT_COMP_DW0, val);
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val = I915_READ(CNL_PORT_CL1CM_DW5);
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val |= CL_POWER_DOWN_ENABLE;
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I915_WRITE(CNL_PORT_CL1CM_DW5, val);
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}
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void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
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{
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u32 val;
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val = I915_READ(CHICKEN_MISC_2);
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val |= CNL_COMP_PWR_DOWN;
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I915_WRITE(CHICKEN_MISC_2, val);
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}
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void icl_combo_phys_init(struct drm_i915_private *dev_priv)
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{
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enum port port;
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for (port = PORT_A; port <= PORT_B; port++) {
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u32 val;
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val = I915_READ(ICL_PHY_MISC(port));
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val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
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I915_WRITE(ICL_PHY_MISC(port), val);
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cnl_set_procmon_ref_values(dev_priv, port);
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val = I915_READ(ICL_PORT_COMP_DW0(port));
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val |= COMP_INIT;
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I915_WRITE(ICL_PORT_COMP_DW0(port), val);
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val = I915_READ(ICL_PORT_CL_DW5(port));
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val |= CL_POWER_DOWN_ENABLE;
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I915_WRITE(ICL_PORT_CL_DW5(port), val);
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}
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}
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void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
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{
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enum port port;
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for (port = PORT_A; port <= PORT_B; port++) {
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u32 val;
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val = I915_READ(ICL_PHY_MISC(port));
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val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
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I915_WRITE(ICL_PHY_MISC(port), val);
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val = I915_READ(ICL_PORT_COMP_DW0(port));
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val &= ~COMP_INIT;
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I915_WRITE(ICL_PORT_COMP_DW0(port), val);
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}
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}
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