License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2015-11-12 20:59:04 +00:00
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#include <linux/jump_label.h>
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2017-07-11 15:33:44 +00:00
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#include <asm/unwind_hints.h>
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2017-12-04 14:07:35 +00:00
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#include <asm/cpufeatures.h>
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#include <asm/page_types.h>
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2017-12-04 14:07:59 +00:00
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#include <asm/percpu.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor-flags.h>
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2021-05-10 18:53:10 +00:00
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#include <asm/ptrace-abi.h>
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2022-07-10 02:42:53 +00:00
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#include <asm/msr.h>
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#include <asm/nospec-branch.h>
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2015-11-12 20:59:04 +00:00
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2008-01-30 12:32:49 +00:00
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/*
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2009-02-03 17:02:36 +00:00
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x86 function call convention, 64-bit:
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-------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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---------------------------------------------------------------------------
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rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
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( rsp is obviously invariant across normal function calls. (gcc can 'merge'
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functions when it sees tail-call optimization possibilities) rflags is
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clobbered. Leftover arguments are passed over the stack frame.)
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[*] In the frame-pointers case rbp is fixed to the stack frame.
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[**] for struct return values wider than 64 bits the return convention is a
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bit more complex: up to 128 bits width we return small structures
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straight in rax, rdx. For structures larger than that (3 words or
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larger) the caller puts a pointer to an on-stack return struct
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[allocated in the caller's stack frame] into the first argument - i.e.
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into rdi. All other arguments shift up by one in this case.
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Fortunately this case is rare in the kernel.
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For 32-bit we have the following conventions - kernel is built with
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-mregparm=3 and -freg-struct-return:
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x86 function calling convention, 32-bit:
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----------------------------------------
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arguments | callee-saved | extra caller-saved | return
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[callee-clobbered] | | [callee-clobbered] |
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-------------------------------------------------------------------------
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eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
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( here too esp is obviously invariant across normal function calls. eflags
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is clobbered. Leftover arguments are passed over the stack frame. )
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[*] In the frame-pointers case ebp is fixed to the stack frame.
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[**] We build with -freg-struct-return, which on 32-bit means similar
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semantics as on 64-bit: edx can be used for a second return value
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(i.e. covering integer and structure sizes up to 64 bits) - after that
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it gets more complex and more expensive: 3-word or larger struct returns
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get done in the caller's frame and the pointer to the return struct goes
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into regparm0, i.e. eax - the other arguments shift up and the
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function's register parameters degenerate to regparm=2 in essence.
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*/
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2013-08-14 12:51:00 +00:00
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#ifdef CONFIG_X86_64
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2009-02-03 17:02:36 +00:00
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/*
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2012-09-26 08:28:22 +00:00
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* 64-bit system call stack frame layout defines and helpers,
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* for assembly code:
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2008-01-30 12:32:49 +00:00
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*/
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2005-04-16 22:20:36 +00:00
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2021-05-10 18:53:14 +00:00
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.macro PUSH_REGS rdx=%rdx rax=%rax save_ret=0
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2018-02-14 17:59:23 +00:00
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.if \save_ret
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pushq %rsi /* pt_regs->si */
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movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
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movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
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.else
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2018-02-11 10:49:45 +00:00
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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2018-02-14 17:59:23 +00:00
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.endif
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2018-02-11 10:49:46 +00:00
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pushq \rdx /* pt_regs->dx */
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2018-02-11 10:49:45 +00:00
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pushq %rcx /* pt_regs->cx */
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2018-02-11 10:49:46 +00:00
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pushq \rax /* pt_regs->ax */
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2018-02-11 10:49:45 +00:00
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pushq %r8 /* pt_regs->r8 */
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pushq %r9 /* pt_regs->r9 */
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pushq %r10 /* pt_regs->r10 */
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pushq %r11 /* pt_regs->r11 */
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pushq %rbx /* pt_regs->rbx */
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pushq %rbp /* pt_regs->rbp */
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pushq %r12 /* pt_regs->r12 */
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pushq %r13 /* pt_regs->r13 */
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pushq %r14 /* pt_regs->r14 */
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pushq %r15 /* pt_regs->r15 */
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UNWIND_HINT_REGS
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2020-04-25 10:03:01 +00:00
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2018-02-14 17:59:23 +00:00
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.if \save_ret
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pushq %rsi /* return address on top of stack */
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.endif
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2021-05-10 18:53:14 +00:00
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.endm
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2020-04-25 10:03:01 +00:00
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2021-05-10 18:53:14 +00:00
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.macro CLEAR_REGS
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2020-04-25 10:03:01 +00:00
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/*
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* Sanitize registers of values that a speculation attack might
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* otherwise want to exploit. The lower registers are likely clobbered
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* well before they could be put to use in a speculative execution
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* gadget.
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*/
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xorl %edx, %edx /* nospec dx */
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xorl %ecx, %ecx /* nospec cx */
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xorl %r8d, %r8d /* nospec r8 */
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xorl %r9d, %r9d /* nospec r9 */
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xorl %r10d, %r10d /* nospec r10 */
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xorl %r11d, %r11d /* nospec r11 */
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xorl %ebx, %ebx /* nospec rbx */
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xorl %ebp, %ebp /* nospec rbp */
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xorl %r12d, %r12d /* nospec r12 */
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xorl %r13d, %r13d /* nospec r13 */
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xorl %r14d, %r14d /* nospec r14 */
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xorl %r15d, %r15d /* nospec r15 */
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2018-02-11 10:49:48 +00:00
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.endm
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2018-02-11 10:49:45 +00:00
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2021-05-10 18:53:14 +00:00
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.macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
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PUSH_REGS rdx=\rdx, rax=\rax, save_ret=\save_ret
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CLEAR_REGS
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.endm
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2022-05-06 12:14:35 +00:00
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.macro POP_REGS pop_rdi=1
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2017-11-02 07:59:01 +00:00
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popq %r15
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popq %r14
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popq %r13
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popq %r12
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popq %rbp
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popq %rbx
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popq %r11
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popq %r10
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popq %r9
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popq %r8
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popq %rax
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popq %rcx
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popq %rdx
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popq %rsi
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2018-02-11 10:49:43 +00:00
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.if \pop_rdi
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2017-11-02 07:59:01 +00:00
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popq %rdi
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2018-02-11 10:49:43 +00:00
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.endif
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2018-02-11 10:49:48 +00:00
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.endm
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2013-08-14 12:51:00 +00:00
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2017-12-04 14:07:35 +00:00
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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2017-12-04 14:07:59 +00:00
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/*
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* PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
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* halves:
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*/
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2018-01-13 23:23:57 +00:00
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#define PTI_USER_PGTABLE_BIT PAGE_SHIFT
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#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
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#define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
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#define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
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#define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
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2017-12-04 14:07:35 +00:00
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2017-12-04 14:07:59 +00:00
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.macro SET_NOFLUSH_BIT reg:req
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bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
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2017-12-04 14:07:35 +00:00
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.endm
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2017-12-04 14:07:59 +00:00
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.macro ADJUST_KERNEL_CR3 reg:req
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ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
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/* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
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2018-01-13 23:23:57 +00:00
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andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
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2017-12-04 14:07:35 +00:00
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.endm
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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2017-12-04 14:07:36 +00:00
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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2017-12-04 14:07:35 +00:00
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mov %cr3, \scratch_reg
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ADJUST_KERNEL_CR3 \scratch_reg
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mov \scratch_reg, %cr3
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2017-12-04 14:07:36 +00:00
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.Lend_\@:
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2017-12-04 14:07:35 +00:00
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.endm
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2017-12-04 14:07:59 +00:00
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#define THIS_CPU_user_pcid_flush_mask \
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PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
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.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
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2017-12-04 14:07:36 +00:00
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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2017-12-04 14:07:35 +00:00
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mov %cr3, \scratch_reg
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2017-12-04 14:07:59 +00:00
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ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
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/*
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* Test if the ASID needs a flush.
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*/
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movq \scratch_reg, \scratch_reg2
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andq $(0x7FF), \scratch_reg /* mask ASID */
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bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
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jnc .Lnoflush_\@
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/* Flush needed, clear the bit */
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btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
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movq \scratch_reg2, \scratch_reg
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2018-01-13 23:23:57 +00:00
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jmp .Lwrcr3_pcid_\@
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2017-12-04 14:07:59 +00:00
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.Lnoflush_\@:
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movq \scratch_reg2, \scratch_reg
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SET_NOFLUSH_BIT \scratch_reg
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2018-01-13 23:23:57 +00:00
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.Lwrcr3_pcid_\@:
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/* Flip the ASID to the user version */
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orq $(PTI_USER_PCID_MASK), \scratch_reg
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2017-12-04 14:07:59 +00:00
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.Lwrcr3_\@:
|
2018-01-13 23:23:57 +00:00
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/* Flip the PGD to the user version */
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orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
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2017-12-04 14:07:35 +00:00
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mov \scratch_reg, %cr3
|
2017-12-04 14:07:36 +00:00
|
|
|
.Lend_\@:
|
2017-12-04 14:07:35 +00:00
|
|
|
.endm
|
|
|
|
|
|
2017-12-04 14:07:59 +00:00
|
|
|
.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
|
|
|
|
|
pushq %rax
|
|
|
|
|
SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
|
|
|
|
|
popq %rax
|
|
|
|
|
.endm
|
|
|
|
|
|
2017-12-04 14:07:35 +00:00
|
|
|
.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
|
2017-12-04 14:07:36 +00:00
|
|
|
ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
|
2017-12-04 14:07:35 +00:00
|
|
|
movq %cr3, \scratch_reg
|
|
|
|
|
movq \scratch_reg, \save_reg
|
|
|
|
|
/*
|
2018-01-13 23:23:57 +00:00
|
|
|
* Test the user pagetable bit. If set, then the user page tables
|
|
|
|
|
* are active. If clear CR3 already has the kernel page table
|
|
|
|
|
* active.
|
2017-12-04 14:07:35 +00:00
|
|
|
*/
|
2018-01-13 23:23:57 +00:00
|
|
|
bt $PTI_USER_PGTABLE_BIT, \scratch_reg
|
|
|
|
|
jnc .Ldone_\@
|
2017-12-04 14:07:35 +00:00
|
|
|
|
|
|
|
|
ADJUST_KERNEL_CR3 \scratch_reg
|
|
|
|
|
movq \scratch_reg, %cr3
|
|
|
|
|
|
|
|
|
|
.Ldone_\@:
|
|
|
|
|
.endm
|
|
|
|
|
|
2017-12-04 14:08:00 +00:00
|
|
|
.macro RESTORE_CR3 scratch_reg:req save_reg:req
|
2017-12-04 14:07:36 +00:00
|
|
|
ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
|
2017-12-04 14:08:00 +00:00
|
|
|
|
|
|
|
|
ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* KERNEL pages can always resume with NOFLUSH as we do
|
|
|
|
|
* explicit flushes.
|
|
|
|
|
*/
|
2018-01-13 23:23:57 +00:00
|
|
|
bt $PTI_USER_PGTABLE_BIT, \save_reg
|
2017-12-04 14:08:00 +00:00
|
|
|
jnc .Lnoflush_\@
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check if there's a pending flush for the user ASID we're
|
|
|
|
|
* about to set.
|
|
|
|
|
*/
|
|
|
|
|
movq \save_reg, \scratch_reg
|
|
|
|
|
andq $(0x7FF), \scratch_reg
|
|
|
|
|
bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
|
|
|
|
|
jnc .Lnoflush_\@
|
|
|
|
|
|
|
|
|
|
btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
|
|
|
|
|
jmp .Lwrcr3_\@
|
|
|
|
|
|
|
|
|
|
.Lnoflush_\@:
|
|
|
|
|
SET_NOFLUSH_BIT \save_reg
|
|
|
|
|
|
|
|
|
|
.Lwrcr3_\@:
|
2017-12-04 14:07:35 +00:00
|
|
|
/*
|
|
|
|
|
* The CR3 write could be avoided when not changing its value,
|
|
|
|
|
* but would require a CR3 read *and* a scratch register.
|
|
|
|
|
*/
|
|
|
|
|
movq \save_reg, %cr3
|
2017-12-04 14:07:36 +00:00
|
|
|
.Lend_\@:
|
2017-12-04 14:07:35 +00:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
#else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
|
|
|
|
|
|
|
|
|
|
.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
|
|
|
|
|
.endm
|
2017-12-04 14:07:59 +00:00
|
|
|
.macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
|
|
|
|
|
.endm
|
|
|
|
|
.macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
|
2017-12-04 14:07:35 +00:00
|
|
|
.endm
|
|
|
|
|
.macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
|
|
|
|
|
.endm
|
2017-12-04 14:08:00 +00:00
|
|
|
.macro RESTORE_CR3 scratch_reg:req save_reg:req
|
2017-12-04 14:07:35 +00:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
2022-07-10 02:42:53 +00:00
|
|
|
/*
|
|
|
|
|
* IBRS kernel mitigation for Spectre_v2.
|
|
|
|
|
*
|
|
|
|
|
* Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers
|
|
|
|
|
* the regs it uses (AX, CX, DX). Must be called before the first RET
|
|
|
|
|
* instruction (NOTE! UNTRAIN_RET includes a RET instruction)
|
|
|
|
|
*
|
|
|
|
|
* The optional argument is used to save/restore the current value,
|
|
|
|
|
* which is used on the paranoid paths.
|
|
|
|
|
*
|
|
|
|
|
* Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set.
|
|
|
|
|
*/
|
|
|
|
|
.macro IBRS_ENTER save_reg
|
2022-06-27 22:21:17 +00:00
|
|
|
#ifdef CONFIG_CPU_IBRS_ENTRY
|
2022-07-10 02:42:53 +00:00
|
|
|
ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
|
|
|
|
|
movl $MSR_IA32_SPEC_CTRL, %ecx
|
|
|
|
|
|
|
|
|
|
.ifnb \save_reg
|
|
|
|
|
rdmsr
|
|
|
|
|
shl $32, %rdx
|
|
|
|
|
or %rdx, %rax
|
|
|
|
|
mov %rax, \save_reg
|
|
|
|
|
test $SPEC_CTRL_IBRS, %eax
|
|
|
|
|
jz .Ldo_wrmsr_\@
|
|
|
|
|
lfence
|
|
|
|
|
jmp .Lend_\@
|
|
|
|
|
.Ldo_wrmsr_\@:
|
|
|
|
|
.endif
|
|
|
|
|
|
|
|
|
|
movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
|
|
|
|
|
movl %edx, %eax
|
|
|
|
|
shr $32, %rdx
|
|
|
|
|
wrmsr
|
|
|
|
|
.Lend_\@:
|
2022-06-27 22:21:17 +00:00
|
|
|
#endif
|
2022-07-10 02:42:53 +00:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX)
|
|
|
|
|
* regs. Must be called after the last RET.
|
|
|
|
|
*/
|
|
|
|
|
.macro IBRS_EXIT save_reg
|
2022-06-27 22:21:17 +00:00
|
|
|
#ifdef CONFIG_CPU_IBRS_ENTRY
|
2022-07-10 02:42:53 +00:00
|
|
|
ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
|
|
|
|
|
movl $MSR_IA32_SPEC_CTRL, %ecx
|
|
|
|
|
|
|
|
|
|
.ifnb \save_reg
|
|
|
|
|
mov \save_reg, %rdx
|
|
|
|
|
.else
|
|
|
|
|
movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
|
|
|
|
|
andl $(~SPEC_CTRL_IBRS), %edx
|
|
|
|
|
.endif
|
|
|
|
|
|
|
|
|
|
movl %edx, %eax
|
|
|
|
|
shr $32, %rdx
|
|
|
|
|
wrmsr
|
|
|
|
|
.Lend_\@:
|
2022-06-27 22:21:17 +00:00
|
|
|
#endif
|
2022-07-10 02:42:53 +00:00
|
|
|
.endm
|
|
|
|
|
|
x86/speculation: Prepare entry code for Spectre v1 swapgs mitigations
Spectre v1 isn't only about array bounds checks. It can affect any
conditional checks. The kernel entry code interrupt, exception, and NMI
handlers all have conditional swapgs checks. Those may be problematic in
the context of Spectre v1, as kernel code can speculatively run with a user
GS.
For example:
if (coming from user space)
swapgs
mov %gs:<percpu_offset>, %reg
mov (%reg), %reg1
When coming from user space, the CPU can speculatively skip the swapgs, and
then do a speculative percpu load using the user GS value. So the user can
speculatively force a read of any kernel value. If a gadget exists which
uses the percpu value as an address in another load/store, then the
contents of the kernel value may become visible via an L1 side channel
attack.
A similar attack exists when coming from kernel space. The CPU can
speculatively do the swapgs, causing the user GS to get used for the rest
of the speculative window.
The mitigation is similar to a traditional Spectre v1 mitigation, except:
a) index masking isn't possible; because the index (percpu offset)
isn't user-controlled; and
b) an lfence is needed in both the "from user" swapgs path and the
"from kernel" non-swapgs path (because of the two attacks described
above).
The user entry swapgs paths already have SWITCH_TO_KERNEL_CR3, which has a
CR3 write when PTI is enabled. Since CR3 writes are serializing, the
lfences can be skipped in those cases.
On the other hand, the kernel entry swapgs paths don't depend on PTI.
To avoid unnecessary lfences for the user entry case, create two separate
features for alternative patching:
X86_FEATURE_FENCE_SWAPGS_USER
X86_FEATURE_FENCE_SWAPGS_KERNEL
Use these features in entry code to patch in lfences where needed.
The features aren't enabled yet, so there's no functional change.
Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Dave Hansen <dave.hansen@intel.com>
2019-07-08 16:52:25 +00:00
|
|
|
/*
|
|
|
|
|
* Mitigate Spectre v1 for conditional swapgs code paths.
|
|
|
|
|
*
|
|
|
|
|
* FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
|
|
|
|
|
* prevent a speculative swapgs when coming from kernel space.
|
|
|
|
|
*
|
|
|
|
|
* FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
|
|
|
|
|
* to prevent the swapgs from getting speculatively skipped when coming from
|
|
|
|
|
* user space.
|
|
|
|
|
*/
|
|
|
|
|
.macro FENCE_SWAPGS_USER_ENTRY
|
|
|
|
|
ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
|
|
|
|
|
.endm
|
|
|
|
|
.macro FENCE_SWAPGS_KERNEL_ENTRY
|
|
|
|
|
ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
|
|
|
|
|
.endm
|
|
|
|
|
|
2018-08-16 22:16:58 +00:00
|
|
|
.macro STACKLEAK_ERASE_NOCLOBBER
|
|
|
|
|
#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
|
|
|
|
|
PUSH_AND_CLEAR_REGS
|
|
|
|
|
call stackleak_erase
|
|
|
|
|
POP_REGS
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2020-05-28 20:13:57 +00:00
|
|
|
.macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req
|
|
|
|
|
rdgsbase \save_reg
|
|
|
|
|
GET_PERCPU_BASE \scratch_reg
|
|
|
|
|
wrgsbase \scratch_reg
|
|
|
|
|
.endm
|
|
|
|
|
|
2020-05-21 20:05:34 +00:00
|
|
|
#else /* CONFIG_X86_64 */
|
|
|
|
|
# undef UNWIND_HINT_IRET_REGS
|
|
|
|
|
# define UNWIND_HINT_IRET_REGS
|
|
|
|
|
#endif /* !CONFIG_X86_64 */
|
2013-08-14 12:51:00 +00:00
|
|
|
|
2018-08-16 22:16:58 +00:00
|
|
|
.macro STACKLEAK_ERASE
|
|
|
|
|
#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
|
|
|
|
|
call stackleak_erase
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
2020-05-28 20:13:56 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CPU/node NR is loaded from the limit (size) field of a special segment
|
|
|
|
|
* descriptor entry in GDT.
|
|
|
|
|
*/
|
|
|
|
|
.macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req
|
|
|
|
|
movq $__CPUNODE_SEG, \reg
|
|
|
|
|
lsl \reg, \reg
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Fetch the per-CPU GSBASE value for this processor and put it in @reg.
|
|
|
|
|
* We normally use %gs for accessing per-CPU data, but we are setting up
|
|
|
|
|
* %gs here and obviously can not use %gs itself to access per-CPU data.
|
2020-08-21 10:52:29 +00:00
|
|
|
*
|
|
|
|
|
* Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and
|
|
|
|
|
* may not restore the host's value until the CPU returns to userspace.
|
|
|
|
|
* Thus the kernel would consume a guest's TSC_AUX if an NMI arrives
|
|
|
|
|
* while running KVM's run loop.
|
2020-05-28 20:13:56 +00:00
|
|
|
*/
|
|
|
|
|
.macro GET_PERCPU_BASE reg:req
|
2020-08-21 10:52:29 +00:00
|
|
|
LOAD_CPU_AND_NODE_SEG_LIMIT \reg
|
2020-05-28 20:13:56 +00:00
|
|
|
andq $VDSO_CPUNODE_MASK, \reg
|
|
|
|
|
movq __per_cpu_offset(, \reg, 8), \reg
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
.macro GET_PERCPU_BASE reg:req
|
|
|
|
|
movq pcpu_unit_offsets(%rip), \reg
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_SMP */
|