2009-11-26 11:10:05 +00:00
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/*
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* SuperH MSIOF SPI Master Interface
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*
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* Copyright (c) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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2011-01-21 15:56:37 +00:00
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#include <linux/bitmap.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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2009-11-26 11:10:05 +00:00
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#include <linux/delay.h>
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2011-01-21 15:56:37 +00:00
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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2009-11-26 11:10:05 +00:00
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#include <linux/interrupt.h>
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2011-01-21 15:56:37 +00:00
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#include <linux/io.h>
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#include <linux/kernel.h>
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2011-07-03 19:44:29 +00:00
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#include <linux/module.h>
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2012-12-12 11:54:48 +00:00
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#include <linux/of.h>
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2014-02-25 10:21:09 +00:00
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#include <linux/of_device.h>
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2009-11-26 11:10:05 +00:00
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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2011-01-21 15:56:37 +00:00
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#include <linux/spi/sh_msiof.h>
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2009-11-26 11:10:05 +00:00
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <asm/unaligned.h>
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2014-02-25 10:21:09 +00:00
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struct sh_msiof_chipdata {
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u16 tx_fifo_size;
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u16 rx_fifo_size;
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spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
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u16 master_flags;
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2014-02-25 10:21:09 +00:00
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};
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2009-11-26 11:10:05 +00:00
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struct sh_msiof_spi_priv {
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struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
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void __iomem *mapbase;
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struct clk *clk;
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struct platform_device *pdev;
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2014-02-25 10:21:09 +00:00
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const struct sh_msiof_chipdata *chipdata;
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2009-11-26 11:10:05 +00:00
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struct sh_msiof_spi_info *info;
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struct completion done;
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int tx_fifo_size;
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int rx_fifo_size;
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};
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2014-02-20 14:43:03 +00:00
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#define TMDR1 0x00 /* Transmit Mode Register 1 */
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#define TMDR2 0x04 /* Transmit Mode Register 2 */
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#define TMDR3 0x08 /* Transmit Mode Register 3 */
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#define RMDR1 0x10 /* Receive Mode Register 1 */
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#define RMDR2 0x14 /* Receive Mode Register 2 */
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#define RMDR3 0x18 /* Receive Mode Register 3 */
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#define TSCR 0x20 /* Transmit Clock Select Register */
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#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
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#define CTR 0x28 /* Control Register */
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#define FCTR 0x30 /* FIFO Control Register */
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#define STR 0x40 /* Status Register */
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#define IER 0x44 /* Interrupt Enable Register */
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#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
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#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
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#define TFDR 0x50 /* Transmit FIFO Data Register */
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#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
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#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
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#define RFDR 0x60 /* Receive FIFO Data Register */
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/* TMDR1 and RMDR1 */
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#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
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#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
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#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
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#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
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#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
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#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */
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#define MDR1_FLD_SHIFT 2
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#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
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/* TMDR1 */
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#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
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/* TMDR2 and RMDR2 */
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#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
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#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
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#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
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/* TSCR and RSCR */
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#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
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#define SCR_BRPS(i) (((i) - 1) << 8)
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#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
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#define SCR_BRDV_DIV_2 0x0000
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#define SCR_BRDV_DIV_4 0x0001
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#define SCR_BRDV_DIV_8 0x0002
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#define SCR_BRDV_DIV_16 0x0003
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#define SCR_BRDV_DIV_32 0x0004
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#define SCR_BRDV_DIV_1 0x0007
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/* CTR */
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#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
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#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
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#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
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#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
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#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
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#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
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#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
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#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
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#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
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#define CTR_TXDIZ_LOW 0x00000000 /* 0 */
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#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
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#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
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#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
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#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
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#define CTR_TXE 0x00000200 /* Transmit Enable */
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#define CTR_RXE 0x00000100 /* Receive Enable */
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/* STR and IER */
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#define STR_TEOF 0x00800000 /* Frame Transmission End */
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#define STR_REOF 0x00000080 /* Frame Reception End */
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2011-01-21 15:56:37 +00:00
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static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
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2009-11-26 11:10:05 +00:00
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{
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switch (reg_offs) {
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case TSCR:
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case RSCR:
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return ioread16(p->mapbase + reg_offs);
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default:
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return ioread32(p->mapbase + reg_offs);
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}
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}
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static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
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2011-01-21 15:56:37 +00:00
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u32 value)
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2009-11-26 11:10:05 +00:00
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{
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switch (reg_offs) {
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case TSCR:
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case RSCR:
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iowrite16(value, p->mapbase + reg_offs);
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break;
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default:
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iowrite32(value, p->mapbase + reg_offs);
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break;
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}
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}
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static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
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2011-01-21 15:56:37 +00:00
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u32 clr, u32 set)
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2009-11-26 11:10:05 +00:00
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{
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2011-01-21 15:56:37 +00:00
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u32 mask = clr | set;
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u32 data;
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2009-11-26 11:10:05 +00:00
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int k;
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data = sh_msiof_read(p, CTR);
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data &= ~clr;
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data |= set;
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sh_msiof_write(p, CTR, data);
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for (k = 100; k > 0; k--) {
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if ((sh_msiof_read(p, CTR) & mask) == set)
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break;
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udelay(10);
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}
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return k > 0 ? 0 : -ETIMEDOUT;
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}
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static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
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{
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struct sh_msiof_spi_priv *p = data;
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/* just disable the interrupt and wake up */
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sh_msiof_write(p, IER, 0);
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complete(&p->done);
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return IRQ_HANDLED;
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}
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static struct {
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unsigned short div;
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unsigned short scr;
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} const sh_msiof_spi_clk_table[] = {
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2014-02-20 14:43:03 +00:00
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{ 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
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{ 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
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{ 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
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{ 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
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{ 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
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{ 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
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{ 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
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{ 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
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{ 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
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{ 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
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{ 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
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2009-11-26 11:10:05 +00:00
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};
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static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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2014-02-20 14:43:02 +00:00
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unsigned long parent_rate, u32 spi_hz)
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2009-11-26 11:10:05 +00:00
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{
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unsigned long div = 1024;
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size_t k;
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if (!WARN_ON(!spi_hz || !parent_rate))
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2013-12-01 18:19:13 +00:00
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div = DIV_ROUND_UP(parent_rate, spi_hz);
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2009-11-26 11:10:05 +00:00
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/* TODO: make more fine grained */
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for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
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if (sh_msiof_spi_clk_table[k].div >= div)
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break;
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}
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k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
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sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
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spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
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if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
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sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
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2009-11-26 11:10:05 +00:00
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}
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static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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2011-01-21 15:56:37 +00:00
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u32 cpol, u32 cpha,
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2013-12-01 18:19:15 +00:00
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u32 tx_hi_z, u32 lsb_first, u32 cs_high)
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2009-11-26 11:10:05 +00:00
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{
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2011-01-21 15:56:37 +00:00
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u32 tmp;
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2009-11-26 11:10:05 +00:00
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int edge;
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/*
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2010-02-02 02:29:15 +00:00
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* CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
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* 0 0 10 10 1 1
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* 0 1 10 10 0 0
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* 1 0 11 11 0 0
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* 1 1 11 11 1 1
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2009-11-26 11:10:05 +00:00
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*/
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sh_msiof_write(p, FCTR, 0);
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2013-12-01 18:19:15 +00:00
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2014-02-20 14:43:03 +00:00
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tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
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tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
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tmp |= lsb_first << MDR1_BITLSB_SHIFT;
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sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
|
spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
|
|
|
if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
|
|
|
|
/* These bits are reserved if RX needs TX */
|
|
|
|
tmp &= ~0x0000ffff;
|
|
|
|
}
|
2014-02-20 14:43:03 +00:00
|
|
|
sh_msiof_write(p, RMDR1, tmp);
|
2009-11-26 11:10:05 +00:00
|
|
|
|
2014-02-20 14:43:03 +00:00
|
|
|
tmp = 0;
|
|
|
|
tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
|
|
|
|
tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
|
2009-11-26 11:10:05 +00:00
|
|
|
|
2011-01-21 15:56:37 +00:00
|
|
|
edge = cpol ^ !cpha;
|
2009-11-26 11:10:05 +00:00
|
|
|
|
2014-02-20 14:43:03 +00:00
|
|
|
tmp |= edge << CTR_TEDG_SHIFT;
|
|
|
|
tmp |= edge << CTR_REDG_SHIFT;
|
|
|
|
tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
|
2009-11-26 11:10:05 +00:00
|
|
|
sh_msiof_write(p, CTR, tmp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, void *rx_buf,
|
2011-01-21 15:56:37 +00:00
|
|
|
u32 bits, u32 words)
|
2009-11-26 11:10:05 +00:00
|
|
|
{
|
2014-02-20 14:43:03 +00:00
|
|
|
u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
|
2009-11-26 11:10:05 +00:00
|
|
|
|
spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
|
|
|
if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
|
2009-11-26 11:10:05 +00:00
|
|
|
sh_msiof_write(p, TMDR2, dr2);
|
|
|
|
else
|
2014-02-20 14:43:03 +00:00
|
|
|
sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
|
2009-11-26 11:10:05 +00:00
|
|
|
|
|
|
|
if (rx_buf)
|
|
|
|
sh_msiof_write(p, RMDR2, dr2);
|
|
|
|
|
|
|
|
sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
|
|
|
|
{
|
|
|
|
sh_msiof_write(p, STR, sh_msiof_read(p, STR));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
const u8 *buf_8 = tx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
sh_msiof_write(p, TFDR, buf_8[k] << fs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
const u16 *buf_16 = tx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
sh_msiof_write(p, TFDR, buf_16[k] << fs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
const u16 *buf_16 = tx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
const u32 *buf_32 = tx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
sh_msiof_write(p, TFDR, buf_32[k] << fs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
const u32 *buf_32 = tx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
|
|
|
|
}
|
|
|
|
|
2011-01-21 15:56:42 +00:00
|
|
|
static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, int words, int fs)
|
|
|
|
{
|
|
|
|
const u32 *buf_32 = tx_buf;
|
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
|
|
|
|
const void *tx_buf, int words, int fs)
|
|
|
|
{
|
|
|
|
const u32 *buf_32 = tx_buf;
|
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
|
|
|
|
}
|
|
|
|
|
2009-11-26 11:10:05 +00:00
|
|
|
static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
|
|
|
|
void *rx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
u8 *buf_8 = rx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
|
|
|
|
void *rx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
u16 *buf_16 = rx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
|
|
|
|
void *rx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
u16 *buf_16 = rx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
|
|
|
|
void *rx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
u32 *buf_32 = rx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
|
|
|
|
void *rx_buf, int words, int fs)
|
|
|
|
{
|
2011-01-21 15:56:37 +00:00
|
|
|
u32 *buf_32 = rx_buf;
|
2009-11-26 11:10:05 +00:00
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
|
|
|
|
}
|
|
|
|
|
2011-01-21 15:56:42 +00:00
|
|
|
static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
|
|
|
|
void *rx_buf, int words, int fs)
|
|
|
|
{
|
|
|
|
u32 *buf_32 = rx_buf;
|
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
|
|
|
|
void *rx_buf, int words, int fs)
|
|
|
|
{
|
|
|
|
u32 *buf_32 = rx_buf;
|
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < words; k++)
|
|
|
|
put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
|
|
|
|
}
|
|
|
|
|
2009-11-26 11:10:05 +00:00
|
|
|
static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
|
|
|
|
{
|
|
|
|
int bits;
|
|
|
|
|
|
|
|
bits = t ? t->bits_per_word : 0;
|
2011-01-21 15:56:37 +00:00
|
|
|
if (!bits)
|
|
|
|
bits = spi->bits_per_word;
|
2009-11-26 11:10:05 +00:00
|
|
|
return bits;
|
|
|
|
}
|
|
|
|
|
2014-02-20 14:43:02 +00:00
|
|
|
static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t)
|
2009-11-26 11:10:05 +00:00
|
|
|
{
|
2014-02-20 14:43:02 +00:00
|
|
|
u32 hz;
|
2009-11-26 11:10:05 +00:00
|
|
|
|
|
|
|
hz = t ? t->speed_hz : 0;
|
2011-01-21 15:56:37 +00:00
|
|
|
if (!hz)
|
|
|
|
hz = spi->max_speed_hz;
|
2009-11-26 11:10:05 +00:00
|
|
|
return hz;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
|
|
|
|
struct spi_transfer *t)
|
|
|
|
{
|
|
|
|
int bits;
|
|
|
|
|
|
|
|
/* noting to check hz values against since parent clock is disabled */
|
|
|
|
|
|
|
|
bits = sh_msiof_spi_bits(spi, t);
|
|
|
|
if (bits < 8)
|
|
|
|
return -EINVAL;
|
|
|
|
if (bits > 32)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return spi_bitbang_setup_transfer(spi, t);
|
|
|
|
}
|
|
|
|
|
2014-02-20 14:43:04 +00:00
|
|
|
static int sh_msiof_spi_setup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct device_node *np = spi->master->dev.of_node;
|
2014-02-25 10:21:11 +00:00
|
|
|
struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
|
2014-02-20 14:43:04 +00:00
|
|
|
|
|
|
|
if (!np) {
|
|
|
|
/*
|
|
|
|
* Use spi->controller_data for CS (same strategy as spi_gpio),
|
|
|
|
* if any. otherwise let HW control CS
|
|
|
|
*/
|
|
|
|
spi->cs_gpio = (uintptr_t)spi->controller_data;
|
|
|
|
}
|
|
|
|
|
2014-02-25 10:21:11 +00:00
|
|
|
/* Configure pins before deasserting CS */
|
|
|
|
sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
|
|
|
|
!!(spi->mode & SPI_CPHA),
|
|
|
|
!!(spi->mode & SPI_3WIRE),
|
|
|
|
!!(spi->mode & SPI_LSB_FIRST),
|
|
|
|
!!(spi->mode & SPI_CS_HIGH));
|
|
|
|
|
2014-02-20 14:43:04 +00:00
|
|
|
return spi_bitbang_setup(spi);
|
|
|
|
}
|
|
|
|
|
2014-02-25 10:21:11 +00:00
|
|
|
static int sh_msiof_prepare_message(struct spi_master *master,
|
|
|
|
struct spi_message *msg)
|
|
|
|
{
|
|
|
|
struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
|
|
|
|
const struct spi_device *spi = msg->spi;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(&p->pdev->dev);
|
|
|
|
clk_enable(p->clk);
|
|
|
|
|
|
|
|
/* Configure pins before asserting CS */
|
|
|
|
sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
|
|
|
|
!!(spi->mode & SPI_CPHA),
|
|
|
|
!!(spi->mode & SPI_3WIRE),
|
|
|
|
!!(spi->mode & SPI_LSB_FIRST),
|
|
|
|
!!(spi->mode & SPI_CS_HIGH));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_msiof_unprepare_message(struct spi_master *master,
|
|
|
|
struct spi_message *msg)
|
|
|
|
{
|
|
|
|
struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
clk_disable(p->clk);
|
|
|
|
pm_runtime_put(&p->pdev->dev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-26 11:10:05 +00:00
|
|
|
static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
|
|
|
|
{
|
|
|
|
int value;
|
|
|
|
|
|
|
|
/* chip select is active low unless SPI_CS_HIGH is set */
|
|
|
|
if (spi->mode & SPI_CS_HIGH)
|
|
|
|
value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
|
|
|
|
else
|
|
|
|
value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
|
|
|
|
|
2014-02-20 14:43:04 +00:00
|
|
|
if (spi->cs_gpio >= 0)
|
|
|
|
gpio_set_value(spi->cs_gpio, value);
|
2009-11-26 11:10:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
|
|
|
|
void (*tx_fifo)(struct sh_msiof_spi_priv *,
|
|
|
|
const void *, int, int),
|
|
|
|
void (*rx_fifo)(struct sh_msiof_spi_priv *,
|
|
|
|
void *, int, int),
|
|
|
|
const void *tx_buf, void *rx_buf,
|
|
|
|
int words, int bits)
|
|
|
|
{
|
|
|
|
int fifo_shift;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* limit maximum word transfer to rx/tx fifo size */
|
|
|
|
if (tx_buf)
|
|
|
|
words = min_t(int, words, p->tx_fifo_size);
|
|
|
|
if (rx_buf)
|
|
|
|
words = min_t(int, words, p->rx_fifo_size);
|
|
|
|
|
|
|
|
/* the fifo contents need shifting */
|
|
|
|
fifo_shift = 32 - bits;
|
|
|
|
|
|
|
|
/* setup msiof transfer mode registers */
|
|
|
|
sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
|
|
|
|
|
|
|
|
/* write tx fifo */
|
|
|
|
if (tx_buf)
|
|
|
|
tx_fifo(p, tx_buf, words, fifo_shift);
|
|
|
|
|
|
|
|
/* setup clock and rx/tx signals */
|
|
|
|
ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
|
|
|
|
if (rx_buf)
|
|
|
|
ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
|
|
|
|
ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
|
|
|
|
|
|
|
|
/* start by setting frame bit */
|
2013-11-14 22:32:02 +00:00
|
|
|
reinit_completion(&p->done);
|
2009-11-26 11:10:05 +00:00
|
|
|
ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&p->pdev->dev, "failed to start hardware\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* wait for tx fifo to be emptied / rx fifo to be filled */
|
|
|
|
wait_for_completion(&p->done);
|
|
|
|
|
|
|
|
/* read rx fifo */
|
|
|
|
if (rx_buf)
|
|
|
|
rx_fifo(p, rx_buf, words, fifo_shift);
|
|
|
|
|
|
|
|
/* clear status bits */
|
|
|
|
sh_msiof_reset_str(p);
|
|
|
|
|
2014-02-20 14:43:01 +00:00
|
|
|
/* shut down frame, rx/tx and clock signals */
|
2009-11-26 11:10:05 +00:00
|
|
|
ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
|
|
|
|
ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
|
|
|
|
if (rx_buf)
|
|
|
|
ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
|
|
|
|
ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&p->pdev->dev, "failed to shut down hardware\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return words;
|
|
|
|
|
|
|
|
err:
|
|
|
|
sh_msiof_write(p, IER, 0);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
|
|
|
{
|
|
|
|
struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
|
|
|
|
void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
|
|
|
|
void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
|
|
|
|
int bits;
|
|
|
|
int bytes_per_word;
|
|
|
|
int bytes_done;
|
|
|
|
int words;
|
|
|
|
int n;
|
2011-01-21 15:56:42 +00:00
|
|
|
bool swab;
|
2009-11-26 11:10:05 +00:00
|
|
|
|
|
|
|
bits = sh_msiof_spi_bits(spi, t);
|
|
|
|
|
2011-01-21 15:56:42 +00:00
|
|
|
if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
|
|
|
|
bits = 32;
|
|
|
|
swab = true;
|
|
|
|
} else {
|
|
|
|
swab = false;
|
|
|
|
}
|
|
|
|
|
2009-11-26 11:10:05 +00:00
|
|
|
/* setup bytes per word and fifo read/write functions */
|
|
|
|
if (bits <= 8) {
|
|
|
|
bytes_per_word = 1;
|
|
|
|
tx_fifo = sh_msiof_spi_write_fifo_8;
|
|
|
|
rx_fifo = sh_msiof_spi_read_fifo_8;
|
|
|
|
} else if (bits <= 16) {
|
|
|
|
bytes_per_word = 2;
|
|
|
|
if ((unsigned long)t->tx_buf & 0x01)
|
|
|
|
tx_fifo = sh_msiof_spi_write_fifo_16u;
|
|
|
|
else
|
|
|
|
tx_fifo = sh_msiof_spi_write_fifo_16;
|
|
|
|
|
|
|
|
if ((unsigned long)t->rx_buf & 0x01)
|
|
|
|
rx_fifo = sh_msiof_spi_read_fifo_16u;
|
|
|
|
else
|
|
|
|
rx_fifo = sh_msiof_spi_read_fifo_16;
|
2011-01-21 15:56:42 +00:00
|
|
|
} else if (swab) {
|
|
|
|
bytes_per_word = 4;
|
|
|
|
if ((unsigned long)t->tx_buf & 0x03)
|
|
|
|
tx_fifo = sh_msiof_spi_write_fifo_s32u;
|
|
|
|
else
|
|
|
|
tx_fifo = sh_msiof_spi_write_fifo_s32;
|
|
|
|
|
|
|
|
if ((unsigned long)t->rx_buf & 0x03)
|
|
|
|
rx_fifo = sh_msiof_spi_read_fifo_s32u;
|
|
|
|
else
|
|
|
|
rx_fifo = sh_msiof_spi_read_fifo_s32;
|
2009-11-26 11:10:05 +00:00
|
|
|
} else {
|
|
|
|
bytes_per_word = 4;
|
|
|
|
if ((unsigned long)t->tx_buf & 0x03)
|
|
|
|
tx_fifo = sh_msiof_spi_write_fifo_32u;
|
|
|
|
else
|
|
|
|
tx_fifo = sh_msiof_spi_write_fifo_32;
|
|
|
|
|
|
|
|
if ((unsigned long)t->rx_buf & 0x03)
|
|
|
|
rx_fifo = sh_msiof_spi_read_fifo_32u;
|
|
|
|
else
|
|
|
|
rx_fifo = sh_msiof_spi_read_fifo_32;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* setup clocks (clock already enabled in chipselect()) */
|
|
|
|
sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
|
|
|
|
sh_msiof_spi_hz(spi, t));
|
|
|
|
|
|
|
|
/* transfer in fifo sized chunks */
|
|
|
|
words = t->len / bytes_per_word;
|
|
|
|
bytes_done = 0;
|
|
|
|
|
|
|
|
while (bytes_done < t->len) {
|
2011-01-21 15:56:47 +00:00
|
|
|
void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
|
|
|
|
const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
|
2009-11-26 11:10:05 +00:00
|
|
|
n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
|
2011-01-21 15:56:47 +00:00
|
|
|
tx_buf,
|
|
|
|
rx_buf,
|
2009-11-26 11:10:05 +00:00
|
|
|
words, bits);
|
|
|
|
if (n < 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
bytes_done += n * bytes_per_word;
|
|
|
|
words -= n;
|
|
|
|
}
|
|
|
|
|
|
|
|
return bytes_done;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
|
|
|
|
u32 word, u8 bits)
|
|
|
|
{
|
|
|
|
BUG(); /* unused but needed by bitbang code */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-25 10:21:09 +00:00
|
|
|
static const struct sh_msiof_chipdata sh_data = {
|
|
|
|
.tx_fifo_size = 64,
|
|
|
|
.rx_fifo_size = 64,
|
spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
|
|
|
.master_flags = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct sh_msiof_chipdata r8a779x_data = {
|
|
|
|
.tx_fifo_size = 64,
|
|
|
|
.rx_fifo_size = 256,
|
|
|
|
.master_flags = SPI_MASTER_MUST_TX,
|
2014-02-25 10:21:09 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id sh_msiof_match[] = {
|
|
|
|
{ .compatible = "renesas,sh-msiof", .data = &sh_data },
|
|
|
|
{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
|
spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
|
|
|
{ .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
|
|
|
|
{ .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
|
2014-02-25 10:21:09 +00:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, sh_msiof_match);
|
|
|
|
|
2012-12-12 11:54:48 +00:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
|
|
|
|
{
|
|
|
|
struct sh_msiof_spi_info *info;
|
|
|
|
struct device_node *np = dev->of_node;
|
2014-02-25 10:21:08 +00:00
|
|
|
u32 num_cs = 1;
|
2012-12-12 11:54:48 +00:00
|
|
|
|
|
|
|
info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
|
|
|
|
if (!info) {
|
|
|
|
dev_err(dev, "failed to allocate setup data\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Parse the MSIOF properties */
|
|
|
|
of_property_read_u32(np, "num-cs", &num_cs);
|
|
|
|
of_property_read_u32(np, "renesas,tx-fifo-size",
|
|
|
|
&info->tx_fifo_override);
|
|
|
|
of_property_read_u32(np, "renesas,rx-fifo-size",
|
|
|
|
&info->rx_fifo_override);
|
|
|
|
|
|
|
|
info->num_chipselect = num_cs;
|
|
|
|
|
|
|
|
return info;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-11-26 11:10:05 +00:00
|
|
|
static int sh_msiof_spi_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct resource *r;
|
|
|
|
struct spi_master *master;
|
2014-02-25 10:21:09 +00:00
|
|
|
const struct of_device_id *of_id;
|
2009-11-26 11:10:05 +00:00
|
|
|
struct sh_msiof_spi_priv *p;
|
|
|
|
int i;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
|
|
|
|
if (master == NULL) {
|
|
|
|
dev_err(&pdev->dev, "failed to allocate spi master\n");
|
2013-11-28 01:39:42 +00:00
|
|
|
return -ENOMEM;
|
2009-11-26 11:10:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
p = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, p);
|
2014-02-25 10:21:09 +00:00
|
|
|
|
|
|
|
of_id = of_match_device(sh_msiof_match, &pdev->dev);
|
|
|
|
if (of_id) {
|
|
|
|
p->chipdata = of_id->data;
|
2012-12-12 11:54:48 +00:00
|
|
|
p->info = sh_msiof_spi_parse_dt(&pdev->dev);
|
2014-02-25 10:21:09 +00:00
|
|
|
} else {
|
|
|
|
p->chipdata = (const void *)pdev->id_entry->driver_data;
|
2013-07-30 07:58:59 +00:00
|
|
|
p->info = dev_get_platdata(&pdev->dev);
|
2014-02-25 10:21:09 +00:00
|
|
|
}
|
2012-12-12 11:54:48 +00:00
|
|
|
|
|
|
|
if (!p->info) {
|
|
|
|
dev_err(&pdev->dev, "failed to obtain device info\n");
|
|
|
|
ret = -ENXIO;
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
2009-11-26 11:10:05 +00:00
|
|
|
init_completion(&p->done);
|
|
|
|
|
2013-11-28 01:39:42 +00:00
|
|
|
p->clk = devm_clk_get(&pdev->dev, NULL);
|
2009-11-26 11:10:05 +00:00
|
|
|
if (IS_ERR(p->clk)) {
|
2012-11-07 11:40:04 +00:00
|
|
|
dev_err(&pdev->dev, "cannot get clock\n");
|
2009-11-26 11:10:05 +00:00
|
|
|
ret = PTR_ERR(p->clk);
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
|
|
|
i = platform_get_irq(pdev, 0);
|
2013-11-28 01:39:42 +00:00
|
|
|
if (i < 0) {
|
|
|
|
dev_err(&pdev->dev, "cannot get platform IRQ\n");
|
2009-11-26 11:10:05 +00:00
|
|
|
ret = -ENOENT;
|
2013-11-28 01:39:42 +00:00
|
|
|
goto err1;
|
2009-11-26 11:10:05 +00:00
|
|
|
}
|
2013-11-28 01:39:42 +00:00
|
|
|
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
p->mapbase = devm_ioremap_resource(&pdev->dev, r);
|
|
|
|
if (IS_ERR(p->mapbase)) {
|
|
|
|
ret = PTR_ERR(p->mapbase);
|
|
|
|
goto err1;
|
2009-11-26 11:10:05 +00:00
|
|
|
}
|
|
|
|
|
2013-11-28 01:39:42 +00:00
|
|
|
ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
|
|
|
|
dev_name(&pdev->dev), p);
|
2009-11-26 11:10:05 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "unable to request irq\n");
|
2013-11-28 01:39:42 +00:00
|
|
|
goto err1;
|
2009-11-26 11:10:05 +00:00
|
|
|
}
|
|
|
|
|
2013-11-28 01:39:43 +00:00
|
|
|
ret = clk_prepare(p->clk);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "unable to prepare clock\n");
|
|
|
|
goto err1;
|
2009-11-26 11:10:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
p->pdev = pdev;
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
|
|
|
/* Platform data may override FIFO sizes */
|
2014-02-25 10:21:09 +00:00
|
|
|
p->tx_fifo_size = p->chipdata->tx_fifo_size;
|
|
|
|
p->rx_fifo_size = p->chipdata->rx_fifo_size;
|
2009-11-26 11:10:05 +00:00
|
|
|
if (p->info->tx_fifo_override)
|
|
|
|
p->tx_fifo_size = p->info->tx_fifo_override;
|
|
|
|
if (p->info->rx_fifo_override)
|
|
|
|
p->rx_fifo_size = p->info->rx_fifo_override;
|
|
|
|
|
|
|
|
/* init master and bitbang code */
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
|
spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
|
|
|
master->flags = p->chipdata->master_flags;
|
2009-11-26 11:10:05 +00:00
|
|
|
master->bus_num = pdev->id;
|
2014-02-20 14:43:00 +00:00
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
2009-11-26 11:10:05 +00:00
|
|
|
master->num_chipselect = p->info->num_chipselect;
|
2014-02-20 14:43:04 +00:00
|
|
|
master->setup = sh_msiof_spi_setup;
|
2009-11-26 11:10:05 +00:00
|
|
|
master->cleanup = spi_bitbang_cleanup;
|
2014-02-25 10:21:11 +00:00
|
|
|
master->prepare_message = sh_msiof_prepare_message;
|
|
|
|
master->unprepare_message = sh_msiof_unprepare_message;
|
2009-11-26 11:10:05 +00:00
|
|
|
|
|
|
|
p->bitbang.master = master;
|
|
|
|
p->bitbang.chipselect = sh_msiof_spi_chipselect;
|
|
|
|
p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
|
|
|
|
p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
|
|
|
|
p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
|
|
|
|
p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
|
|
|
|
p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
|
|
|
|
p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
|
|
|
|
|
|
|
|
ret = spi_bitbang_start(&p->bitbang);
|
|
|
|
if (ret == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2013-11-28 01:39:43 +00:00
|
|
|
clk_unprepare(p->clk);
|
2009-11-26 11:10:05 +00:00
|
|
|
err1:
|
|
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_msiof_spi_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = spi_bitbang_stop(&p->bitbang);
|
|
|
|
if (!ret) {
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2013-11-28 01:39:43 +00:00
|
|
|
clk_unprepare(p->clk);
|
2009-11-26 11:10:05 +00:00
|
|
|
spi_master_put(p->bitbang.master);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-02-25 10:21:09 +00:00
|
|
|
static struct platform_device_id spi_driver_ids[] = {
|
|
|
|
{ "spi_sh_msiof", (kernel_ulong_t)&sh_data },
|
spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-25 10:21:10 +00:00
|
|
|
{ "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data },
|
|
|
|
{ "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data },
|
2012-12-12 11:54:48 +00:00
|
|
|
{},
|
|
|
|
};
|
2014-02-25 10:21:09 +00:00
|
|
|
MODULE_DEVICE_TABLE(platform, spi_driver_ids);
|
2012-12-12 11:54:48 +00:00
|
|
|
|
2009-11-26 11:10:05 +00:00
|
|
|
static struct platform_driver sh_msiof_spi_drv = {
|
|
|
|
.probe = sh_msiof_spi_probe,
|
|
|
|
.remove = sh_msiof_spi_remove,
|
2014-02-25 10:21:09 +00:00
|
|
|
.id_table = spi_driver_ids,
|
2009-11-26 11:10:05 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "spi_sh_msiof",
|
|
|
|
.owner = THIS_MODULE,
|
2013-03-14 10:01:51 +00:00
|
|
|
.of_match_table = of_match_ptr(sh_msiof_match),
|
2009-11-26 11:10:05 +00:00
|
|
|
},
|
|
|
|
};
|
2011-10-05 17:29:49 +00:00
|
|
|
module_platform_driver(sh_msiof_spi_drv);
|
2009-11-26 11:10:05 +00:00
|
|
|
|
|
|
|
MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_ALIAS("platform:spi_sh_msiof");
|