2019-06-04 08:11:33 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2009-08-18 17:06:25 +00:00
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/*
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* sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
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*
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2012-09-02 20:34:59 +00:00
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* Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org>
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2009-08-18 17:06:25 +00:00
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*
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* See industrialio/accels/sca3000.h for comments.
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*/
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#include <linux/interrupt.h>
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#include <linux/fs.h>
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#include <linux/device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2009-08-18 17:06:25 +00:00
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/sysfs.h>
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2011-07-03 19:49:50 +00:00
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#include <linux/module.h>
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2016-10-08 16:39:02 +00:00
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#include <linux/uaccess.h>
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2012-04-25 14:54:58 +00:00
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/events.h>
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#include <linux/iio/buffer.h>
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2016-10-08 16:39:06 +00:00
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#include <linux/iio/kfifo_buf.h>
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2009-08-18 17:06:25 +00:00
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2016-10-08 16:39:02 +00:00
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#define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
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#define SCA3000_READ_REG(a) ((a) << 2)
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_REVID_ADDR 0x00
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#define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)
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#define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)
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#define SCA3000_REG_STATUS_ADDR 0x02
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#define SCA3000_LOCKED BIT(5)
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#define SCA3000_EEPROM_CS_ERROR BIT(1)
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#define SCA3000_SPI_FRAME_ERROR BIT(0)
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2017-06-27 01:45:22 +00:00
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2016-10-08 16:39:02 +00:00
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/* All reads done using register decrement so no need to directly access LSBs */
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_X_MSB_ADDR 0x05
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#define SCA3000_REG_Y_MSB_ADDR 0x07
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#define SCA3000_REG_Z_MSB_ADDR 0x09
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2016-10-08 16:39:02 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_RING_OUT_ADDR 0x0f
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2016-10-08 16:39:02 +00:00
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/* Temp read untested - the e05 doesn't have the sensor */
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_TEMP_MSB_ADDR 0x13
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2016-10-08 16:39:02 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_MODE_ADDR 0x14
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#define SCA3000_MODE_PROT_MASK 0x28
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#define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7)
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#define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6)
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2016-10-08 16:39:02 +00:00
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/*
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* Free fall detection triggers an interrupt if the acceleration
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* is below a threshold for equivalent of 25cm drop
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*/
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4)
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#define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00
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#define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01
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#define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02
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2016-10-08 16:39:02 +00:00
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/*
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* In motion detection mode the accelerations are band pass filtered
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* (approx 1 - 25Hz) and then a programmable threshold used to trigger
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* and interrupt.
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*/
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03
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#define SCA3000_REG_MODE_MODE_MASK 0x03
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2016-10-08 16:39:02 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_BUF_COUNT_ADDR 0x15
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2016-10-08 16:39:02 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_INT_STATUS_ADDR 0x16
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#define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7)
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#define SCA3000_REG_INT_STATUS_HALF BIT(6)
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2017-06-27 01:45:22 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_INT_STATUS_FREE_FALL BIT(3)
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#define SCA3000_INT_STATUS_Y_TRIGGER BIT(2)
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#define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
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#define SCA3000_INT_STATUS_Z_TRIGGER BIT(0)
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2016-10-08 16:39:02 +00:00
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/* Used to allow access to multiplexed registers */
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_CTRL_SEL_ADDR 0x18
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2016-10-08 16:39:02 +00:00
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/* Only available for SCA3000-D03 and SCA3000-D01 */
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
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#define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
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#define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
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#define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
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#define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
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2016-10-08 16:39:02 +00:00
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/*
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* BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
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* will not function
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*/
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
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#define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0
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#define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10
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#define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08
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#define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04
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#define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03
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#define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02
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#define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01
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2016-10-08 16:39:02 +00:00
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/*
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* Control which motion detector interrupts are on.
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* For now only OR combinations are supported.
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*/
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2016-10-08 16:39:09 +00:00
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#define SCA3000_MD_CTRL_PROT_MASK 0xC0
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#define SCA3000_MD_CTRL_OR_Y BIT(0)
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#define SCA3000_MD_CTRL_OR_X BIT(1)
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#define SCA3000_MD_CTRL_OR_Z BIT(2)
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2016-10-08 16:39:02 +00:00
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/* Currently unsupported */
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2016-10-08 16:39:09 +00:00
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#define SCA3000_MD_CTRL_AND_Y BIT(3)
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#define SCA3000_MD_CTRL_AND_X BIT(4)
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2019-07-21 10:53:53 +00:00
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#define SCA3000_MD_CTRL_AND_Z BIT(5)
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2016-10-08 16:39:02 +00:00
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/*
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* Some control registers of complex access methods requiring this register to
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* be used to remove a lock.
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*/
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_UNLOCK_ADDR 0x1e
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2016-10-08 16:39:02 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_INT_MASK_ADDR 0x21
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#define SCA3000_REG_INT_MASK_PROT_MASK 0x1C
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2017-06-27 01:45:22 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7)
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#define SCA3000_REG_INT_MASK_RING_HALF BIT(6)
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2016-10-08 16:39:02 +00:00
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_INT_MASK_ALL_INTS 0x02
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#define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01
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#define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00
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2016-10-08 16:39:02 +00:00
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/* Values of multiplexed registers (write to ctrl_data after select) */
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2016-10-08 16:39:09 +00:00
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#define SCA3000_REG_CTRL_DATA_ADDR 0x22
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2016-10-08 16:39:02 +00:00
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/*
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* Measurement modes available on some sca3000 series chips. Code assumes others
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* may become available in the future.
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*
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* Bypass - Bypass the low-pass filter in the signal channel so as to increase
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* signal bandwidth.
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*
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* Narrow - Narrow low-pass filtering of the signal channel and half output
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* data rate by decimation.
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*
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* Wide - Widen low-pass filtering of signal channel to increase bandwidth
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*/
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2016-10-08 16:39:09 +00:00
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#define SCA3000_OP_MODE_BYPASS 0x01
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#define SCA3000_OP_MODE_NARROW 0x02
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#define SCA3000_OP_MODE_WIDE 0x04
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2016-10-08 16:39:02 +00:00
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#define SCA3000_MAX_TX 6
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#define SCA3000_MAX_RX 2
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/**
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* struct sca3000_state - device instance state information
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* @us: the associated spi device
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* @info: chip variant information
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* @last_timestamp: the timestamp of the last event
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* @mo_det_use_count: reference counter for the motion detection unit
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* @lock: lock used to protect elements of sca3000_state
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* and the underlying device state.
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* @tx: dma-able transmit buffer
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* @rx: dma-able receive buffer
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**/
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struct sca3000_state {
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struct spi_device *us;
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const struct sca3000_chip_info *info;
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s64 last_timestamp;
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int mo_det_use_count;
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struct mutex lock;
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/* Can these share a cacheline ? */
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2022-05-08 17:55:47 +00:00
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u8 rx[384] __aligned(IIO_DMA_MINALIGN);
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u8 tx[6] __aligned(IIO_DMA_MINALIGN);
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2016-10-08 16:39:02 +00:00
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};
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/**
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* struct sca3000_chip_info - model dependent parameters
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* @scale: scale * 10^-6
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* @temp_output: some devices have temperature sensors.
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* @measurement_mode_freq: normal mode sampling frequency
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2016-10-08 16:39:17 +00:00
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* @measurement_mode_3db_freq: 3db cutoff frequency of the low pass filter for
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* the normal measurement mode.
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2016-10-08 16:39:02 +00:00
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* @option_mode_1: first optional mode. Not all models have one
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* @option_mode_1_freq: option mode 1 sampling frequency
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2016-10-08 16:39:17 +00:00
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* @option_mode_1_3db_freq: 3db cutoff frequency of the low pass filter for
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* the first option mode.
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2016-10-08 16:39:02 +00:00
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* @option_mode_2: second optional mode. Not all chips have one
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* @option_mode_2_freq: option mode 2 sampling frequency
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2016-10-08 16:39:17 +00:00
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* @option_mode_2_3db_freq: 3db cutoff frequency of the low pass filter for
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* the second option mode.
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2020-07-17 16:55:24 +00:00
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* @mot_det_mult_xz: Bit wise multipliers to calculate the threshold
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2016-10-08 16:39:17 +00:00
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* for motion detection in the x and z axis.
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2020-07-17 16:55:24 +00:00
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* @mot_det_mult_y: Bit wise multipliers to calculate the threshold
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2016-10-08 16:39:17 +00:00
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* for motion detection in the y axis.
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2016-10-08 16:39:02 +00:00
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*
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* This structure is used to hold information about the functionality of a given
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* sca3000 variant.
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**/
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struct sca3000_chip_info {
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unsigned int scale;
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bool temp_output;
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int measurement_mode_freq;
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2016-10-08 16:39:10 +00:00
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int measurement_mode_3db_freq;
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2016-10-08 16:39:02 +00:00
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int option_mode_1;
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int option_mode_1_freq;
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2016-10-08 16:39:10 +00:00
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int option_mode_1_3db_freq;
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2016-10-08 16:39:02 +00:00
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int option_mode_2;
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int option_mode_2_freq;
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2016-10-08 16:39:10 +00:00
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int option_mode_2_3db_freq;
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2016-10-08 16:39:02 +00:00
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int mot_det_mult_xz[6];
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int mot_det_mult_y[7];
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};
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2009-08-18 17:06:25 +00:00
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enum sca3000_variant {
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d01,
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e02,
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e04,
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e05,
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};
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2014-01-13 21:28:00 +00:00
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/*
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* Note where option modes are not defined, the chip simply does not
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2009-08-18 17:06:25 +00:00
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* support any.
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* Other chips in the sca3000 series use i2c and are not included here.
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*
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* Some of these devices are only listed in the family data sheet and
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* do not actually appear to be available.
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*/
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static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
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2011-05-18 13:41:44 +00:00
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[d01] = {
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2011-05-18 13:41:01 +00:00
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.scale = 7357,
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2009-08-18 17:06:25 +00:00
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.temp_output = true,
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.measurement_mode_freq = 250,
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2016-10-08 16:39:10 +00:00
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.measurement_mode_3db_freq = 45,
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2009-08-18 17:06:25 +00:00
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.option_mode_1 = SCA3000_OP_MODE_BYPASS,
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.option_mode_1_freq = 250,
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2016-10-08 16:39:10 +00:00
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.option_mode_1_3db_freq = 70,
|
2011-05-18 13:41:01 +00:00
|
|
|
.mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
|
|
|
|
.mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
|
2011-05-18 13:41:44 +00:00
|
|
|
},
|
|
|
|
[e02] = {
|
2011-05-18 13:41:01 +00:00
|
|
|
.scale = 9810,
|
2009-08-18 17:06:25 +00:00
|
|
|
.measurement_mode_freq = 125,
|
2016-10-08 16:39:10 +00:00
|
|
|
.measurement_mode_3db_freq = 40,
|
2009-08-18 17:06:25 +00:00
|
|
|
.option_mode_1 = SCA3000_OP_MODE_NARROW,
|
|
|
|
.option_mode_1_freq = 63,
|
2016-10-08 16:39:10 +00:00
|
|
|
.option_mode_1_3db_freq = 11,
|
2011-05-18 13:41:01 +00:00
|
|
|
.mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
|
|
|
|
.mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
|
2011-05-18 13:41:44 +00:00
|
|
|
},
|
|
|
|
[e04] = {
|
2011-05-18 13:41:01 +00:00
|
|
|
.scale = 19620,
|
2009-08-18 17:06:25 +00:00
|
|
|
.measurement_mode_freq = 100,
|
2016-10-08 16:39:10 +00:00
|
|
|
.measurement_mode_3db_freq = 38,
|
2009-08-18 17:06:25 +00:00
|
|
|
.option_mode_1 = SCA3000_OP_MODE_NARROW,
|
|
|
|
.option_mode_1_freq = 50,
|
2016-10-08 16:39:10 +00:00
|
|
|
.option_mode_1_3db_freq = 9,
|
2009-08-18 17:06:25 +00:00
|
|
|
.option_mode_2 = SCA3000_OP_MODE_WIDE,
|
|
|
|
.option_mode_2_freq = 400,
|
2016-10-08 16:39:10 +00:00
|
|
|
.option_mode_2_3db_freq = 70,
|
2011-05-18 13:41:01 +00:00
|
|
|
.mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
|
|
|
|
.mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
|
2011-05-18 13:41:44 +00:00
|
|
|
},
|
|
|
|
[e05] = {
|
2011-05-18 13:41:01 +00:00
|
|
|
.scale = 61313,
|
2009-08-18 17:06:25 +00:00
|
|
|
.measurement_mode_freq = 200,
|
2016-10-08 16:39:10 +00:00
|
|
|
.measurement_mode_3db_freq = 60,
|
2009-08-18 17:06:25 +00:00
|
|
|
.option_mode_1 = SCA3000_OP_MODE_NARROW,
|
|
|
|
.option_mode_1_freq = 50,
|
2016-10-08 16:39:10 +00:00
|
|
|
.option_mode_1_3db_freq = 9,
|
2009-08-18 17:06:25 +00:00
|
|
|
.option_mode_2 = SCA3000_OP_MODE_WIDE,
|
|
|
|
.option_mode_2_freq = 400,
|
2016-10-08 16:39:10 +00:00
|
|
|
.option_mode_2_3db_freq = 75,
|
2011-05-18 13:41:01 +00:00
|
|
|
.mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
|
|
|
|
.mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
|
2009-08-18 17:06:25 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2016-10-08 16:39:02 +00:00
|
|
|
static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
|
|
|
st->tx[0] = SCA3000_WRITE_REG(address);
|
|
|
|
st->tx[1] = val;
|
2011-05-18 13:41:01 +00:00
|
|
|
return spi_write(st->us, st->tx, 2);
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-08 16:39:02 +00:00
|
|
|
static int sca3000_read_data_short(struct sca3000_state *st,
|
2016-10-08 16:39:16 +00:00
|
|
|
u8 reg_address_high,
|
|
|
|
int len)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-05-18 13:41:01 +00:00
|
|
|
struct spi_transfer xfer[2] = {
|
|
|
|
{
|
|
|
|
.len = 1,
|
|
|
|
.tx_buf = st->tx,
|
|
|
|
}, {
|
|
|
|
.len = len,
|
|
|
|
.rx_buf = st->rx,
|
|
|
|
}
|
2009-08-18 17:06:25 +00:00
|
|
|
};
|
|
|
|
st->tx[0] = SCA3000_READ_REG(reg_address_high);
|
|
|
|
|
2013-01-09 17:31:00 +00:00
|
|
|
return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
2011-05-18 13:41:01 +00:00
|
|
|
|
2009-08-18 17:06:25 +00:00
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_reg_lock_on() - test if the ctrl register lock is on
|
|
|
|
* @st: Driver specific device instance data.
|
2009-08-18 17:06:25 +00:00
|
|
|
*
|
|
|
|
* Lock must be held.
|
|
|
|
**/
|
|
|
|
static int sca3000_reg_lock_on(struct sca3000_state *st)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
return !(st->rx[0] & SCA3000_LOCKED);
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* __sca3000_unlock_reg_lock() - unlock the control registers
|
|
|
|
* @st: Driver specific device instance data.
|
2009-08-18 17:06:25 +00:00
|
|
|
*
|
|
|
|
* Note the device does not appear to support doing this in a single transfer.
|
|
|
|
* This should only ever be used as part of ctrl reg read.
|
|
|
|
* Lock must be held before calling this
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2009-08-18 17:06:25 +00:00
|
|
|
static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
|
|
|
|
{
|
|
|
|
struct spi_transfer xfer[3] = {
|
|
|
|
{
|
|
|
|
.len = 2,
|
|
|
|
.cs_change = 1,
|
|
|
|
.tx_buf = st->tx,
|
|
|
|
}, {
|
|
|
|
.len = 2,
|
|
|
|
.cs_change = 1,
|
|
|
|
.tx_buf = st->tx + 2,
|
|
|
|
}, {
|
|
|
|
.len = 2,
|
|
|
|
.tx_buf = st->tx + 4,
|
|
|
|
},
|
|
|
|
};
|
2016-10-08 16:39:09 +00:00
|
|
|
st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
|
2009-08-18 17:06:25 +00:00
|
|
|
st->tx[1] = 0x00;
|
2016-10-08 16:39:09 +00:00
|
|
|
st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
|
2009-08-18 17:06:25 +00:00
|
|
|
st->tx[3] = 0x50;
|
2016-10-08 16:39:09 +00:00
|
|
|
st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
|
2009-08-18 17:06:25 +00:00
|
|
|
st->tx[5] = 0xA0;
|
|
|
|
|
2013-01-09 17:31:00 +00:00
|
|
|
return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-03-14 16:46:54 +00:00
|
|
|
* sca3000_write_ctrl_reg() - write to a lock protect ctrl register
|
2016-10-08 16:39:17 +00:00
|
|
|
* @st: Driver specific device instance data.
|
2009-08-18 17:06:25 +00:00
|
|
|
* @sel: selects which registers we wish to write to
|
|
|
|
* @val: the value to be written
|
|
|
|
*
|
|
|
|
* Certain control registers are protected against overwriting by the lock
|
|
|
|
* register and use a shared write address. This function allows writing of
|
|
|
|
* these registers.
|
|
|
|
* Lock must be held.
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2009-08-18 17:06:25 +00:00
|
|
|
static int sca3000_write_ctrl_reg(struct sca3000_state *st,
|
2015-10-28 23:01:50 +00:00
|
|
|
u8 sel,
|
2009-08-18 17:06:25 +00:00
|
|
|
uint8_t val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sca3000_reg_lock_on(st);
|
|
|
|
if (ret < 0)
|
|
|
|
goto error_ret;
|
|
|
|
if (ret) {
|
|
|
|
ret = __sca3000_unlock_reg_lock(st);
|
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set the control select register */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
|
|
|
|
/* Write the actual value into the register */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
|
|
|
error_ret:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-03-14 16:46:54 +00:00
|
|
|
* sca3000_read_ctrl_reg() - read from lock protected control register.
|
2016-10-08 16:39:17 +00:00
|
|
|
* @st: Driver specific device instance data.
|
|
|
|
* @ctrl_reg: Which ctrl register do we want to read.
|
2009-08-18 17:06:25 +00:00
|
|
|
*
|
|
|
|
* Lock must be held.
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2009-08-18 17:06:25 +00:00
|
|
|
static int sca3000_read_ctrl_reg(struct sca3000_state *st,
|
2011-05-18 13:41:01 +00:00
|
|
|
u8 ctrl_reg)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sca3000_reg_lock_on(st);
|
|
|
|
if (ret < 0)
|
|
|
|
goto error_ret;
|
|
|
|
if (ret) {
|
|
|
|
ret = __sca3000_unlock_reg_lock(st);
|
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
/* Set the control select register */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
|
2011-05-18 13:41:01 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
2016-02-18 21:22:29 +00:00
|
|
|
return st->rx[0];
|
2009-08-18 17:06:25 +00:00
|
|
|
error_ret:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-03-14 16:46:54 +00:00
|
|
|
* sca3000_print_rev() - sysfs interface to read the chip revision number
|
2016-10-08 16:39:17 +00:00
|
|
|
* @indio_dev: Device instance specific generic IIO data.
|
|
|
|
* Driver specific device instance data can be obtained via
|
2022-06-04 04:05:41 +00:00
|
|
|
* iio_priv(indio_dev)
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2016-10-08 16:39:14 +00:00
|
|
|
static int sca3000_print_rev(struct iio_dev *indio_dev)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2016-10-08 16:39:14 +00:00
|
|
|
int ret;
|
2011-10-06 16:14:36 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error_ret;
|
2016-10-08 16:39:14 +00:00
|
|
|
dev_info(&indio_dev->dev,
|
|
|
|
"sca3000 revision major=%lu, minor=%lu\n",
|
|
|
|
st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
|
|
|
|
st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
|
2009-08-18 17:06:25 +00:00
|
|
|
error_ret:
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
|
2016-10-08 16:39:14 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-08 16:39:12 +00:00
|
|
|
static ssize_t
|
|
|
|
sca3000_show_available_3db_freqs(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
|
|
|
int len;
|
|
|
|
|
|
|
|
len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
|
|
|
|
if (st->info->option_mode_1)
|
|
|
|
len += sprintf(buf + len, " %d",
|
|
|
|
st->info->option_mode_1_3db_freq);
|
|
|
|
if (st->info->option_mode_2)
|
|
|
|
len += sprintf(buf + len, " %d",
|
|
|
|
st->info->option_mode_2_3db_freq);
|
|
|
|
len += sprintf(buf + len, "\n");
|
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2016-10-08 16:39:12 +00:00
|
|
|
static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
|
|
|
|
S_IRUGO, sca3000_show_available_3db_freqs,
|
|
|
|
NULL, 0);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2013-10-07 14:11:00 +00:00
|
|
|
static const struct iio_event_spec sca3000_event = {
|
|
|
|
.type = IIO_EV_TYPE_MAG,
|
|
|
|
.dir = IIO_EV_DIR_RISING,
|
|
|
|
.mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
|
|
|
|
};
|
2011-05-18 13:41:01 +00:00
|
|
|
|
2016-10-08 16:39:06 +00:00
|
|
|
/*
|
|
|
|
* Note the hack in the number of bits to pretend we have 2 more than
|
|
|
|
* we do in the fifo.
|
|
|
|
*/
|
2012-04-13 09:42:53 +00:00
|
|
|
#define SCA3000_CHAN(index, mod) \
|
|
|
|
{ \
|
|
|
|
.type = IIO_ACCEL, \
|
|
|
|
.modified = 1, \
|
|
|
|
.channel2 = mod, \
|
2013-02-27 19:36:45 +00:00
|
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
|
2016-10-08 16:39:10 +00:00
|
|
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
|
|
|
|
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
|
2016-09-13 19:14:14 +00:00
|
|
|
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
|
2012-04-13 09:42:53 +00:00
|
|
|
.address = index, \
|
|
|
|
.scan_index = index, \
|
|
|
|
.scan_type = { \
|
|
|
|
.sign = 's', \
|
2016-10-08 16:39:06 +00:00
|
|
|
.realbits = 13, \
|
2012-04-13 09:42:53 +00:00
|
|
|
.storagebits = 16, \
|
2016-10-08 16:39:06 +00:00
|
|
|
.shift = 3, \
|
|
|
|
.endianness = IIO_BE, \
|
2012-04-13 09:42:53 +00:00
|
|
|
}, \
|
2013-10-07 14:11:00 +00:00
|
|
|
.event_spec = &sca3000_event, \
|
|
|
|
.num_event_specs = 1, \
|
2016-08-23 02:45:05 +00:00
|
|
|
}
|
2012-04-13 09:42:53 +00:00
|
|
|
|
2016-10-08 16:39:08 +00:00
|
|
|
static const struct iio_event_spec sca3000_freefall_event_spec = {
|
|
|
|
.type = IIO_EV_TYPE_MAG,
|
|
|
|
.dir = IIO_EV_DIR_FALLING,
|
|
|
|
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
|
|
|
|
BIT(IIO_EV_INFO_PERIOD),
|
|
|
|
};
|
|
|
|
|
2012-08-09 07:51:00 +00:00
|
|
|
static const struct iio_chan_spec sca3000_channels[] = {
|
2012-04-13 09:42:53 +00:00
|
|
|
SCA3000_CHAN(0, IIO_MOD_X),
|
|
|
|
SCA3000_CHAN(1, IIO_MOD_Y),
|
|
|
|
SCA3000_CHAN(2, IIO_MOD_Z),
|
2016-10-08 16:39:08 +00:00
|
|
|
{
|
|
|
|
.type = IIO_ACCEL,
|
|
|
|
.modified = 1,
|
|
|
|
.channel2 = IIO_MOD_X_AND_Y_AND_Z,
|
|
|
|
.scan_index = -1, /* Fake channel */
|
|
|
|
.event_spec = &sca3000_freefall_event_spec,
|
|
|
|
.num_event_specs = 1,
|
|
|
|
},
|
2011-05-18 13:41:01 +00:00
|
|
|
};
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2014-01-13 21:28:00 +00:00
|
|
|
static const struct iio_chan_spec sca3000_channels_with_temp[] = {
|
|
|
|
SCA3000_CHAN(0, IIO_MOD_X),
|
|
|
|
SCA3000_CHAN(1, IIO_MOD_Y),
|
|
|
|
SCA3000_CHAN(2, IIO_MOD_Z),
|
|
|
|
{
|
|
|
|
.type = IIO_TEMP,
|
|
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
|
|
|
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
|
|
|
|
BIT(IIO_CHAN_INFO_OFFSET),
|
2014-11-26 17:55:10 +00:00
|
|
|
/* No buffer support */
|
|
|
|
.scan_index = -1,
|
2021-11-04 08:24:04 +00:00
|
|
|
.scan_type = {
|
|
|
|
.sign = 'u',
|
|
|
|
.realbits = 9,
|
|
|
|
.storagebits = 16,
|
|
|
|
.shift = 5,
|
|
|
|
.endianness = IIO_BE,
|
|
|
|
},
|
2014-01-13 21:28:00 +00:00
|
|
|
},
|
2016-10-08 16:39:08 +00:00
|
|
|
{
|
|
|
|
.type = IIO_ACCEL,
|
|
|
|
.modified = 1,
|
|
|
|
.channel2 = IIO_MOD_X_AND_Y_AND_Z,
|
|
|
|
.scan_index = -1, /* Fake channel */
|
|
|
|
.event_spec = &sca3000_freefall_event_spec,
|
|
|
|
.num_event_specs = 1,
|
|
|
|
},
|
2014-01-13 21:28:00 +00:00
|
|
|
};
|
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
static u8 sca3000_addresses[3][3] = {
|
2016-10-08 16:39:09 +00:00
|
|
|
[0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
|
2011-05-18 13:41:01 +00:00
|
|
|
SCA3000_MD_CTRL_OR_X},
|
2016-10-08 16:39:09 +00:00
|
|
|
[1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
|
2011-05-18 13:41:01 +00:00
|
|
|
SCA3000_MD_CTRL_OR_Y},
|
2016-10-08 16:39:09 +00:00
|
|
|
[2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
|
2011-05-18 13:41:01 +00:00
|
|
|
SCA3000_MD_CTRL_OR_Z},
|
|
|
|
};
|
|
|
|
|
2016-09-13 19:14:14 +00:00
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* __sca3000_get_base_freq() - obtain mode specific base frequency
|
|
|
|
* @st: Private driver specific device instance specific state.
|
|
|
|
* @info: chip type specific information.
|
|
|
|
* @base_freq: Base frequency for the current measurement mode.
|
2016-09-13 19:14:14 +00:00
|
|
|
*
|
|
|
|
* lock must be held
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2016-09-13 19:14:14 +00:00
|
|
|
static inline int __sca3000_get_base_freq(struct sca3000_state *st,
|
|
|
|
const struct sca3000_chip_info *info,
|
|
|
|
int *base_freq)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
2016-09-13 19:14:14 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
2016-10-08 16:39:09 +00:00
|
|
|
switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
|
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
|
2016-09-13 19:14:14 +00:00
|
|
|
*base_freq = info->measurement_mode_freq;
|
|
|
|
break;
|
2016-10-08 16:39:09 +00:00
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_OP_1:
|
2016-09-13 19:14:14 +00:00
|
|
|
*base_freq = info->option_mode_1_freq;
|
|
|
|
break;
|
2016-10-08 16:39:09 +00:00
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_OP_2:
|
2016-09-13 19:14:14 +00:00
|
|
|
*base_freq = info->option_mode_2_freq;
|
|
|
|
break;
|
2016-09-22 09:43:42 +00:00
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
2016-09-13 19:14:14 +00:00
|
|
|
}
|
|
|
|
error_ret:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
|
|
|
|
* @st: Private driver specific device instance specific state.
|
|
|
|
* @val: The frequency read back.
|
2016-09-13 19:14:14 +00:00
|
|
|
*
|
|
|
|
* lock must be held
|
|
|
|
**/
|
2016-10-08 16:39:17 +00:00
|
|
|
static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
|
2016-09-13 19:14:14 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = __sca3000_get_base_freq(st, st->info, val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (*val > 0) {
|
2016-10-08 16:39:09 +00:00
|
|
|
ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
|
2016-09-13 19:14:14 +00:00
|
|
|
switch (ret) {
|
2016-10-08 16:39:09 +00:00
|
|
|
case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
|
2016-09-13 19:14:14 +00:00
|
|
|
*val /= 2;
|
|
|
|
break;
|
2016-10-08 16:39:09 +00:00
|
|
|
case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
|
2016-09-13 19:14:14 +00:00
|
|
|
*val /= 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
|
|
|
|
* @st: Private driver specific device instance specific state.
|
|
|
|
* @val: The frequency desired.
|
2016-09-13 19:14:14 +00:00
|
|
|
*
|
|
|
|
* lock must be held
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
|
|
|
static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
|
2016-09-13 19:14:14 +00:00
|
|
|
{
|
|
|
|
int ret, base_freq, ctrlval;
|
|
|
|
|
|
|
|
ret = __sca3000_get_base_freq(st, st->info, &base_freq);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2016-10-08 16:39:09 +00:00
|
|
|
ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
|
2016-09-13 19:14:14 +00:00
|
|
|
|
|
|
|
if (val == base_freq / 2)
|
2016-10-08 16:39:09 +00:00
|
|
|
ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
|
2016-09-13 19:14:14 +00:00
|
|
|
if (val == base_freq / 4)
|
2016-10-08 16:39:09 +00:00
|
|
|
ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
|
2016-09-13 19:14:14 +00:00
|
|
|
else if (val != base_freq)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
|
|
|
|
ctrlval);
|
|
|
|
}
|
|
|
|
|
2016-10-08 16:39:10 +00:00
|
|
|
static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* mask bottom 2 bits - only ones that are relevant */
|
|
|
|
st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
|
|
|
|
switch (st->rx[0]) {
|
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
|
|
|
|
*val = st->info->measurement_mode_3db_freq;
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
|
|
|
|
return -EBUSY;
|
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_OP_1:
|
|
|
|
*val = st->info->option_mode_1_3db_freq;
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_OP_2:
|
|
|
|
*val = st->info->option_mode_2_3db_freq;
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-08 16:39:12 +00:00
|
|
|
static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int mode;
|
|
|
|
|
|
|
|
if (val == st->info->measurement_mode_3db_freq)
|
|
|
|
mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
|
|
|
|
else if (st->info->option_mode_1 &&
|
|
|
|
(val == st->info->option_mode_1_3db_freq))
|
|
|
|
mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
|
|
|
|
else if (st->info->option_mode_2 &&
|
|
|
|
(val == st->info->option_mode_2_3db_freq))
|
|
|
|
mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
|
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
|
|
|
|
st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
|
|
|
|
|
|
|
|
return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
|
|
|
|
}
|
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
static int sca3000_read_raw(struct iio_dev *indio_dev,
|
|
|
|
struct iio_chan_spec const *chan,
|
|
|
|
int *val,
|
|
|
|
int *val2,
|
|
|
|
long mask)
|
|
|
|
{
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2011-05-18 13:41:01 +00:00
|
|
|
int ret;
|
|
|
|
u8 address;
|
|
|
|
|
|
|
|
switch (mask) {
|
2012-04-15 16:41:17 +00:00
|
|
|
case IIO_CHAN_INFO_RAW:
|
2011-05-18 13:41:01 +00:00
|
|
|
mutex_lock(&st->lock);
|
2014-01-13 21:28:00 +00:00
|
|
|
if (chan->type == IIO_ACCEL) {
|
|
|
|
if (st->mo_det_use_count) {
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
address = sca3000_addresses[chan->address][0];
|
|
|
|
ret = sca3000_read_data_short(st, address, 2);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return ret;
|
|
|
|
}
|
2021-11-04 08:24:04 +00:00
|
|
|
*val = sign_extend32(be16_to_cpup((__be16 *)st->rx) >>
|
|
|
|
chan->scan_type.shift,
|
|
|
|
chan->scan_type.realbits - 1);
|
2014-01-13 21:28:00 +00:00
|
|
|
} else {
|
|
|
|
/* get the temperature when available */
|
|
|
|
ret = sca3000_read_data_short(st,
|
2016-10-08 16:39:09 +00:00
|
|
|
SCA3000_REG_TEMP_MSB_ADDR,
|
2015-10-28 23:01:49 +00:00
|
|
|
2);
|
2014-01-13 21:28:00 +00:00
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return ret;
|
|
|
|
}
|
2021-11-04 08:24:04 +00:00
|
|
|
*val = (be16_to_cpup((__be16 *)st->rx) >>
|
|
|
|
chan->scan_type.shift) &
|
|
|
|
GENMASK(chan->scan_type.realbits - 1, 0);
|
2011-05-18 13:41:01 +00:00
|
|
|
}
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return IIO_VAL_INT;
|
2011-10-26 16:41:36 +00:00
|
|
|
case IIO_CHAN_INFO_SCALE:
|
2011-05-18 13:41:01 +00:00
|
|
|
*val = 0;
|
|
|
|
if (chan->type == IIO_ACCEL)
|
|
|
|
*val2 = st->info->scale;
|
|
|
|
else /* temperature */
|
|
|
|
*val2 = 555556;
|
|
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
2014-01-13 21:28:00 +00:00
|
|
|
case IIO_CHAN_INFO_OFFSET:
|
|
|
|
*val = -214;
|
|
|
|
*val2 = 600000;
|
|
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
2016-09-13 19:14:14 +00:00
|
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:17 +00:00
|
|
|
ret = sca3000_read_raw_samp_freq(st, val);
|
2016-09-13 19:14:14 +00:00
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return ret ? ret : IIO_VAL_INT;
|
2016-10-08 16:39:10 +00:00
|
|
|
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
|
|
|
|
mutex_lock(&st->lock);
|
|
|
|
ret = sca3000_read_3db_freq(st, val);
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return ret;
|
2016-09-13 19:14:14 +00:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sca3000_write_raw(struct iio_dev *indio_dev,
|
|
|
|
struct iio_chan_spec const *chan,
|
|
|
|
int val, int val2, long mask)
|
|
|
|
{
|
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (mask) {
|
|
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
|
|
if (val2)
|
|
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:17 +00:00
|
|
|
ret = sca3000_write_raw_samp_freq(st, val);
|
2016-09-13 19:14:14 +00:00
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return ret;
|
2016-10-08 16:39:12 +00:00
|
|
|
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
|
|
|
|
if (val2)
|
|
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&st->lock);
|
|
|
|
ret = sca3000_write_3db_freq(st, val);
|
|
|
|
mutex_unlock(&st->lock);
|
2018-07-07 17:44:01 +00:00
|
|
|
return ret;
|
2011-05-18 13:41:01 +00:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2016-09-13 19:14:14 +00:00
|
|
|
|
|
|
|
return ret;
|
2011-05-18 13:41:01 +00:00
|
|
|
}
|
2009-08-18 17:06:25 +00:00
|
|
|
|
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_read_av_freq() - sysfs function to get available frequencies
|
|
|
|
* @dev: Device structure for this device.
|
|
|
|
* @attr: Description of the attribute.
|
|
|
|
* @buf: Incoming string
|
2009-08-18 17:06:25 +00:00
|
|
|
*
|
|
|
|
* The later modes are only relevant to the ring buffer - and depend on current
|
|
|
|
* mode. Note that data sheet gives rather wide tolerances for these so integer
|
|
|
|
* division will give good enough answer and not all chips have them specified
|
|
|
|
* at all.
|
|
|
|
**/
|
|
|
|
static ssize_t sca3000_read_av_freq(struct device *dev,
|
2015-10-28 23:01:49 +00:00
|
|
|
struct device_attribute *attr,
|
|
|
|
char *buf)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2012-05-12 13:39:43 +00:00
|
|
|
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2011-05-18 13:41:01 +00:00
|
|
|
int len = 0, ret, val;
|
|
|
|
|
2009-08-18 17:06:25 +00:00
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
2011-05-18 13:41:01 +00:00
|
|
|
val = st->rx[0];
|
2009-08-18 17:06:25 +00:00
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
2011-05-18 13:41:01 +00:00
|
|
|
|
2016-10-08 16:39:09 +00:00
|
|
|
switch (val & SCA3000_REG_MODE_MODE_MASK) {
|
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
|
2009-08-18 17:06:25 +00:00
|
|
|
len += sprintf(buf + len, "%d %d %d\n",
|
|
|
|
st->info->measurement_mode_freq,
|
2015-10-28 23:01:48 +00:00
|
|
|
st->info->measurement_mode_freq / 2,
|
|
|
|
st->info->measurement_mode_freq / 4);
|
2009-08-18 17:06:25 +00:00
|
|
|
break;
|
2016-10-08 16:39:09 +00:00
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_OP_1:
|
2009-08-18 17:06:25 +00:00
|
|
|
len += sprintf(buf + len, "%d %d %d\n",
|
|
|
|
st->info->option_mode_1_freq,
|
2015-10-28 23:01:48 +00:00
|
|
|
st->info->option_mode_1_freq / 2,
|
|
|
|
st->info->option_mode_1_freq / 4);
|
2009-08-18 17:06:25 +00:00
|
|
|
break;
|
2016-10-08 16:39:09 +00:00
|
|
|
case SCA3000_REG_MODE_MEAS_MODE_OP_2:
|
2009-08-18 17:06:25 +00:00
|
|
|
len += sprintf(buf + len, "%d %d %d\n",
|
|
|
|
st->info->option_mode_2_freq,
|
2015-10-28 23:01:48 +00:00
|
|
|
st->info->option_mode_2_freq / 2,
|
|
|
|
st->info->option_mode_2_freq / 4);
|
2009-08-18 17:06:25 +00:00
|
|
|
break;
|
2010-05-23 07:10:30 +00:00
|
|
|
}
|
2009-08-18 17:06:25 +00:00
|
|
|
return len;
|
|
|
|
error_ret:
|
|
|
|
return ret;
|
|
|
|
}
|
2015-10-28 23:01:51 +00:00
|
|
|
|
2014-01-13 21:28:00 +00:00
|
|
|
/*
|
|
|
|
* Should only really be registered if ring buffer support is compiled in.
|
2009-08-18 17:06:25 +00:00
|
|
|
* Does no harm however and doing it right would add a fair bit of complexity
|
|
|
|
*/
|
2010-05-04 13:42:58 +00:00
|
|
|
static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2020-07-17 16:55:24 +00:00
|
|
|
/*
|
2016-10-08 16:39:08 +00:00
|
|
|
* sca3000_read_event_value() - query of a threshold or period
|
2020-07-17 16:55:24 +00:00
|
|
|
*/
|
2016-10-08 16:39:08 +00:00
|
|
|
static int sca3000_read_event_value(struct iio_dev *indio_dev,
|
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
enum iio_event_info info,
|
|
|
|
int *val, int *val2)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2019-06-21 09:18:28 +00:00
|
|
|
long ret;
|
|
|
|
int i;
|
2016-10-08 16:39:11 +00:00
|
|
|
|
2016-10-08 16:39:08 +00:00
|
|
|
switch (info) {
|
|
|
|
case IIO_EV_INFO_VALUE:
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:11 +00:00
|
|
|
ret = sca3000_read_ctrl_reg(st,
|
|
|
|
sca3000_addresses[chan->address][1]);
|
2016-10-08 16:39:08 +00:00
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
*val = 0;
|
2016-10-08 16:39:11 +00:00
|
|
|
if (chan->channel2 == IIO_MOD_Y)
|
2019-06-21 09:18:28 +00:00
|
|
|
for_each_set_bit(i, &ret,
|
2016-10-08 16:39:08 +00:00
|
|
|
ARRAY_SIZE(st->info->mot_det_mult_y))
|
|
|
|
*val += st->info->mot_det_mult_y[i];
|
|
|
|
else
|
2019-06-21 09:18:28 +00:00
|
|
|
for_each_set_bit(i, &ret,
|
2016-10-08 16:39:08 +00:00
|
|
|
ARRAY_SIZE(st->info->mot_det_mult_xz))
|
|
|
|
*val += st->info->mot_det_mult_xz[i];
|
2014-07-08 00:22:00 +00:00
|
|
|
|
2016-10-08 16:39:08 +00:00
|
|
|
return IIO_VAL_INT;
|
|
|
|
case IIO_EV_INFO_PERIOD:
|
|
|
|
*val = 0;
|
|
|
|
*val2 = 226000;
|
|
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-03-14 16:46:54 +00:00
|
|
|
* sca3000_write_event_value() - control of threshold and period
|
2016-10-08 16:39:17 +00:00
|
|
|
* @indio_dev: Device instance specific IIO information.
|
|
|
|
* @chan: Description of the channel for which the event is being
|
|
|
|
* configured.
|
|
|
|
* @type: The type of event being configured, here magnitude rising
|
|
|
|
* as everything else is read only.
|
|
|
|
* @dir: Direction of the event (here rising)
|
|
|
|
* @info: What information about the event are we configuring.
|
|
|
|
* Here the threshold only.
|
|
|
|
* @val: Integer part of the value being written..
|
|
|
|
* @val2: Non integer part of the value being written. Here always 0.
|
|
|
|
*/
|
2016-10-08 16:39:08 +00:00
|
|
|
static int sca3000_write_event_value(struct iio_dev *indio_dev,
|
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
enum iio_event_info info,
|
|
|
|
int val, int val2)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
int ret;
|
2011-05-18 13:41:01 +00:00
|
|
|
int i;
|
|
|
|
u8 nonlinear = 0;
|
|
|
|
|
2016-10-08 16:39:11 +00:00
|
|
|
if (chan->channel2 == IIO_MOD_Y) {
|
2011-05-18 13:41:01 +00:00
|
|
|
i = ARRAY_SIZE(st->info->mot_det_mult_y);
|
|
|
|
while (i > 0)
|
|
|
|
if (val >= st->info->mot_det_mult_y[--i]) {
|
|
|
|
nonlinear |= (1 << i);
|
|
|
|
val -= st->info->mot_det_mult_y[i];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
i = ARRAY_SIZE(st->info->mot_det_mult_xz);
|
|
|
|
while (i > 0)
|
|
|
|
if (val >= st->info->mot_det_mult_xz[--i]) {
|
|
|
|
nonlinear |= (1 << i);
|
|
|
|
val -= st->info->mot_det_mult_xz[i];
|
|
|
|
}
|
|
|
|
}
|
2009-08-18 17:06:25 +00:00
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:11 +00:00
|
|
|
ret = sca3000_write_ctrl_reg(st,
|
|
|
|
sca3000_addresses[chan->address][1],
|
|
|
|
nonlinear);
|
2009-08-18 17:06:25 +00:00
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct attribute *sca3000_attributes[] = {
|
2016-10-08 16:39:12 +00:00
|
|
|
&iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
|
2010-05-04 13:42:58 +00:00
|
|
|
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
|
2009-08-18 17:06:25 +00:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group sca3000_attribute_group = {
|
|
|
|
.attrs = sca3000_attributes,
|
|
|
|
};
|
|
|
|
|
2016-10-08 16:39:06 +00:00
|
|
|
static int sca3000_read_data(struct sca3000_state *st,
|
|
|
|
u8 reg_address_high,
|
|
|
|
u8 *rx,
|
|
|
|
int len)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
struct spi_transfer xfer[2] = {
|
|
|
|
{
|
|
|
|
.len = 1,
|
|
|
|
.tx_buf = st->tx,
|
|
|
|
}, {
|
|
|
|
.len = len,
|
|
|
|
.rx_buf = rx,
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
st->tx[0] = SCA3000_READ_REG(reg_address_high);
|
|
|
|
ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
|
|
|
|
if (ret) {
|
2020-05-06 03:52:06 +00:00
|
|
|
dev_err(&st->us->dev, "problem reading register\n");
|
2016-10-08 16:39:06 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-10-08 16:39:02 +00:00
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_ring_int_process() - ring specific interrupt handling.
|
|
|
|
* @val: Value of the interrupt status register.
|
|
|
|
* @indio_dev: Device instance specific IIO device structure.
|
|
|
|
*/
|
2016-10-08 16:39:06 +00:00
|
|
|
static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
|
2016-10-08 16:39:02 +00:00
|
|
|
{
|
2016-10-08 16:39:06 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
|
|
|
int ret, i, num_available;
|
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:09 +00:00
|
|
|
|
|
|
|
if (val & SCA3000_REG_INT_STATUS_HALF) {
|
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
|
2016-10-08 16:39:06 +00:00
|
|
|
1);
|
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
num_available = st->rx[0];
|
|
|
|
/*
|
|
|
|
* num_available is the total number of samples available
|
|
|
|
* i.e. number of time points * number of channels.
|
|
|
|
*/
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
|
2016-10-08 16:39:06 +00:00
|
|
|
num_available * 2);
|
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
for (i = 0; i < num_available / 3; i++) {
|
|
|
|
/*
|
|
|
|
* Dirty hack to cover for 11 bit in fifo, 13 bit
|
|
|
|
* direct reading.
|
|
|
|
*
|
|
|
|
* In theory the bottom two bits are undefined.
|
|
|
|
* In reality they appear to always be 0.
|
|
|
|
*/
|
|
|
|
iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
|
|
|
|
}
|
2016-10-08 16:39:02 +00:00
|
|
|
}
|
2016-10-08 16:39:06 +00:00
|
|
|
error_ret:
|
|
|
|
mutex_unlock(&st->lock);
|
2016-10-08 16:39:02 +00:00
|
|
|
}
|
|
|
|
|
2009-08-18 17:06:25 +00:00
|
|
|
/**
|
2011-05-18 13:41:01 +00:00
|
|
|
* sca3000_event_handler() - handling ring and non ring events
|
2016-10-08 16:39:17 +00:00
|
|
|
* @irq: The irq being handled.
|
|
|
|
* @private: struct iio_device pointer for the device.
|
2009-08-18 17:06:25 +00:00
|
|
|
*
|
2014-01-13 21:28:00 +00:00
|
|
|
* Ring related interrupt handler. Depending on event, push to
|
|
|
|
* the ring buffer event chrdev or the event one.
|
|
|
|
*
|
2009-08-18 17:06:25 +00:00
|
|
|
* This function is complicated by the fact that the devices can signify ring
|
|
|
|
* and non ring events via the same interrupt line and they can only
|
|
|
|
* be distinguished via a read of the relevant status register.
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2011-05-18 13:41:01 +00:00
|
|
|
static irqreturn_t sca3000_event_handler(int irq, void *private)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-05-18 13:41:01 +00:00
|
|
|
struct iio_dev *indio_dev = private;
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2011-05-18 13:41:01 +00:00
|
|
|
int ret, val;
|
2016-03-09 18:05:49 +00:00
|
|
|
s64 last_timestamp = iio_get_time_ns(indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2014-01-13 21:28:00 +00:00
|
|
|
/*
|
|
|
|
* Could lead if badly timed to an extra read of status reg,
|
2009-08-18 17:06:25 +00:00
|
|
|
* but ensures no interrupt is missed.
|
|
|
|
*/
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
|
2011-05-18 13:41:01 +00:00
|
|
|
val = st->rx[0];
|
2009-08-18 17:06:25 +00:00
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
if (ret)
|
|
|
|
goto done;
|
|
|
|
|
2016-10-08 16:39:06 +00:00
|
|
|
sca3000_ring_int_process(val, indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
if (val & SCA3000_INT_STATUS_FREE_FALL)
|
2011-08-30 11:41:06 +00:00
|
|
|
iio_push_event(indio_dev,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_EVENT_CODE(IIO_ACCEL,
|
2010-10-08 11:14:03 +00:00
|
|
|
0,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_X_AND_Y_AND_Z,
|
2010-10-08 11:14:03 +00:00
|
|
|
IIO_EV_TYPE_MAG,
|
|
|
|
IIO_EV_DIR_FALLING),
|
2011-05-18 13:41:01 +00:00
|
|
|
last_timestamp);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
if (val & SCA3000_INT_STATUS_Y_TRIGGER)
|
2011-08-30 11:41:06 +00:00
|
|
|
iio_push_event(indio_dev,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_EVENT_CODE(IIO_ACCEL,
|
2010-10-08 11:14:03 +00:00
|
|
|
0,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_Y,
|
2010-10-08 11:14:03 +00:00
|
|
|
IIO_EV_TYPE_MAG,
|
|
|
|
IIO_EV_DIR_RISING),
|
2011-05-18 13:41:01 +00:00
|
|
|
last_timestamp);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
if (val & SCA3000_INT_STATUS_X_TRIGGER)
|
2011-08-30 11:41:06 +00:00
|
|
|
iio_push_event(indio_dev,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_EVENT_CODE(IIO_ACCEL,
|
2010-10-08 11:14:03 +00:00
|
|
|
0,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_X,
|
2010-10-08 11:14:03 +00:00
|
|
|
IIO_EV_TYPE_MAG,
|
|
|
|
IIO_EV_DIR_RISING),
|
2011-05-18 13:41:01 +00:00
|
|
|
last_timestamp);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
if (val & SCA3000_INT_STATUS_Z_TRIGGER)
|
2011-08-30 11:41:06 +00:00
|
|
|
iio_push_event(indio_dev,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_EVENT_CODE(IIO_ACCEL,
|
2010-10-08 11:14:03 +00:00
|
|
|
0,
|
2011-08-12 16:56:04 +00:00
|
|
|
IIO_MOD_Z,
|
2010-10-08 11:14:03 +00:00
|
|
|
IIO_EV_TYPE_MAG,
|
|
|
|
IIO_EV_DIR_RISING),
|
2011-05-18 13:41:01 +00:00
|
|
|
last_timestamp);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
|
|
|
done:
|
2011-05-18 13:41:01 +00:00
|
|
|
return IRQ_HANDLED;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
2020-07-17 16:55:24 +00:00
|
|
|
/*
|
2011-05-18 13:41:01 +00:00
|
|
|
* sca3000_read_event_config() what events are enabled
|
2020-07-17 16:55:24 +00:00
|
|
|
*/
|
2011-05-18 13:41:01 +00:00
|
|
|
static int sca3000_read_event_config(struct iio_dev *indio_dev,
|
2013-10-07 14:11:00 +00:00
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2011-05-18 13:41:01 +00:00
|
|
|
int ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
/* read current value of mode register */
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:08 +00:00
|
|
|
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
|
2016-10-08 16:39:08 +00:00
|
|
|
switch (chan->channel2) {
|
|
|
|
case IIO_MOD_X_AND_Y_AND_Z:
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
|
2016-10-08 16:39:08 +00:00
|
|
|
break;
|
|
|
|
case IIO_MOD_X:
|
|
|
|
case IIO_MOD_Y:
|
|
|
|
case IIO_MOD_Z:
|
|
|
|
/*
|
|
|
|
* Motion detection mode cannot run at the same time as
|
|
|
|
* acceleration data being read.
|
|
|
|
*/
|
2016-10-08 16:39:09 +00:00
|
|
|
if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
|
|
|
|
!= SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
|
2016-10-08 16:39:08 +00:00
|
|
|
ret = 0;
|
|
|
|
} else {
|
|
|
|
ret = sca3000_read_ctrl_reg(st,
|
|
|
|
SCA3000_REG_CTRL_SEL_MD_CTRL);
|
|
|
|
if (ret < 0)
|
|
|
|
goto error_ret;
|
|
|
|
/* only supporting logical or's for now */
|
2016-10-08 16:39:11 +00:00
|
|
|
ret = !!(ret & sca3000_addresses[chan->address][2]);
|
2016-10-08 16:39:08 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
2016-10-08 16:39:08 +00:00
|
|
|
|
2009-08-18 17:06:25 +00:00
|
|
|
error_ret:
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
2015-10-28 23:01:51 +00:00
|
|
|
|
2016-10-08 16:39:08 +00:00
|
|
|
static int sca3000_freefall_set_state(struct iio_dev *indio_dev, int state)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* read current value of mode register */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
2016-10-08 16:39:08 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2014-01-13 21:28:00 +00:00
|
|
|
/* if off and should be on */
|
2016-10-08 16:39:09 +00:00
|
|
|
if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
|
|
|
|
return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
|
|
|
|
st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
|
2009-08-18 17:06:25 +00:00
|
|
|
/* if on and should be off */
|
2016-10-08 16:39:09 +00:00
|
|
|
else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
|
|
|
|
return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
|
|
|
|
st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
|
2016-10-08 16:39:08 +00:00
|
|
|
else
|
|
|
|
return 0;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-08 16:39:08 +00:00
|
|
|
static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
|
|
|
|
int state)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-06-27 12:07:16 +00:00
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2011-05-18 13:41:01 +00:00
|
|
|
int ret, ctrlval;
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2014-01-13 21:28:00 +00:00
|
|
|
/*
|
|
|
|
* First read the motion detector config to find out if
|
|
|
|
* this axis is on
|
|
|
|
*/
|
2011-05-18 13:41:01 +00:00
|
|
|
ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
|
|
|
|
if (ret < 0)
|
2016-10-08 16:39:08 +00:00
|
|
|
return ret;
|
2011-05-18 13:41:01 +00:00
|
|
|
ctrlval = ret;
|
2014-01-13 21:28:00 +00:00
|
|
|
/* if off and should be on */
|
2016-10-08 16:39:08 +00:00
|
|
|
if (state && !(ctrlval & sca3000_addresses[axis][2])) {
|
2009-08-18 17:06:25 +00:00
|
|
|
ret = sca3000_write_ctrl_reg(st,
|
|
|
|
SCA3000_REG_CTRL_SEL_MD_CTRL,
|
2011-05-18 13:41:01 +00:00
|
|
|
ctrlval |
|
2016-10-08 16:39:08 +00:00
|
|
|
sca3000_addresses[axis][2]);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
2016-10-08 16:39:08 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
st->mo_det_use_count++;
|
2016-10-08 16:39:08 +00:00
|
|
|
} else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
|
2009-08-18 17:06:25 +00:00
|
|
|
ret = sca3000_write_ctrl_reg(st,
|
|
|
|
SCA3000_REG_CTRL_SEL_MD_CTRL,
|
2011-05-18 13:41:01 +00:00
|
|
|
ctrlval &
|
2016-10-08 16:39:08 +00:00
|
|
|
~(sca3000_addresses[axis][2]));
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
2016-10-08 16:39:08 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
st->mo_det_use_count--;
|
2011-05-18 13:41:01 +00:00
|
|
|
}
|
|
|
|
|
2009-08-18 17:06:25 +00:00
|
|
|
/* read current value of mode register */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
2016-10-08 16:39:08 +00:00
|
|
|
return ret;
|
2014-01-13 21:28:00 +00:00
|
|
|
/* if off and should be on */
|
2015-10-28 23:01:54 +00:00
|
|
|
if ((st->mo_det_use_count) &&
|
2016-10-08 16:39:09 +00:00
|
|
|
((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
|
|
|
|
!= SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
|
|
|
|
return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
|
|
|
|
(st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
|
|
|
|
| SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
|
2009-08-18 17:06:25 +00:00
|
|
|
/* if on and should be off */
|
2015-10-28 23:01:54 +00:00
|
|
|
else if (!(st->mo_det_use_count) &&
|
2016-10-08 16:39:09 +00:00
|
|
|
((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
|
|
|
|
== SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
|
|
|
|
return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
|
|
|
|
st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
|
2016-10-08 16:39:08 +00:00
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_write_event_config() - simple on off control for motion detector
|
|
|
|
* @indio_dev: IIO device instance specific structure. Data specific to this
|
|
|
|
* particular driver may be accessed via iio_priv(indio_dev).
|
|
|
|
* @chan: Description of the channel whose event we are configuring.
|
|
|
|
* @type: The type of event.
|
|
|
|
* @dir: The direction of the event.
|
|
|
|
* @state: Desired state of event being configured.
|
2016-10-08 16:39:08 +00:00
|
|
|
*
|
|
|
|
* This is a per axis control, but enabling any will result in the
|
|
|
|
* motion detector unit being enabled.
|
|
|
|
* N.B. enabling motion detector stops normal data acquisition.
|
|
|
|
* There is a complexity in knowing which mode to return to when
|
|
|
|
* this mode is disabled. Currently normal mode is assumed.
|
|
|
|
**/
|
|
|
|
static int sca3000_write_event_config(struct iio_dev *indio_dev,
|
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
int state)
|
|
|
|
{
|
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
|
|
|
switch (chan->channel2) {
|
|
|
|
case IIO_MOD_X_AND_Y_AND_Z:
|
|
|
|
ret = sca3000_freefall_set_state(indio_dev, state);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case IIO_MOD_X:
|
|
|
|
case IIO_MOD_Y:
|
|
|
|
case IIO_MOD_Z:
|
2016-10-08 16:39:11 +00:00
|
|
|
ret = sca3000_motion_detect_set_state(indio_dev,
|
|
|
|
chan->address,
|
2016-10-08 16:39:08 +00:00
|
|
|
state);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
2009-08-18 17:06:25 +00:00
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-08 16:39:02 +00:00
|
|
|
static inline
|
|
|
|
int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
|
|
|
|
{
|
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
2016-10-08 16:39:02 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
if (state) {
|
|
|
|
dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
|
|
|
|
ret = sca3000_write_reg(st,
|
2016-10-08 16:39:09 +00:00
|
|
|
SCA3000_REG_MODE_ADDR,
|
|
|
|
(st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
|
2016-10-08 16:39:02 +00:00
|
|
|
} else
|
|
|
|
ret = sca3000_write_reg(st,
|
2016-10-08 16:39:09 +00:00
|
|
|
SCA3000_REG_MODE_ADDR,
|
|
|
|
(st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
|
2016-10-08 16:39:02 +00:00
|
|
|
error_ret:
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_hw_ring_preenable() - hw ring buffer preenable function
|
|
|
|
* @indio_dev: structure representing the IIO device. Device instance
|
|
|
|
* specific state can be accessed via iio_priv(indio_dev).
|
2016-10-08 16:39:02 +00:00
|
|
|
*
|
|
|
|
* Very simple enable function as the chip will allows normal reads
|
|
|
|
* during ring buffer operation so as long as it is indeed running
|
|
|
|
* before we notify the core, the precise ordering does not matter.
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2016-10-08 16:39:02 +00:00
|
|
|
static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
|
|
|
|
{
|
2016-10-08 16:39:05 +00:00
|
|
|
int ret;
|
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
|
|
|
|
|
|
|
/* Enable the 50% full interrupt */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
|
2016-10-08 16:39:05 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_unlock;
|
|
|
|
ret = sca3000_write_reg(st,
|
2016-10-08 16:39:09 +00:00
|
|
|
SCA3000_REG_INT_MASK_ADDR,
|
|
|
|
st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
|
2016-10-08 16:39:05 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_unlock;
|
|
|
|
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
|
2016-10-08 16:39:02 +00:00
|
|
|
return __sca3000_hw_ring_state_set(indio_dev, 1);
|
2016-10-08 16:39:05 +00:00
|
|
|
|
|
|
|
error_unlock:
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
|
|
|
|
return ret;
|
2016-10-08 16:39:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
|
|
|
|
{
|
2016-10-08 16:39:05 +00:00
|
|
|
int ret;
|
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
ret = __sca3000_hw_ring_state_set(indio_dev, 0);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Disable the 50% full interrupt */
|
|
|
|
mutex_lock(&st->lock);
|
|
|
|
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
|
2016-10-08 16:39:05 +00:00
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
|
|
|
ret = sca3000_write_reg(st,
|
2016-10-08 16:39:09 +00:00
|
|
|
SCA3000_REG_INT_MASK_ADDR,
|
|
|
|
st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
|
2016-10-08 16:39:05 +00:00
|
|
|
unlock:
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return ret;
|
2016-10-08 16:39:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
|
|
|
|
.preenable = &sca3000_hw_ring_preenable,
|
|
|
|
.postdisable = &sca3000_hw_ring_postdisable,
|
|
|
|
};
|
|
|
|
|
2009-08-18 17:06:25 +00:00
|
|
|
/**
|
2016-10-08 16:39:17 +00:00
|
|
|
* sca3000_clean_setup() - get the device into a predictable state
|
|
|
|
* @st: Device instance specific private data structure
|
2009-08-18 17:06:25 +00:00
|
|
|
*
|
|
|
|
* Devices use flash memory to store many of the register values
|
|
|
|
* and hence can come up in somewhat unpredictable states.
|
|
|
|
* Hence reset everything on driver load.
|
2016-10-08 16:39:17 +00:00
|
|
|
*/
|
2009-08-18 17:06:25 +00:00
|
|
|
static int sca3000_clean_setup(struct sca3000_state *st)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
|
|
|
/* Ensure all interrupts have been acknowledged */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
|
|
|
|
/* Turn off all motion detection channels */
|
2011-05-18 13:41:01 +00:00
|
|
|
ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
|
|
|
|
if (ret < 0)
|
2009-08-18 17:06:25 +00:00
|
|
|
goto error_ret;
|
2011-05-18 13:41:01 +00:00
|
|
|
ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
|
|
|
|
ret & SCA3000_MD_CTRL_PROT_MASK);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
|
|
|
|
/* Disable ring buffer */
|
2011-05-18 13:41:01 +00:00
|
|
|
ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
|
2016-06-22 19:43:31 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error_ret;
|
2011-05-18 13:41:01 +00:00
|
|
|
ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
|
2016-10-08 16:39:09 +00:00
|
|
|
(ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
|
|
|
|
| SCA3000_REG_OUT_CTRL_BUF_X_EN
|
|
|
|
| SCA3000_REG_OUT_CTRL_BUF_Y_EN
|
|
|
|
| SCA3000_REG_OUT_CTRL_BUF_Z_EN
|
|
|
|
| SCA3000_REG_OUT_CTRL_BUF_DIV_4);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
/* Enable interrupts, relevant to mode and set up as active low */
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
ret = sca3000_write_reg(st,
|
2016-10-08 16:39:09 +00:00
|
|
|
SCA3000_REG_INT_MASK_ADDR,
|
|
|
|
(ret & SCA3000_REG_INT_MASK_PROT_MASK)
|
|
|
|
| SCA3000_REG_INT_MASK_ACTIVE_LOW);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
2014-01-13 21:28:00 +00:00
|
|
|
/*
|
|
|
|
* Select normal measurement mode, free fall off, ring off
|
|
|
|
* Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
|
|
|
|
* as that occurs in one of the example on the datasheet
|
|
|
|
*/
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
|
2011-05-18 13:41:01 +00:00
|
|
|
(st->rx[0] & SCA3000_MODE_PROT_MASK));
|
2009-08-18 17:06:25 +00:00
|
|
|
|
|
|
|
error_ret:
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-05-18 13:42:37 +00:00
|
|
|
static const struct iio_info sca3000_info = {
|
|
|
|
.attrs = &sca3000_attribute_group,
|
|
|
|
.read_raw = &sca3000_read_raw,
|
2016-09-13 19:14:14 +00:00
|
|
|
.write_raw = &sca3000_write_raw,
|
2016-10-08 16:39:08 +00:00
|
|
|
.read_event_value = &sca3000_read_event_value,
|
|
|
|
.write_event_value = &sca3000_write_event_value,
|
2013-12-07 10:45:00 +00:00
|
|
|
.read_event_config = &sca3000_read_event_config,
|
|
|
|
.write_event_config = &sca3000_write_event_config,
|
2011-05-18 13:42:37 +00:00
|
|
|
};
|
|
|
|
|
2012-11-19 18:21:57 +00:00
|
|
|
static int sca3000_probe(struct spi_device *spi)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-10-14 13:46:58 +00:00
|
|
|
int ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
struct sca3000_state *st;
|
2011-06-27 12:07:16 +00:00
|
|
|
struct iio_dev *indio_dev;
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2013-08-24 18:48:00 +00:00
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
|
|
|
if (!indio_dev)
|
|
|
|
return -ENOMEM;
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-06-29 19:50:48 +00:00
|
|
|
st = iio_priv(indio_dev);
|
2011-06-27 12:07:16 +00:00
|
|
|
spi_set_drvdata(spi, indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
st->us = spi;
|
|
|
|
mutex_init(&st->lock);
|
2011-05-18 13:41:01 +00:00
|
|
|
st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
|
|
|
|
->driver_data];
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-06-27 12:07:16 +00:00
|
|
|
indio_dev->name = spi_get_device_id(spi)->name;
|
2014-01-13 21:28:00 +00:00
|
|
|
indio_dev->info = &sca3000_info;
|
|
|
|
if (st->info->temp_output) {
|
|
|
|
indio_dev->channels = sca3000_channels_with_temp;
|
|
|
|
indio_dev->num_channels =
|
|
|
|
ARRAY_SIZE(sca3000_channels_with_temp);
|
|
|
|
} else {
|
|
|
|
indio_dev->channels = sca3000_channels;
|
|
|
|
indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
|
|
|
|
}
|
2011-06-27 12:07:16 +00:00
|
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2021-02-15 10:40:23 +00:00
|
|
|
ret = devm_iio_kfifo_buffer_setup(&spi->dev, indio_dev,
|
|
|
|
&sca3000_ring_setup_ops);
|
2018-04-08 19:44:15 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-10-14 13:46:58 +00:00
|
|
|
|
2011-10-12 09:57:33 +00:00
|
|
|
if (spi->irq) {
|
2011-05-18 13:41:01 +00:00
|
|
|
ret = request_threaded_irq(spi->irq,
|
|
|
|
NULL,
|
|
|
|
&sca3000_event_handler,
|
2012-07-02 08:54:45 +00:00
|
|
|
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
|
2011-05-18 13:41:01 +00:00
|
|
|
"sca3000",
|
2011-06-27 12:07:16 +00:00
|
|
|
indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
2016-10-08 16:39:15 +00:00
|
|
|
return ret;
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
ret = sca3000_clean_setup(st);
|
|
|
|
if (ret)
|
2011-05-18 13:41:01 +00:00
|
|
|
goto error_free_irq;
|
2016-10-08 16:39:14 +00:00
|
|
|
|
|
|
|
ret = sca3000_print_rev(indio_dev);
|
|
|
|
if (ret)
|
|
|
|
goto error_free_irq;
|
|
|
|
|
2016-10-08 16:39:15 +00:00
|
|
|
return iio_device_register(indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
error_free_irq:
|
2011-10-12 09:57:33 +00:00
|
|
|
if (spi->irq)
|
2011-06-27 12:07:16 +00:00
|
|
|
free_irq(spi->irq, indio_dev);
|
2016-10-08 16:39:15 +00:00
|
|
|
|
2009-08-18 17:06:25 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sca3000_stop_all_interrupts(struct sca3000_state *st)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&st->lock);
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
|
2009-08-18 17:06:25 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
2016-10-08 16:39:09 +00:00
|
|
|
ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
|
2011-05-18 13:41:01 +00:00
|
|
|
(st->rx[0] &
|
2016-10-08 16:39:09 +00:00
|
|
|
~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
|
|
|
|
SCA3000_REG_INT_MASK_RING_HALF |
|
|
|
|
SCA3000_REG_INT_MASK_ALL_INTS)));
|
2009-08-18 17:06:25 +00:00
|
|
|
error_ret:
|
2011-05-18 13:41:01 +00:00
|
|
|
mutex_unlock(&st->lock);
|
2009-08-18 17:06:25 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-01-23 17:52:01 +00:00
|
|
|
static void sca3000_remove(struct spi_device *spi)
|
2009-08-18 17:06:25 +00:00
|
|
|
{
|
2011-06-27 12:07:16 +00:00
|
|
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
|
|
|
struct sca3000_state *st = iio_priv(indio_dev);
|
2012-09-22 08:56:00 +00:00
|
|
|
|
2016-10-08 16:39:15 +00:00
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
|
2014-01-13 21:28:00 +00:00
|
|
|
/* Must ensure no interrupts can be generated after this! */
|
2012-09-22 08:56:00 +00:00
|
|
|
sca3000_stop_all_interrupts(st);
|
2011-10-12 09:57:33 +00:00
|
|
|
if (spi->irq)
|
2011-05-18 13:41:01 +00:00
|
|
|
free_irq(spi->irq, indio_dev);
|
2009-08-18 17:06:25 +00:00
|
|
|
}
|
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
static const struct spi_device_id sca3000_id[] = {
|
|
|
|
{"sca3000_d01", d01},
|
|
|
|
{"sca3000_e02", e02},
|
|
|
|
{"sca3000_e04", e04},
|
|
|
|
{"sca3000_e05", e05},
|
|
|
|
{}
|
|
|
|
};
|
2011-11-16 07:53:31 +00:00
|
|
|
MODULE_DEVICE_TABLE(spi, sca3000_id);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2011-05-18 13:41:01 +00:00
|
|
|
static struct spi_driver sca3000_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "sca3000",
|
|
|
|
},
|
|
|
|
.probe = sca3000_probe,
|
2012-11-19 18:21:38 +00:00
|
|
|
.remove = sca3000_remove,
|
2011-05-18 13:41:01 +00:00
|
|
|
.id_table = sca3000_id,
|
|
|
|
};
|
2011-11-16 09:13:39 +00:00
|
|
|
module_spi_driver(sca3000_driver);
|
2009-08-18 17:06:25 +00:00
|
|
|
|
2012-09-02 20:34:59 +00:00
|
|
|
MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
|
2009-08-18 17:06:25 +00:00
|
|
|
MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|