License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2010-02-04 18:59:27 +00:00
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/*
|
2013-10-17 22:35:27 +00:00
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* Intel MID PCI support
|
2010-02-04 18:59:27 +00:00
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* Copyright (c) 2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Moorestown has an interesting PCI implementation:
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* - configuration space is memory mapped (as defined by MCFG)
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* - Lincroft devices also have a real, type 1 configuration space
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* - Early Lincroft silicon has a type 1 access bug that will cause
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* a hang if non-existent devices are accessed
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* - some devices have the "fixed BAR" capability, which means
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* they can't be relocated or modified; check for that during
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* BAR sizing
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*
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* So, we use the MCFG space for all reads and writes, but also send
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* Lincroft writes to type 1 space. But only read/write if the device
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* actually exists, otherwise return all 1s for reads and bit bucket
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* the writes.
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*/
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/dmi.h>
|
2013-07-15 07:40:48 +00:00
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/smp.h>
|
2010-02-04 18:59:27 +00:00
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2021-02-11 13:40:03 +00:00
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#include <asm/cpu_device_id.h>
|
2010-02-04 18:59:27 +00:00
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#include <asm/segment.h>
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#include <asm/pci_x86.h>
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#include <asm/hw_irq.h>
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#include <asm/io_apic.h>
|
2021-02-11 13:40:03 +00:00
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#include <asm/intel-family.h>
|
2013-12-16 20:07:38 +00:00
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#include <asm/intel-mid.h>
|
2020-08-22 00:10:27 +00:00
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#include <asm/acpi.h>
|
2010-02-04 18:59:27 +00:00
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#define PCIE_CAP_OFFSET 0x100
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|
2015-07-29 09:16:47 +00:00
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/* Quirks for the listed devices */
|
2016-07-12 11:04:22 +00:00
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#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
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#define PCI_DEVICE_ID_INTEL_MRFLD_HSU 0x1191
|
2015-07-29 09:16:47 +00:00
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|
2010-02-04 18:59:27 +00:00
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/* Fixed BAR fields */
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#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
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#define PCI_FIXED_BAR_0_SIZE 0x04
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#define PCI_FIXED_BAR_1_SIZE 0x08
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#define PCI_FIXED_BAR_2_SIZE 0x0c
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#define PCI_FIXED_BAR_3_SIZE 0x10
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#define PCI_FIXED_BAR_4_SIZE 0x14
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#define PCI_FIXED_BAR_5_SIZE 0x1c
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|
2013-07-15 07:40:48 +00:00
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static int pci_soc_mode;
|
2012-02-13 12:59:37 +00:00
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|
2010-02-04 18:59:27 +00:00
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|
/**
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* fixed_bar_cap - return the offset of the fixed BAR cap if found
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* @bus: PCI bus
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* @devfn: device in question
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*
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* Look for the fixed BAR cap on @bus and @devfn, returning its offset
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* if found or 0 otherwise.
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*/
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static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
|
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|
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{
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int pos;
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u32 pcie_cap = 0, cap_data;
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pos = PCIE_CAP_OFFSET;
|
2010-02-24 17:42:50 +00:00
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if (!raw_pci_ext_ops)
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return 0;
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|
2010-02-04 18:59:27 +00:00
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while (pos) {
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if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
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devfn, pos, 4, &pcie_cap))
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return 0;
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|
2010-07-16 18:58:26 +00:00
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if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
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PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
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break;
|
2010-02-04 18:59:27 +00:00
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if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
|
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raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
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devfn, pos + 4, 4, &cap_data);
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if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
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return pos;
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}
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|
2010-07-16 18:58:26 +00:00
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pos = PCI_EXT_CAP_NEXT(pcie_cap);
|
2010-02-04 18:59:27 +00:00
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}
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return 0;
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}
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static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
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int reg, int len, u32 val, int offset)
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{
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u32 size;
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unsigned int domain, busnum;
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int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
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domain = pci_domain_nr(bus);
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busnum = bus->number;
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if (val == ~0 && len == 4) {
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unsigned long decode;
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raw_pci_ext_ops->read(domain, busnum, devfn,
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offset + 8 + (bar * 4), 4, &size);
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/* Turn the size into a decode pattern for the sizing code */
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if (size) {
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decode = size - 1;
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decode |= decode >> 1;
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decode |= decode >> 2;
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decode |= decode >> 4;
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decode |= decode >> 8;
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decode |= decode >> 16;
|
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decode++;
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decode = ~(decode - 1);
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} else {
|
2010-05-14 21:41:14 +00:00
|
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|
decode = 0;
|
2010-02-04 18:59:27 +00:00
|
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|
}
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/*
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* If val is all ones, the core code is trying to size the reg,
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* so update the mmconfig space with the real size.
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*
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* Note: this assumes the fixed size we got is a power of two.
|
|
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*/
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return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
|
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decode);
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}
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/* This is some other kind of BAR write, so just do it. */
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return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
|
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}
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/**
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|
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* type1_access_ok - check whether to use type 1
|
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* @bus: bus number
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* @devfn: device & function in question
|
2021-02-11 13:40:04 +00:00
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* @reg: configuration register offset
|
2010-02-04 18:59:27 +00:00
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*
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* If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
|
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* all, the we can go ahead with any reads & writes. If it's on a Lincroft,
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* but doesn't exist, avoid the access altogether to keep the chip from
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* hanging.
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*/
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static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
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{
|
2013-07-15 07:40:48 +00:00
|
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/*
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|
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* This is a workaround for A0 LNC bug where PCI status register does
|
2010-02-04 18:59:27 +00:00
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* not have new CAP bit set. can not be written by SW either.
|
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*
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* PCI header type in real LNC indicates a single function device, this
|
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* will prevent probing other devices under the same function in PCI
|
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* shim. Therefore, use the header type in shim instead.
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*/
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if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
|
2013-10-17 22:35:28 +00:00
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return false;
|
2013-05-20 16:20:21 +00:00
|
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if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
|
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|| devfn == PCI_DEVFN(0, 0)
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|| devfn == PCI_DEVFN(3, 0)))
|
2013-10-17 22:35:28 +00:00
|
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return true;
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|
return false; /* Langwell on others */
|
2010-02-04 18:59:27 +00:00
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}
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
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int size, u32 *value)
|
|
|
|
{
|
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if (type1_access_ok(bus->number, devfn, where))
|
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|
return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
|
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devfn, where, size, value);
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return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
|
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devfn, where, size, value);
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}
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static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
|
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{
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int offset;
|
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|
|
|
2013-07-15 07:40:48 +00:00
|
|
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/*
|
|
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* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
|
2010-02-04 18:59:27 +00:00
|
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* to ROM BAR return 0 then being ignored.
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*/
|
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if (where == PCI_ROM_ADDRESS)
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|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Devices with fixed BARs need special handling:
|
|
|
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* - BAR sizing code will save, write ~0, read size, restore
|
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* - so writes to fixed BARs need special handling
|
|
|
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* - other writes to fixed BAR devices should go through mmconfig
|
|
|
|
*/
|
|
|
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offset = fixed_bar_cap(bus, devfn);
|
|
|
|
if (offset &&
|
|
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(where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
|
|
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|
return pci_device_update_fixed(bus, devfn, where, size, value,
|
|
|
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offset);
|
|
|
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}
|
|
|
|
|
|
|
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/*
|
|
|
|
* On Moorestown update both real & mmconfig space
|
|
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* Note: early Lincroft silicon can't handle type 1 accesses to
|
|
|
|
* non-existent devices, so just eat the write in that case.
|
|
|
|
*/
|
|
|
|
if (type1_access_ok(bus->number, devfn, where))
|
|
|
|
return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
|
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devfn, where, size, value);
|
|
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return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
|
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|
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where, size, value);
|
|
|
|
}
|
|
|
|
|
2021-02-11 13:40:03 +00:00
|
|
|
static const struct x86_cpu_id intel_mid_cpu_ids[] = {
|
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|
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL),
|
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{}
|
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|
|
};
|
|
|
|
|
2013-10-17 22:35:29 +00:00
|
|
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static int intel_mid_pci_irq_enable(struct pci_dev *dev)
|
2010-02-04 18:59:27 +00:00
|
|
|
{
|
2021-02-11 13:40:03 +00:00
|
|
|
const struct x86_cpu_id *id;
|
2015-04-13 06:11:54 +00:00
|
|
|
struct irq_alloc_info info;
|
2020-10-24 21:35:19 +00:00
|
|
|
bool polarity_low;
|
2021-02-11 13:40:03 +00:00
|
|
|
u16 model = 0;
|
2015-07-29 09:16:48 +00:00
|
|
|
int ret;
|
2017-07-24 17:34:02 +00:00
|
|
|
u8 gsi;
|
2010-02-04 18:59:27 +00:00
|
|
|
|
2016-02-17 18:26:38 +00:00
|
|
|
if (dev->irq_managed && dev->irq > 0)
|
2014-10-27 05:21:42 +00:00
|
|
|
return 0;
|
|
|
|
|
2017-07-24 17:34:02 +00:00
|
|
|
ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-02-11 13:40:03 +00:00
|
|
|
id = x86_match_cpu(intel_mid_cpu_ids);
|
|
|
|
if (id)
|
|
|
|
model = id->model;
|
|
|
|
|
|
|
|
switch (model) {
|
|
|
|
case INTEL_FAM6_ATOM_SILVERMONT_MID:
|
2020-10-24 21:35:19 +00:00
|
|
|
polarity_low = false;
|
2015-07-29 09:16:47 +00:00
|
|
|
|
|
|
|
/* Special treatment for IRQ0 */
|
2017-07-24 17:34:02 +00:00
|
|
|
if (gsi == 0) {
|
x86/platform/intel_mid_pci: Rework IRQ0 workaround
On Intel Merrifield platform several PCI devices have a bogus configuration,
i.e. the IRQ0 had been assigned to few of them. These are PCI root bridge,
eMMC0, HS UART common registers, PWM, and HDMI. The actual interrupt line can
be allocated to one device exclusively, in our case to eMMC0, the rest should
cope without it and basically known drivers for them are not using interrupt
line at all.
Rework IRQ0 workaround, which was previously done to avoid conflict between
eMMC0 and HS UART common registers, to behave differently based on the device
in question, i.e. allocate interrupt line to eMMC0, but silently skip interrupt
allocation for the rest except HS UART common registers which are not used
anyway. With this rework IOSF MBI driver in particular would be used.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Fixes: 39d9b77b8deb ("x86/pci/intel_mid_pci: Work around for IRQ0 assignment")
Link: http://lkml.kernel.org/r/1465842481-136852-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-06-13 18:28:00 +00:00
|
|
|
/*
|
|
|
|
* Skip HS UART common registers device since it has
|
|
|
|
* IRQ0 assigned and not used by the kernel.
|
|
|
|
*/
|
2016-07-12 11:04:22 +00:00
|
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)
|
x86/platform/intel_mid_pci: Rework IRQ0 workaround
On Intel Merrifield platform several PCI devices have a bogus configuration,
i.e. the IRQ0 had been assigned to few of them. These are PCI root bridge,
eMMC0, HS UART common registers, PWM, and HDMI. The actual interrupt line can
be allocated to one device exclusively, in our case to eMMC0, the rest should
cope without it and basically known drivers for them are not using interrupt
line at all.
Rework IRQ0 workaround, which was previously done to avoid conflict between
eMMC0 and HS UART common registers, to behave differently based on the device
in question, i.e. allocate interrupt line to eMMC0, but silently skip interrupt
allocation for the rest except HS UART common registers which are not used
anyway. With this rework IOSF MBI driver in particular would be used.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Fixes: 39d9b77b8deb ("x86/pci/intel_mid_pci: Work around for IRQ0 assignment")
Link: http://lkml.kernel.org/r/1465842481-136852-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-06-13 18:28:00 +00:00
|
|
|
return -EBUSY;
|
2015-07-29 09:16:47 +00:00
|
|
|
/*
|
|
|
|
* TNG has IRQ0 assigned to eMMC controller. But there
|
|
|
|
* are also other devices with bogus PCI configuration
|
|
|
|
* that have IRQ0 assigned. This check ensures that
|
x86/platform/intel_mid_pci: Rework IRQ0 workaround
On Intel Merrifield platform several PCI devices have a bogus configuration,
i.e. the IRQ0 had been assigned to few of them. These are PCI root bridge,
eMMC0, HS UART common registers, PWM, and HDMI. The actual interrupt line can
be allocated to one device exclusively, in our case to eMMC0, the rest should
cope without it and basically known drivers for them are not using interrupt
line at all.
Rework IRQ0 workaround, which was previously done to avoid conflict between
eMMC0 and HS UART common registers, to behave differently based on the device
in question, i.e. allocate interrupt line to eMMC0, but silently skip interrupt
allocation for the rest except HS UART common registers which are not used
anyway. With this rework IOSF MBI driver in particular would be used.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Fixes: 39d9b77b8deb ("x86/pci/intel_mid_pci: Work around for IRQ0 assignment")
Link: http://lkml.kernel.org/r/1465842481-136852-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-06-13 18:28:00 +00:00
|
|
|
* eMMC gets it. The rest of devices still could be
|
|
|
|
* enabled without interrupt line being allocated.
|
2015-07-29 09:16:47 +00:00
|
|
|
*/
|
2016-07-12 11:04:22 +00:00
|
|
|
if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)
|
x86/platform/intel_mid_pci: Rework IRQ0 workaround
On Intel Merrifield platform several PCI devices have a bogus configuration,
i.e. the IRQ0 had been assigned to few of them. These are PCI root bridge,
eMMC0, HS UART common registers, PWM, and HDMI. The actual interrupt line can
be allocated to one device exclusively, in our case to eMMC0, the rest should
cope without it and basically known drivers for them are not using interrupt
line at all.
Rework IRQ0 workaround, which was previously done to avoid conflict between
eMMC0 and HS UART common registers, to behave differently based on the device
in question, i.e. allocate interrupt line to eMMC0, but silently skip interrupt
allocation for the rest except HS UART common registers which are not used
anyway. With this rework IOSF MBI driver in particular would be used.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Fixes: 39d9b77b8deb ("x86/pci/intel_mid_pci: Work around for IRQ0 assignment")
Link: http://lkml.kernel.org/r/1465842481-136852-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-06-13 18:28:00 +00:00
|
|
|
return 0;
|
2015-07-29 09:16:47 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2020-10-24 21:35:19 +00:00
|
|
|
polarity_low = true;
|
2015-07-29 09:16:47 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-10-24 21:35:19 +00:00
|
|
|
ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity_low);
|
2010-02-04 18:59:27 +00:00
|
|
|
|
2013-07-15 07:40:48 +00:00
|
|
|
/*
|
|
|
|
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
|
2010-02-04 18:59:27 +00:00
|
|
|
* IOAPIC RTE entries, so we just enable RTE for the device.
|
|
|
|
*/
|
2017-07-24 17:34:02 +00:00
|
|
|
ret = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info);
|
2015-07-29 09:16:48 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2014-06-09 08:19:56 +00:00
|
|
|
|
2017-07-24 17:34:02 +00:00
|
|
|
dev->irq = ret;
|
2014-10-27 05:21:42 +00:00
|
|
|
dev->irq_managed = 1;
|
|
|
|
|
2010-02-04 18:59:27 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-06-09 08:20:09 +00:00
|
|
|
static void intel_mid_pci_irq_disable(struct pci_dev *dev)
|
|
|
|
{
|
2016-02-17 18:26:42 +00:00
|
|
|
if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
|
|
|
|
dev->irq > 0) {
|
2014-06-09 08:20:09 +00:00
|
|
|
mp_unmap_irq(dev->irq);
|
2014-10-27 05:21:42 +00:00
|
|
|
dev->irq_managed = 0;
|
|
|
|
}
|
2014-06-09 08:20:09 +00:00
|
|
|
}
|
|
|
|
|
2017-09-18 16:24:55 +00:00
|
|
|
static const struct pci_ops intel_mid_pci_ops __initconst = {
|
2010-02-04 18:59:27 +00:00
|
|
|
.read = pci_read,
|
|
|
|
.write = pci_write,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
2013-10-17 22:35:29 +00:00
|
|
|
* intel_mid_pci_init - installs intel_mid_pci_ops
|
2010-02-04 18:59:27 +00:00
|
|
|
*
|
|
|
|
* Moorestown has an interesting PCI implementation (see above).
|
|
|
|
* Called when the early platform detection installs it.
|
|
|
|
*/
|
2013-10-17 22:35:29 +00:00
|
|
|
int __init intel_mid_pci_init(void)
|
2010-02-04 18:59:27 +00:00
|
|
|
{
|
2013-07-15 07:40:48 +00:00
|
|
|
pr_info("Intel MID platform detected, using MID PCI ops\n");
|
2010-02-04 18:59:27 +00:00
|
|
|
pci_mmcfg_late_init();
|
2013-10-17 22:35:29 +00:00
|
|
|
pcibios_enable_irq = intel_mid_pci_irq_enable;
|
2014-06-09 08:20:09 +00:00
|
|
|
pcibios_disable_irq = intel_mid_pci_irq_disable;
|
2013-10-17 22:35:29 +00:00
|
|
|
pci_root_ops = intel_mid_pci_ops;
|
2012-02-13 12:59:37 +00:00
|
|
|
pci_soc_mode = 1;
|
2010-02-04 18:59:27 +00:00
|
|
|
/* Continue with standard init */
|
2018-01-17 17:34:08 +00:00
|
|
|
acpi_noirq_set();
|
2010-02-04 18:59:27 +00:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2013-07-15 07:40:48 +00:00
|
|
|
/*
|
|
|
|
* Langwell devices are not true PCI devices; they are not subject to 10 ms
|
|
|
|
* d3 to d0 delay required by PCI spec.
|
2012-02-13 12:59:00 +00:00
|
|
|
*/
|
2012-12-21 22:02:53 +00:00
|
|
|
static void pci_d3delay_fixup(struct pci_dev *dev)
|
2012-02-13 12:59:00 +00:00
|
|
|
{
|
2013-07-15 07:40:48 +00:00
|
|
|
/*
|
|
|
|
* PCI fixups are effectively decided compile time. If we have a dual
|
|
|
|
* SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
|
|
|
|
*/
|
|
|
|
if (!pci_soc_mode)
|
|
|
|
return;
|
|
|
|
/*
|
|
|
|
* True PCI devices in Lincroft should allow type 1 access, the rest
|
|
|
|
* are Langwell fake PCI devices.
|
2012-02-13 12:59:00 +00:00
|
|
|
*/
|
|
|
|
if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
|
|
|
|
return;
|
2020-07-30 21:08:48 +00:00
|
|
|
dev->d3hot_delay = 0;
|
2012-02-13 12:59:00 +00:00
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
|
|
|
|
|
2016-07-05 20:09:07 +00:00
|
|
|
static void mid_power_off_one_device(struct pci_dev *dev)
|
2012-02-13 12:59:00 +00:00
|
|
|
{
|
2016-06-14 18:29:45 +00:00
|
|
|
u16 pmcsr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Update current state first, otherwise PCI core enforces PCI_D0 in
|
|
|
|
* pci_set_power_state() for devices which status was PCI_UNKNOWN.
|
|
|
|
*/
|
|
|
|
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
|
|
|
|
dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);
|
|
|
|
|
2012-06-23 02:23:50 +00:00
|
|
|
pci_set_power_state(dev, PCI_D3hot);
|
2012-02-13 12:59:00 +00:00
|
|
|
}
|
2016-06-14 18:29:45 +00:00
|
|
|
|
2016-07-05 20:09:07 +00:00
|
|
|
static void mid_power_off_devices(struct pci_dev *dev)
|
2016-06-14 18:29:45 +00:00
|
|
|
{
|
|
|
|
int id;
|
|
|
|
|
|
|
|
if (!pci_soc_mode)
|
|
|
|
return;
|
|
|
|
|
|
|
|
id = intel_mid_pwr_get_lss_id(dev);
|
|
|
|
if (id < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This sets only PMCSR bits. The actual power off will happen in
|
|
|
|
* arch/x86/platform/intel-mid/pwr.c.
|
|
|
|
*/
|
2016-07-05 20:09:07 +00:00
|
|
|
mid_power_off_one_device(dev);
|
2016-06-14 18:29:45 +00:00
|
|
|
}
|
|
|
|
|
2016-07-05 20:09:07 +00:00
|
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices);
|
2012-02-13 12:59:00 +00:00
|
|
|
|
2010-02-04 18:59:27 +00:00
|
|
|
/*
|
|
|
|
* Langwell devices reside at fixed offsets, don't try to move them.
|
|
|
|
*/
|
2012-12-21 22:02:53 +00:00
|
|
|
static void pci_fixed_bar_fixup(struct pci_dev *dev)
|
2010-02-04 18:59:27 +00:00
|
|
|
{
|
|
|
|
unsigned long offset;
|
|
|
|
u32 size;
|
|
|
|
int i;
|
|
|
|
|
2012-02-13 12:59:37 +00:00
|
|
|
if (!pci_soc_mode)
|
|
|
|
return;
|
|
|
|
|
2010-05-14 20:55:57 +00:00
|
|
|
/* Must have extended configuration space */
|
|
|
|
if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
|
|
|
|
return;
|
|
|
|
|
2010-02-04 18:59:27 +00:00
|
|
|
/* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
|
|
|
|
offset = fixed_bar_cap(dev->bus, dev->devfn);
|
|
|
|
if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
|
|
|
|
PCI_DEVFN(2, 2) == dev->devfn)
|
|
|
|
return;
|
|
|
|
|
2019-09-27 23:43:08 +00:00
|
|
|
for (i = 0; i < PCI_STD_NUM_BARS; i++) {
|
2010-02-04 18:59:27 +00:00
|
|
|
pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
|
|
|
|
dev->resource[i].end = dev->resource[i].start + size - 1;
|
|
|
|
dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);
|